74LVC38AD,118

74LVC38A Quad 2-input NAND gate; open-drain Rev. 4 — 4 November 2011 Product data sheet 1. General description The 74LVC38A provides four 2-input NAND functions. The outputs are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits       5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 5.5 V CMOS low power consumption Direct interface with TTL levels Open-drain outputs Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V  JESD8-5A (2.3 V to 2.7 V  JESD8-C/JESD36 (2.7 V to 3.6 V  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC38AD 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVC38ADB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVC38APW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVC38ABQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5  3  0.85 mm SOT762-1 74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 4. Functional diagram 1 & 3 & 6 & 8 & 11 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 3 1Y 4 5 6 2Y 9 3Y 8 4Y 11 10 12 13 mna698 mna697 Fig 1. Logic symbol Fig 2. IEC logic symbol Y A B GND mna699 Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning 74LVC38A 1A 14 VCC 74LVC38A terminal 1 index area 1 14 VCC 1B 2 13 4B 1B 2 13 4B 1Y 3 12 4A 1Y 3 12 4A 2A 4 11 4Y 2B 5 2Y 6 1 1A 5 10 3B 2Y 6 9 3A GND 7 8 3Y GND(1) 10 3B 9 8 2B 3Y 11 4Y 7 4 GND 2A 3A 001aad039 Transparent top view 001aad038 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO14 and (T)SSOP14 74LVC38A Product data sheet Fig 5. Pin configuration for DHVQFN14 All information provided in this document is subject to legal disclaimers. Rev. 4 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 15 74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function selection[1] Input Output nA nB nY L L Z L H Z H L Z H H L [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current Conditions Min Max Unit 0.5 +6.5 V 50 - mA [1] 0.5 +6.5 V VI < 0 VI input voltage IOK output clamping current VO < 0 50 - mA VO output voltage active mode [2] 0.5 +6.5 V high-impedance mode [2] 0.5 +6.5 V - 50 mA IO output current ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot VO = 0 V to VCC Tamb = 40 C to +125 C [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. [3] For (T)SSOP14 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 74LVC38A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 15 74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Min Typ Max Unit 1.65 - 5.5 V functional 1.2 - - V 0 - 5.5 V active mode 0 - VCC V high-impedance mode 0 - 5.5 V in free air 40 - +125 C 0 - 20 ns/V 0 - 10 ns/V Tamb ambient temperature t/V input transition rise and fall VCC = 1.65 V to 2.7 V rate VCC = 2.7 V to 3.6 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL HIGH-level input voltage Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V 0.65  VCC - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7  VCC - - 0.7  VCC - V - - 0.12 - 0.12 V - - 0.35  VCC - 0.35  VCC V - - 0.7 - 0.7 V - 0.8 V LOW-level input VCC = 1.2 V voltage VCC = 1.65 V to 1.95 V LOW-level output voltage 40 C to +125 C VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VOL Typ[1] VCC = 2.7 V to 3.6 V - - 0.8 VCC = 4.5 V to 5.5 V - - 0.30  VCC - 0.30  VCC V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.20 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.8 V - 0.1 5 - 20 A VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V IOZ OFF-state output current VI = VIH; VO = 5.5 V or GND; VCC = 1.65 V to 5.5 V 0.1 5 - 20 A IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V 0.1 10 - 20 A 74LVC38A Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 4 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 15 74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Typ[1] Min 40 C to +125 C Max Min Unit Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - 0.1 10 - 40 A ICC additional supply current per input pin; VI = VCC  0.6 V; IO = 0 A; VCC = 2.7 V to 5.5 V - 5 500 - 5000 A CI input capacitance VCC = 0 V to 5.5 V; VI = GND to VCC - 4.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter tPZL tPLZ OFF-state to LOW propagation delay LOW to OFF-state propagation delay 40 C to +85 C Conditions Min Max Min Max - 5.7 - - - ns VCC = 1.65 V to 1.95 V 1.0 2.6 6.0 1.0 6.9 ns VCC = 2.3 V to 2.7 V 0.5 1.8 3.3 0.5 3.8 ns VCC = 2.7 V 0.5 1.7 2.9 0.5 4.0 ns VCC = 3.0 V to 3.6 V 0.5 1.8 3.0 0.5 4.0 ns - 5.7 - - - ns nA, nB to nY; see Figure 6 VCC = 1.2 V nA, nB to nY; see Figure 6 VCC = 1.2 V VCC = 1.65 V to 1.95 V 1.0 2.7 6.0 1.0 6.9 ns VCC = 2.3 V to 2.7 V 0.5 1.5 3.3 0.5 3.8 ns VCC = 2.7 V 1.0 2.6 3.8 1.0 5.0 ns 1.0 2.3 3.6 1.0 4.5 ns - - 1.0 - 1.5 ns VCC = 3.0 V to 3.6 V tsk(o) output skew time 74LVC38A Product data sheet 40 C to +125 C Unit Typ[1] [2] All information provided in this document is subject to legal disclaimers. Rev. 4 — 4 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 15 74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter CPD 40 C to +85 C Conditions power dissipation capacitance per gate; VI = GND to VCC 40 C to +125 C Unit Min Typ[1] Max Min Max [3] VCC = 1.65 V to 1.95 V - 6.2 - - - pF VCC = 2.3 V to 2.7 V - 9.7 - - - pF VCC = 3.0 V to 3.6 V - 12.9 - - - pF [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL  VCC2  fo) = sum of the outputs 11. AC waveforms VI nA, nB input VM GND t PLZ t PZL VCC nY output VM VX VOL mna700 Measurement points are given in Table 8 VOL is a typical output voltage level that occurs with the output load. Fig 6. Table 8. The input nA, nB to output nY propagation delays Measurement points Supply voltage Input Output VCC VM VX