74LVC3GU04

74LVC3GU04 Triple inverter Rev. 05 — 5 October 2007 Product data sheet 1. General description The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered output. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. 2. Features I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V ±24 mA output drive at VCC = 3.0 V CMOS low power consumption Latch-up performance exceeds 250 mA Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C. I I I I I I 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC3GU04DP 74LVC3GU04DC 74LVC3GU04GT −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name TSSOP8 VSSOP8 XSON8 XQFN8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm Version SOT505-2 SOT765-1 SOT833-1 SOT902-1 Type number 74LVC3GU04GM −40 °C to +125 °C NXP Semiconductors 74LVC3GU04 Triple inverter 4. Marking Table 2. Marking codes Marking code VU04 VU4 VU4 VU4 Type number 74LVC3GU04DP 74LVC3GU04DC 74LVC3GU04GT 74LVC3GU04GM 5. Functional diagram 1 1 7 1 1A 1Y 7 3 1 5 3 2A 2Y 5 1 6 3A 3Y 2 6 2 mna720 mna721 Fig 1. Logic symbol Fig 2. IEC logic symbol VCC VCC 100 Ω A Y mna636 Fig 3. Logic diagram (one gate) 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 2 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 6. Pinning information 6.1 Pinning 74LVC3GU04 1A 3Y 2A GND 1 2 3 4 mnb120 8 7 6 5 VCC 1Y 3A 2Y Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74LVC3GU04 74LVC3GU04 1A 1 8 VCC terminal 1 index area 1Y 1 VCC 8 7 1A 3Y 2 7 1Y 3A 2 6 3Y 2A 3 6 3A 2Y 3 4 5 2A GND GND 4 5 2Y 001aag056 001aac021 Transparent top view Transparent top view Fig 5. Pin configuration SOT833-1 (XSON8) Fig 6. Pin configuration SOT902-1 (XQFN8) 6.2 Pin description Table 3. Pin description Pin SOT505-2, SOT765-1, SOT833-1 nA nY GND VCC 1, 3, 6 7, 5, 2 4 8 SOT902-1 7, 5, 2 1, 3, 6 4 8 data input data output ground (0 V) supply voltage Description Symbol (n = 1, 2, 3) 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 3 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 7. Functional description Table 4. Input nA L H [1] H = HIGH voltage level; L = LOW voltage level Function table[1] Output nY H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO ICC IGND Ptot Tstg [1] [2] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current supply current ground current total power dissipation storage temperature Conditions [1] Min −0.5 −0.5 −0.5 −50 −100 Max +6.5 +6.5 VCC + 0.5 ±50 ±50 100 250 +150 Unit V V V mA mA mA mA mA mW °C Active mode VI < 0 V VO > VCC or VO < 0 V VO = 0 V to VCC [1] Tamb = −40 °C to +125 °C [2] −65 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Active mode Power-down mode; VCC = 0 V Conditions Min 1.65 0 0 0 −40 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V °C ns/V ns/V 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 4 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage HIGH-level output voltage Conditions VCC = 1.65 V to 5.5 V VCC = 1.65 V to 5.5 V VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II ICC CI VIH VIL VOH input leakage current supply current input capacitance HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 1.65 V to 5.5 V VCC = 1.65 V to 5.5 V VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VCC − 0.1 0.95 1.7 1.9 2.0 3.4 V V V V V V VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A 0.8 × VCC ±0.1 0.1 5 0.1 0.45 0.3 0.4 0.55 0.55 ±5 10 0.2 × VCC V V V V V V µA µA pF V V VCC − 0.1 1.2 1.9 2.2 2.3 3.8 V V V V V V Min Typ[1] Max Unit V Tamb = −40 °C to +85 °C 0.75 × VCC 0.25 × VCC V Tamb = −40 °C to +125 °C 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 5 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOL Parameter LOW-level output voltage Conditions VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V II ICC input leakage current supply current VI = 5.5 V or GND; VCC = 0 V to 5.5 V VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A 0.1 0.70 0.45 0.60 0.80 0.80 ±20 40 V V V V V V µA µA Min Typ[1] Max Unit [1] All typical values are measured at Tamb = 25 °C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 2.3 1.8 2.6 2.3 1.7 7 Max 5.0 4.0 4.5 3.7 3.0 - −40 °C to +125 °C Min 0.5 0.3 0.3 0.3 0.3 Max 6.3 4.0 5.6 4.5 3.8 - Unit propagation delay nA to nY; see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 0.5 0.3 0.3 0.3 0.3 [3] ns ns ns ns ns pF CPD power dissipation capacitance VI = GND to VCC; VCC = 3.3 V - [1] [2] [3] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 6 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 12. Waveforms VI nA input GND t PHL VOH RT CL RL VM VM VI VEXT VCC t PLH VO DUT RL G nY output VOL VM VM mna344 mna616 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. The input (nA) to output (nY) propagation delays Table 9. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr = t f ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Measurement points Input VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Fig 8. Load circuitry for switching times Supply voltage Output VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Supply voltage Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 7 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 13. Additional characteristics Rbias = 560 kΩ VCC 0.47 µF input output 100 µF VI (f = 1 kHz) A IO GND mna050 ∆I O g fs = --------∆V I VO is constant. Fig 9. Test set-up for measuring forward transconductance 160 gfs (mA/V) 120 mnb108 80 40 0 0 1 2 3 4 5 6 VCC (V) Tamb = 25 °C. Fig 10. Typical forward transconductance as a function of supply voltage 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 8 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 14. Application information Some applications for the 74LVC3GU04 are: • Linear amplifier (see Figure 11) • Crystal oscillator (see Figure 12). Remark: All values given are typical values unless otherwise specified. R2 VCC 1 µF R1 U04 ZL mna052 ZL > 10 kΩ R1 ≥ 3 kΩ R2 ≤ 1 MΩ Open loop gain: Gol = 20 Voltage gain: G ol G v = – --------------------------------------R1 1 + ------ ( 1 + G ol ) R2 Vo(p-p) = VCC − 1.5 V centered at 0.5 × VCC Unity gain bandwidth product is 5 MHz. Fig 11. Linear amplifier application R1 R2 U04 C1 C2 out mna053 C1 = 47 pF C2 = 22 pF R1 = 1 MΩ to 10 MΩ R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC = 2 mA at VCC = 3.3 V and f = 10 MHz). Fig 12. Crystal oscillator application 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 9 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 13. Package outline SOT505-2 (TSSOP8) 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 10 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 14. Package outline SOT765-1 (VSSOP8) 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 11 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 15. Package outline SOT833-1 (XSON8) 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 12 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-16 05-11-25 Fig 16. Package outline SOT902-1 (XQFN8) 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 13 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 16. Abbreviations Table 11. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 17. Revision history Table 12. Revision history Release date 20071005 Data sheet status Product data sheet Change notice Supersedes 74LVC3GU04_4 Document ID 74LVC3GU04_5 Modifications: 74LVC3GU04_4 74LVC3GU04_3 74LVC3GU04_2 74LVC3GU04_1 • In Section 10 “Static characteristics”, changed conditions for input leakage and supply current. Product data sheet Product data sheet Product data sheet Product data sheet 74LVC3GU04_3 74LVC3GU04_2 74LVC3GU04_1 - 20070315 20050201 20041027 20040512 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 14 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. 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However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC3GU04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 15 of 16 NXP Semiconductors 74LVC3GU04 Triple inverter 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional characteristics . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 October 2007 Document identifier: 74LVC3GU04_5