74LVC574ADB,118

74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Rev. 7.1 — 2 November 2023 Product data sheet 1. General description The 74LVC574A is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • Wide supply voltage range from 1.2 to 3.6 V CMOS low power consumption Direct interface with TTL levels Overvoltage tolerant inputs to 5.5 V High-impedance when VCC = 0 V 8-bit positive edge-triggered register Independent register and 3-state buffer operation Flow-through pin-out architecture IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version -40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVC574APW -40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVC574ABQ DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 74LVC574AD -40 °C to +125 °C SOT764-1 4. Functional diagram 11 C1 1 11 2 3 4 5 6 7 8 9 2 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 OE 1 Fig. 1. 19 D2 Q2 17 17 4 17 6 D4 16 5 16 7 D5 15 6 15 8 D6 Q6 13 9 D7 Q7 12 7 14 8 13 11 CP 9 12 1 OE 12 FF1 to FF8 D1 D Q D3 D CP Q CP FF2 Q Q5 14 Q D6 D CP FF4 Functional diagram D5 D CP FF3 Fig. 3. D4 D Q4 15 mna800 IEC logic symbol D2 Q3 16 3-STATE OUTPUTS mna446 Fig. 2. FF1 Q1 18 4 5 13 CP Q0 19 D1 18 14 Q D0 3 3 18 mna798 D0 19 1D 2 D3 Logic diagram D EN Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna801 Fig. 4. Logic diagram 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 2 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 5. Pinning information 5.1. Pinning D package SOT163-1 (SO20) OE 1 20 VCC D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 CP aaa-035109 1 PW package SOT360-1 (TSSOP20) OE terminal 1 index area OE 1 20 VCC D0 2 19 Q0 20 VCC BQ package SOT764-1 (DHVQFN20) D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 5 16 Q3 D1 3 18 Q1 D3 D2 4 17 Q2 D4 6 15 Q4 D3 5 16 Q3 7 15 Q4 14 Q5 D4 6 D5 D5 7 14 Q5 D6 8 D6 8 13 Q6 D7 9 D7 9 12 Q7 GND 10 11 CP GND(1) CP 11 12 Q7 GND 10 aaa-035110 13 Q6 aaa-035111 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 5.2. Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) CP 11 clock input (LOW to HIGH; edge triggered) D0, D1, D2, D3, D4, D5, D6, D7 2, 3, 4, 5, 6, 7, 8, 9 data input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 19, 18, 17, 16, 15, 14, 13, 12 data output GND 10 ground (0 V) VCC 20 supply voltage 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 3 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 6. Functional description Table 3. Functional table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition; ↑ = LOW to HIGH clock transition; Z = high-impedance OFF-state Operating modes Load and read register Load register and disable outputs Input Output OE CP Dn Internal flip-flop L ↑ l L L L ↑ h H H H ↑ l L Z H ↑ h H Z Qn 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 VO output voltage output HIGH or LOW state IO output current VO = 0 V to VCC ICC IGND Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA -0.5 VCC + 0.5 - ±50 mA supply current - 100 mA ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] [3] VI < 0 Min [1] Tamb = -40 °C to +125 °C [2] [3] mA V The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SOT163-1 (SO20) package: Ptot derates linearly with 12.3 mW/K above 109 °C. For SOT360-1 (TSSOP20) package: Ptot derates linearly with 10.0 mW/K above 100 °C. For SOT764-1 (DHVQFN20) package: Ptot derates linearly with 12.9 mW/K above 111 °C. 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 4 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V -40 - +125 °C supply voltage functional VI input voltage VO output voltage Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL II Conditions -40 °C to +85 °C VCC = 1.2 V HIGH-level input voltage V = 1.65 V to 1.95 V CC LOW-level output voltage Product data sheet Typ[1] Max Min Max 1.08 - - 1.08 - V - - 0.65 × VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - - 0.12 - 0.12 V - - 0.35 × VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V 0.35 × VCC V VCC - 0.2 - - VCC - 0.3 - V IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 μA; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - ±0.1 ±5 - ±20 μA VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 3.6 V VI = VIH or VIL input leakage VCC = 3.6 V; VI = 5.5 V or GND current 74LVC574A Min Unit 0.65 × VCC VCC = 1.2 V LOW-level input voltage V = 1.65 V to 1.95 V CC HIGHlevel output voltage -40 °C to +125 °C All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 5 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Min Typ[1] Max Min Max Unit IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND - 0.1 ±10 - ±20 μA IOFF power-off leakage supply VCC = 0 V; VI or VO = 5.5 V - 0.1 ±10 - ±20 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 μA ΔICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 5 500 - 5000 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 8. Symbol Parameter tpd Conditions -40 °C to +85 °C Max Min Max - 17.0 - - - ns VCC = 1.65 V to 1.95 V 4.6 6.4 13.1 4.6 15.1 ns VCC = 2.3 V to 2.7 V 2.6 3.9 7.9 2.6 9.1 ns VCC = 2.7 V 1.5 3.7 8.0 1.5 10.0 ns VCC = 3.0 V to 3.6 V 1.5 3.5 7.0 1.5 9.0 ns - 19.0 - - - ns VCC = 1.65 V to 1.95 V 1.5 7.0 17.1 1.5 19.8 ns VCC = 2.3 V to 2.7 V 1.5 4.0 9.4 1.5 10.9 ns VCC = 2.7 V 1.5 4.1 8.5 1.5 11.0 ns VCC = 3.0 V to 3.6 V 1.5 3.2 7.5 1.5 9.5 ns propagation delay CP to Qn; see Fig. 5 enable time [2] OE to Qn; see Fig. 7 [2] VCC = 1.2 V tdis disable time OE to Qn; see Fig. 7 VCC = 1.2 V tW pulse width 74LVC574A Product data sheet Unit Typ [1] VCC = 1.2 V ten -40 °C to +125 °C Min [2] - 9.0 - - - ns VCC = 1.65 V to 1.95 V 2.5 4.1 10.1 2.5 11.6 ns VCC = 2.3 V to 2.7 V 1.0 2.3 5.7 1.0 6.6 ns VCC = 2.7 V 1.5 3.1 6.5 1.5 8.5 ns VCC = 3.0 V to 3.6 V 1.5 2.9 6.0 1.5 7.5 ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.3 - - 3.3 - ns VCC = 3.0 V to 3.6 V 3.3 1.7 - 3.3 - ns clock HIGH or LOW; see Fig. 5 All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 6 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Symbol Parameter tsu set-up time th hold time fmax maximum frequency Conditions -40 °C to +85 °C Typ [1] Max Min Max VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 2.0 - - 2.0 - ns VCC = 3.0 V to 3.6 V 2.0 0.3 - 2.0 - ns VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns VCC = 2.7 V 1.5 - - 1.5 - ns VCC = 3.0 V to 3.6 V +1.5 -0.2 - +1.5 - ns VCC = 1.65 V to 1.95 V 100 - - 80 - MHz VCC = 2.3 V to 2.7 V 125 - - 100 - MHz VCC = 2.7 V 150 - - 120 - MHz VCC = 3.0 V to 3.6 V 150 200 - 120 - MHz - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 11.2 - - - pF VCC = 2.3 V to 2.7 V - 13.2 - - - pF VCC = 3.0 V to 3.6 V - 14.9 - - - pF Dn to CP; see Fig. 6 Dn to CP; see Fig. 6 see Fig. 5 output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per flip-flop; VI = GND to VCC [4] [3] [4] Unit Min tsk(0) [1] [2] -40 °C to +125 °C Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 7 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 10.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna802 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. Clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times, and the maximum frequency VI VM CP input GND t su t su th th VI VM Dn input GND VOH VM Qn output VOL mna803 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 6. Data set-up and hold times for the Dn input to the CP input 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 8 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state VI OE input VM GND t PLZ Qn output LOW-to-OFF OFF-to-LOW t PZL VCC VM VX VOL t PZH t PHZ Qn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs enabled outputs disabled mna804 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. 3-state enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 1.65 V to 1.95 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 9 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator; VEXT = External voltage for measuring switching times. Fig. 8. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 10 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 11. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A (A 3 ) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT163-1 (SO20) 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 11 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm D SOT360-1 E A X c HE y v M A Z 11 20 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 10. Package outline SOT360-1 (TSSOP20) 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 12 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm B D SOT764-1 A A A1 E c detail X terminal 1 index area terminal 1 index area e1 C e b 2 9 v w C A B C y1 C y L 1 10 Eh e 20 11 19 12 X Dh 0 2.5 5 mm scale Dimensions (mm are the original dimensions) Unit mm A(1) A1 b max 1.00 0.05 0.30 nom 0.90 0.02 0.25 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 L v 0.2 4.6 4.5 4.4 3.15 3.00 2.85 2.6 2.5 2.4 1.15 1.00 0.85 0.5 3.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT764-1 --- MO-241 --- sot764-1_po European projection Issue date 03-01-27 14-12-12 Fig. 11. Package outline SOT764-1 (DHVQFN20) 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 13 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC574A v.7.1 20231102 Product data sheet - Modifications: • 74LVC574A v.6 20210830 Modifications: • • • • • • Section 2: ESD specification updated according to the latest JEDEC standard. Product data sheet - 74LVC574A v.5 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Type number 74LVC574ADB (SOT339-1/SSOP20) removed. Section 7: Derating values for Ptot total power dissipation updated. Fig. 11: Package outline drawing SOT764-1 (DHVQFN20) updated. 74LVC574A v.5 20121218 Modifications: • 74LVC574A v.4 20121203 Modifications: • • • 74LVC574A v.6 Product data sheet - 74LVC574A v.4 Changed interlacing into interfacing (errata) in features list. Product data sheet - 74LVC574A v.3 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 74LVC574A v.3 20040322 Product specification - 74LVC574A v.2 74LVC574A v.2 20030620 Product specification - 74LVC574A v.1 74LVC574A v.1 19980729 Product specification - - 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 14 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74LVC574A Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 15 / 16 74LVC574A Nexperia Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 8 11. Package outline........................................................ 11 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2023. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 2 November 2023 74LVC574A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 2 November 2023 © Nexperia B.V. 2023. All rights reserved 16 / 16