74LVC595APW

74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 01 — 29 May 2007 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial output (Q7S) for cascading purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. 2. Features s s s s s s s s 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Balanced propagation delays All inputs have Schmitt-trigger action Complies with JEDEC standard JESD8-B/JESD36 ESD protection: x HBM JESD22-A114-D exceeds 2000 V x CDM JESD22-C101-C exceeds 1000 V s Specified from −40 °C to +85 °C and −40 °C to +125 °C. 3. Applications s Serial-to-parallel data conversion s Remote control holding register NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 4. Ordering information Table 1. Ordering information Package Temperature range 74LVC595AD 74LVC595APW 74LVC595ABQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name SO16 TSSOP16 DHVQFN16 Description plastic small outline package; 16 leads; body width 3.9 mm Version SOT109-1 Type number plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 5. Functional diagram 11 12 9 15 1 2 3 4 5 6 7 13 OE 3-STATE OUTPUTS Q 0 Q 1 Q 2 Q3 Q4 Q5 Q6 Q 7 mna552 SHCP STCP Q 7S Q0 Q1 Q2 14 DS Q3 Q4 Q5 Q6 Q7 MR 10 OE 13 14 DS 11 SHCP 10 MR 8-STAGE SHIFT REGISTER Q7S 12 STCP 9 8-BIT STORAGE REGISTER 15 1 2 3 4 5 6 7 mna554 Fig 1. Logic symbol Fig 2. Functional diagram 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 2 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state STAGE 0 DS D FF0 CP SHCP R Q D STAGES 1 TO 6 Q STAGE 7 D FF7 CP R Q Q 7S MR D Q D Q LATCH CP STCP OE LATCH CP mna555 Q0 Q 1 Q2 Q3 Q4 Q5 Q6 Q7 Fig 3. Logic diagram SHCP DS STCP MR OE Q0 Q1 Z-state Z-state Q6 Q7 Q7 S Z-state Z-state mna556 Fig 4. Timing diagram 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 3 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 6. Pinning information 6.1 Pinning 74LVC595A terminal 1 index area 16 VCC 15 Q0 14 DS 13 OE 12 STCP 11 SHCP 10 MR 8 GND Q7S 9 Q1 2 3 4 5 6 7 1 Q2 16 VCC 15 Q0 14 DS 13 OE 12 STCP 11 SHCP 10 MR 9 001aaf569 74LVC595A Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 1 2 3 4 5 6 7 8 Q3 Q4 Q5 Q6 Q7 Q7S 001aaf570 Transparent top view Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 6.2 Pin description Table 2. Symbol Q[0:7] GND Q7S MR SHCP STCP OE DS VCC Pin description Pin 15, 1, 2, 3, 4, 5, 6, 7 8 9 10 11 12 13 14 16 Description parallel data output ground (0 V) serial data output master reset (active LOW) shift register clock input storage register clock input output enable input (active LOW) serial data input supply voltage 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 4 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 7. Functional description Table 3. Input SHCP STCP OE X X X ↑ X ↑ X X L L H L MR L L L H DS X X X H Function table[1] Output Q7S L L L Q6S Qn NC L Z NC a LOW-state on MR only affects the shift register empty shift register loaded into storage register shift register clear; parallel outputs in high impedance OFF-state logic HIGH-state shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages Function X ↑ ↑ ↑ L L H H X X NC Q6S QnS QnS [1] H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [1] [1] Max +6.5 +6.5 ±50 6.5 VCC + 0.5 ±50 100 +150 500 Unit V mA V mA V V mA mA mA °C mW VO > VCC or VO < 0 V 3-state output HIGH or LOW state VO = 0 V to VCC −0.5 −0.5 −100 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 5 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9. Recommended operating conditions Table 5. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage functional input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 3.6 V 3-state output HIGH or LOW state Conditions Min 1.65 1.2 0 0 0 −40 0 0 Typ Max 3.6 5.5 5.5 VCC +125 20 10 Unit V V V V V °C ns/V ns/V 10. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.2 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL LOW-level input voltage VCC = 1.2 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 3.6 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 3.6 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II input leakage VCC = 3.6 V; current VI = 5.5 V or GND ±0.1 0.2 0.45 0.6 0.4 0.55 ±5 0.3 0.65 0.8 0.6 0.8 ±20 V V V V V µA VCC − 0.2 1.2 1.8 2.2 2.4 2.2 VCC − 0.3 1.05 1.65 2.05 2.25 2.0 V V V V V V −40 °C to +85 °C Min 1.08 0.65 × VCC 1.7 2.0 Typ[1] Max 0.12 0.35 × VCC 0.7 0.8 −40 °C to +125 °C Min 1.08 0.65 × VCC 1.7 2.0 Max 0.12 0.7 0.8 V V V V V V V Unit 0.35 × VCC V 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 6 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter IOZ OFF-state output current power-off leakage current supply current additional supply current input capacitance Conditions VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V VCC = 0 V; VI or VO = 5.5 V [2] −40 °C to +85 °C Min Typ[1] 0.1 Max ±10 −40 °C to +125 °C Min Max ±20 Unit µA IOFF - 0.1 10 - 20 µA ICC ∆ICC VCC = 3.6 V; VI = VCC or GND; IO = 0 A per input pin; VCC = 1.65 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A VCC = 0 V to 3.6 V; VI = GND to VCC - 0.1 5 10 500 - 40 5000 µA µA CI - 5.0 - - - pF [1] [2] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. For transceivers, the parameter IOZ includes the input leaking current. 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter tpd Conditions [2] −40 °C to +85 °C Min Typ[1] 17.5 6.6 4.2 4.7 4.0 16.8 5.8 3.7 4.0 3.3 17.3 6.9 4.3 4.5 3.8 Max 15.8 8.1 7.6 6.7 15.8 8.1 7.6 6.7 15.8 8.1 7.6 6.7 −40 °C to +125 °C Min 2.0 1.5 1.5 1.5 2.0 1.5 1.5 1.2 2.0 1.5 1.5 1.2 Max 18.2 9.3 8.7 7.7 18.2 9.3 8.7 7.7 18.2 9.3 8.7 7.7 Unit propagation delay SHCP to Q7S; see Figure 7 VCC = 1.2 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V STCP to Qn; see Figure 8 VCC = 1.2 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V 2.0 1.5 1.5 1.5 [2] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2.0 1.5 1.5 1.2 2.0 1.5 1.5 1.2 tPHL HIGH to LOW MR to Q7S; see Figure 11 propagation delay VCC = 1.2 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 7 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter ten enable time Conditions OE to Qn; see Figure 12 VCC = 1.2 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tdis disable time OE to Qn; see Figure 12 VCC = 1.2 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tW pulse width SHCP, STCP HIGH or LOW; see Figure 7 and Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V MR LOW; see Figure 11 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsu set-up time DS to SHCP; see Figure 9 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V MR to STCP; see Figure 10 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V SHCP to STCP; see Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V 8.0 5.0 4.0 4.0 3.5 2.1 1.8 1.7 8.5 5.5 4.5 4.5 ns ns ns ns 8.0 5.0 4.0 4.0 3.5 2.1 1.8 1.7 8.5 5.5 4.5 4.5 ns ns ns ns 5.0 4.0 2.0 2.0 0.4 0.1 0 −0.1 5.5 4.5 2.5 2.5 ns ns ns ns 5.0 4.0 2.5 2.5 2.0 1.5 1.0 1.0 5.5 4.5 3.0 3.0 ns ns ns ns 6.0 5.0 4.5 4.0 2.5 2.0 1.5 1.5 7.0 5.5 5.0 4.5 ns ns ns ns [4] [3] −40 °C to +85 °C Min 2.0 1.5 1.5 1.2 2.0 1.2 1.5 1.2 Typ[1] 17.9 6.4 4.2 4.5 3.8 9.6 4.9 2.8 3.7 3.5 Max 14.1 8.0 7.6 6.7 9.8 5.8 6.2 5.7 −40 °C to +125 °C Min 2.0 1.5 1.5 1.2 2.0 1.2 1.5 1.2 Max 16.2 9.2 8.7 7.7 11.2 6.6 7.1 6.5 Unit ns ns ns ns ns ns ns ns ns ns 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 8 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter th hold time Conditions DS to SHCP; see Figure 9 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V trec recovery time MR to SHCP; see Figure 11 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency SHCP or STCP; see Figure 7 and Figure 8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(o) CPD output skew time power dissipation capacitance VCC = 3.0 V to 3.6 V VI = GND to VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] [3] [4] [5] [6] [5] [6] −40 °C to +85 °C Min 1.5 1.5 1.5 1.0 5.0 4.0 2.0 2.0 Typ[1] 0.2 0.1 −0.1 −0.2 −2.7 −1.5 −1.0 −1.0 Max - −40 °C to +125 °C Min 2.0 2.0 2.0 1.5 5.5 4.5 2.5 2.5 Max - Unit ns ns ns ns ns ns ns ns 80 100 110 130 - 130 140 150 180 50 45 44 1.0 - 70 90 100 115 - 1.5 - MHz MHz MHz MHz ns pF pF pF Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 9 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 12. Waveforms 1/fmax VI SHCP input GND tW t PLH VOH Q 7S output VOL mna557 VM t PHL VM Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency VI SHCP input GND t su VI STCP input GND tW t PLH VOH Q n output VOL mna558 VM 1/fmax VM t PHL VM Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 10 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI SHCP input GND t su th VI DS input GND VM t su th VM VOH Q 7S output VOL mna560 VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The data set-up and hold times for the serial data input (DS) VI MR input GND tsu VI STCP input GND VOH Qn outputs VOL 001aaf571 VM VM VM Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The master reset (MR) to storage clock (STCP) set-up times 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 11 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI MR input GND tW VI SHCP input GND t PHL VOH Q 7S output VOL VM mna561 VM t rec VM Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time VI OE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VM VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aae821 VM tPZL VX tPZH VY VM Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. 3-state enable and disable times Table 8. VCC VCC < 2.7 V VCC ≥ 2.7 V Measurement points Input VM 0.5 × VCC 1.5 V Output VM 0.5 × VCC 1.5 V VX VOL + 0.15 V VOL + 0.3 V VY VOH − 0.15 V VOH − 0.3 V Supply voltage 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 12 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC RL VM VI positive pulse 0V VM PULSE GENERATOR VI DUT RT VO CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Load circuitry for switching times Table 9. Test data Input VI 1.2 V 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V VCC VCC VCC 2.7 V 2.7 V tr, tf ≤ 2 ns ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 30 pF 50 pF 50 pF RL 1 kΩ 1 kΩ 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open tPLZ, tPZL 2 × VCC 2 × VCC 2 × VCC 2 × VCC 2 × VCC tPHZ, tPZH GND GND GND GND GND Supply voltage 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 13 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 14 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 15. Package outline SOT403-1 (TSSOP16) 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 15 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 16. Package outline SOT763-1 (DHVQFN16) 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 16 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 14. Abbreviations Table 10. Acronym CDM CMOS DUT ESD HBM TTL Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date 20070529 Data sheet status Product data sheet Change notice Supersedes Document ID 74LVC595A_1 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 17 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC595A_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 May 2007 18 of 19 NXP Semiconductors 74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 May 2007 Document identifier: 74LVC595A_1