74LVC74A

74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 06 — 4 June 2007 Product data sheet 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2. Features I I I I I I 5 V tolerant inputs for interlacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard JESD8-B/JESD36 ESD protection: N HBM JESD22-A114D exceeds 2000 V N CDM JESD22-C101C exceeds 1000 V I Specified from −40 °C to +85 °C and −40 °C to 125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC74AD 74LVC74ADB −40 °C to +125 °C −40 °C to +125 °C SO14 SSOP14 TSSOP14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT337-1 SOT402-1 Type number 74LVC74APW −40 °C to +125 °C 74LVC74ABQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 1SD SD D CP FF Q 4 10 1SD 2SD 2 12 3 11 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 1RD 2RD 1 13 mna418 4 2 3 1D 1CP Q 1Q 5 1Q 6 4 3 2 5 9 1 S C1 1D R RD 5 1 6 10 1RD 2SD SD D CP FF 8 RD mna419 10 6 8 11 12 13 12 S C1 1D R 13 9 11 2D 2CP Q 2Q 9 Q 2Q 8 2RD mna420 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram Q C C C C D C RD C C Q C SD mna421 CP C C Fig 4. Logic diagram for one flip-flop 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 2 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 5.1 Pinning 1RD 2 3 4 5 6 7 GND 2Q 8 1 1D 1CP 1SD 1Q 1Q GND 2 3 4 5 6 7 001aad106 1RD 1 14 VCC 13 2RD 12 2D terminal 1 index area 1D 1CP 1SD 1Q 14 VCC 13 2RD 12 2D 11 2CP 10 2SD 9 2Q 74 11 2CP 10 2SD 74 GND(1) 1Q 9 8 2Q 2Q 001aad107 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration for SO14 and (T)SSOP14 Fig 6. Pin configuration for DHVQFN14 5.2 Pin description Table 2. Symbol 1RD 1D 1CP 1SD 1Q 1Q GND 2Q 2Q 2SD 2CP 2D 2RD VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description asynchronous reset-direct input (active LOW) data input clock input (LOW-to-HIGH, edge-triggered) asynchronous set-direct input (active LOW) true output complement output ground (0 V) complement output true output asynchronous set-direct input (active LOW) clock input (LOW-to-HIGH, edge-triggered) data input asynchronous reset-direct input (active LOW) supply voltage 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 3 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Input nSD L H L [1] Function table[1] Output nRD H L L nCP X X X nD X X X nQ H L H nQ L H H H = HIGH voltage level L = LOW voltage level X = don’t care Table 4. Input nSD H H [1] Function table[1] Output nRD H H nCP ↑ ↑ nD L H nQn+1 L H nQn+1 H L H = HIGH voltage level L = LOW voltage level ↑ = LOW-to-HIGH transition Qn+1 = state after the next LOW-to-HIGH CP transition X = don’t care 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [2] Max +6.5 +6.5 ±50 VCC + 0.5 ±50 100 +150 500 Unit V mA V mA V mA mA mA °C mW VO > VCC or VO < 0 V VO = 0 V to VCC −0.5 −100 −65 Tamb = −40 °C to +125 °C [3] - The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 4 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 8. Recommended operating conditions Table 6. Symbol VCC VI Vo Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.2 V to 2.7 V VCC = 2.7 V to 3.6 V Conditions for maximum speed performance for low-voltage applications Min 2.7 1.2 0 0 −40 0 0 Typ Max 3.6 3.6 5.5 VCC +125 20 10 Unit V V V V °C ns/V ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage Conditions VCC = 1.2 V VCC = 2.7 V to 3.6 V VCC = 1.2 V VCC = 2.7 V to 3.6 V VI = VIH or VIL IO = −100 µA; VCC = 2.7 V to 3.6 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 2.7 V to 3.6 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II ICC ∆ICC input leakage VCC = 3.6 V; VI = 5.5 V or GND current supply current additional supply current input capacitance VCC = 3.6 V; VI = VCC or GND; IO = 0 A per input pin; VCC = 2.7 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A VCC = 0 V to 3.6 V; VI = GND to VCC ±0.1 0.1 5 0.2 0.4 0.55 ±5 10 500 0.3 0.6 0.8 ±20 40 5000 V V V µA µA µA VCC − 0.2 2.2 2.4 2.2 VCC − 0.3 2.05 2.25 2.0 V V V V −40 °C to +85 °C Min VCC 2.0 Typ[1] Max 0 0.8 −40 °C to +125 °C Min VCC 2.0 Max 0 0.8 V V V V Unit CI - 4.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 5 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tpd propagation delay Conditions nCP to nQ, nQ; see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V nSD to nQ, nQ; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V nRD to nQ, nQ; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tW pulse width clock HIGH or LOW; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V set or reset LOW; see Figure 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V trec recovery time set or reset; see Figure 8 VCC = 2.7 V VCC = 3.0 V to 3.6 V tsu set-up time nD to nCP; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V th hold time nD to nCP; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V fmax maximum frequency nCP; see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(o) CPD output skew time VCC = 3.0 V to 3.6 V power dissipation capacitance per flip-flop; VI = GND to VCC VCC = 3.3 V [3] [4] [2] −40 °C to +85 °C Min 1.0 1.0 1.0 1.0 1.0 1.0 3.3 3.3 3.3 3.3 1.5 +1.0 2.2 2.0 1.0 +1.0 83 150 Typ[1] 15 2.7 2.5 15 3.2 2.5 15 3.2 2.5 1.3 1.7 −3.0 0.8 −0.2 250 15 1.0 Max 6.0 5.2 6.4 5.4 6.4 5.4 - −40 °C to +125 °C Unit Min 1.0 1.0 1.0 1.0 1.0 1.0 4.5 4.5 4.5 4.5 1.0 1.0 2.2 2.0 1.0 1.0 66 120 Max 7.5 6.5 8.0 7.0 8.0 7.0 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns pF [1] [2] [3] Typical values are measured at Tamb = 25 °C. For VCC = 3.0 V to 3.6 V range, typical values are measured at 3.3 V. tpd is the same as tPLH and tPHL. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 6 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs 11. AC waveforms VI nD input GND th t su 1/fmax VI nCP input GND tW t PHL VOH nQ output VOL VOH nQ output VOL t PLH t PHL VM mna422 VM th t su VM t PLH VM The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, and the maximum frequency 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 7 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger VI nCP input GND t rec VI nSD input GND tW VI nRD input GND t PLH VOH nQ output VOL VOH nQ output VOL t PHL t PLH mna423 VM VM tW VM t PHL VM VM VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths, and the nRD to nCP recovery time 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 8 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC PULSE GENERATOR VI DUT RT CL RL VO 001aaf615 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Load circuitry for switching times Table 9. Test data Input VI 1.2 V 2.7 V 3.0 V to 3.6 V VCC 2.7 V 2.7 V tr, tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 50 pF 50 pF 50 pF RL 500 Ω 500 Ω 500 Ω Supply voltage 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 9 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ inches 0.069 0.010 0.057 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT108-1 (SO14) 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 10 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE vM A Z 14 8 Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT337-1 (SSOP14) 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 11 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Fig 12. Package outline SOT402-1 (TSSOP14) 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 12 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT762-1 (DHVQFN14) 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 13 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 13. Abbreviations Table 10. Acronym CDM DUT ESD HBM TTL Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20070604 Data sheet status Product data sheet Product data sheet Product specification Product specification Product specification Product specification Change notice Supersedes 74LVC74A_5 74LVC74A_4 74LVC74A_3 74LVC74A_2 74LVC74A_1 Document ID 74LVC74A_6 Modifications: 74LVC74A_5 74LVC74A_4 74LVC74A_3 74LVC74A_2 74LVC74A_1 • Change of hold time in Table 8 “Dynamic characteristics”. Minimum values changed to 1.0 ns. 20070525 20030526 20020618 19980617 19980617 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 14 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC74A_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 4 June 2007 15 of 16 NXP Semiconductors 74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 June 2007 Document identifier: 74LVC74A_6