74LVC823A
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive
edge-trigger; 3-state
Rev. 4 — 8 April 2013
Product data sheet
1. General description
The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable
(pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented
applications. The 9 flip-flops stores the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is
LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all
flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs.
When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pinout architecture
9-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C.
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC823AD
40 C to +125 C
SO24
plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
74LVC823ADB
40 C to +125 C
SSOP24
plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
74LVC823APW
40 C to +125 C
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
74LVC823ABQ
40 C to +125 C
DHVQFN24
plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
4. Functional diagram
2
D0
Q0
23
3
D1
Q1
22
4
D2
Q2
21
5
D3
Q3
20
Q4
19
Q5
18
FF0
to
FF8
6
D4
7
D5
8
D6
Q6
17
9
D7
Q7
16
10
D8
Q8
15
13
CP
11
MR
14
CE
1
OE
3-STATE
OUTPUTS
001aaa849
Fig 1.
Functional diagram
74LVC823A
Product data sheet
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Rev. 4 — 8 April 2013
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2 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
1
11
2
3
4
5
6
7
8
9
10
MR
D0
OE
Q0
D1
Q1
D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
D7
Q7
D8
CP
13
Q8
CE
R
14
G1
13
1
23
EN
11
2
22
1C2
21
3
22
20
4
21
19
5
20
6
19
7
18
8
17
9
16
10
15
18
17
16
15
14
001aaa847
Fig 2.
Logic symbol
74LVC823A
Product data sheet
23
2D
001aaa848
Fig 3.
IEC logic symbol
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3 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
D0
D1
D2
D3
D4
MR
CE
D
R
Q
R
D
Q
CP
CP
FF0
R
D
Q
CP
FF1
R
D
Q
D
CP
FF2
R
Q
CP
FF3
FF4
CP
OE
Q0
D5
Q1
D6
D
R
Q
D7
D
CP
Q2
R
Q
FF5
Q5
R
Q
D
CP
FF6
Q4
D8
D
CP
Q3
Q
CP
FF7
Q6
R
FF8
Q7
Q8
001aaa850
Fig 4.
Logic diagram
74LVC823A
Product data sheet
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Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
4 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
5. Pinning information
24 VCC
D0
2
23 Q0
D2
D3
D4
D5
D6
D7
22 Q1
3
21 Q2
4
5
20 Q3
6
19 Q4
823
7
18 Q5
17 Q6
8
9
16 Q7
D8 10
OE
23 Q0
3
22 Q1
D2
4
21 Q2
D3
5
20 Q3
D4
6
D5
7
D6
8
D7
9
D8 10
15 Q8
18 Q5
17 Q6
16 Q7
GND(1)
15 Q8
14 CE
13 CP
GND 12
19 Q4
823
MR 11
14 CE
MR 11
2
D1
GND 12
D1
D0
001aaa845
CP 13
1
1
terminal 1
index area
OE
24 VCC
5.1 Pinning
001aaa846
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO24 and (T)SSOP24
Fig 6.
Pin configuration DHVQFN24
5.2 Pin description
Table 2.
Pin description
Pin
Name
Description
OE
1
output enable input (active LOW)
MR
11
master reset input (active LOW)
D[0:8]
2, 3, 4, 5, 6, 7, 8, 9, 10
data input
Q[0:8]
23, 22, 21, 20, 19, 18, 17, 16, 15
3-state flip-flop output
CP
13
clock input (LOW to HIGH; edge-triggered)
CE
14
clock enable input (active LOW)
GND
12
ground (0 V)
VCC
24
supply voltage
74LVC823A
Product data sheet
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Rev. 4 — 8 April 2013
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5 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
6. Functional description
Table 3.
Function table [1]
Operating mode
OE
MR
CE
CP
Dn
Internal
flip-flop
Clear
L
L
X
X
X
L
Load and read register
L
H
L
l
L
L
L
H
L
h
H
H
Load register and
disable outputs
H
H
L
l
L
Z
H
H
L
h
H
Z
Hold
L
H
H
NC
X
NC
NC
[1]
Input
Output
L
Qn
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
= LOW to HIGH level transition
X = don’t care
NC = no change
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
output voltage
VO
Conditions
VI < 0 V
Min
Max
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
-
50
mA
HIGH or LOW state
[2]
0.5
VCC + 0.5
V
3-state
[2]
0.5
+6.5
V
[1]
VO > VCC or VO < 0 V
IO
output current
-
50
mA
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
total power dissipation
Ptot
VO = 0 V to VCC
Tamb = 40 C to +125 C
[3]
[1]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
For SO24 packages: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN24 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74LVC823A
Product data sheet
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Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
6 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
VO
output voltage
Min
Typ
Max
Unit
1.65
-
3.6
V
functional
1.2
-
-
V
0
-
5.5
V
HIGH or LOW state
0
-
VCC
V
3-state
0
-
5.5
V
Tamb
ambient temperature
in free air
40
-
+125
C
t/V
input transition rise and fall
rate
VCC = 1.65 V to 2.7 V
0
-
20
ns/V
VCC = 2.7 V to 3.6 V
0
-
10
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
VIH
VIL
VOH
VOL
II
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output
voltage
LOW-level
output
voltage
VCC = 1.2 V
Product data sheet
40 C to +125 C
Max
Min
Max
Unit
1.08
-
-
1.08
-
V
0.65 VCC
-
-
0.65 VCC
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
1.7
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
2.0
-
V
0.12
V
VCC = 1.65 V to 1.95 V
VCC = 1.2 V
-
-
0.12
-
VCC = 1.65 V to 1.95 V
-
-
0.35 VCC
-
VCC = 2.3 V to 2.7 V
-
-
0.7
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
-
0.8
V
VCC 0.2
-
-
VCC 0.3
-
V
IO = 4 mA; VCC = 1.65 V
1.2
-
-
1.05
-
V
IO = 8 mA; VCC = 2.3 V
1.8
-
-
1.65
-
V
IO = 12 mA; VCC = 2.7 V
2.2
-
-
2.05
-
V
IO = 18 mA; VCC = 3.0 V
2.4
-
-
2.25
-
V
IO = 24 mA; VCC = 3.0 V
2.2
-
-
2.0
-
V
IO = 100 A;
VCC = 1.65 V to 3.6 V
-
-
0.2
-
0.3
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
-
0.65
V
IO = 8 mA; VCC = 2.3 V
-
-
0.6
-
0.8
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
-
0.8
V
-
0.1
5
-
20
A
0.35 VCC V
VI = VIH or VIL
IO = 100 A;
VCC = 1.65 V to 3.6 V
VI = VIH or VIL
input leakage VCC = 3.6 V; VI = 5.5 V or GND
current
74LVC823A
Typ[1]
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74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Table 6.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
40 C to +125 C
Min
Typ[1]
Max
Min
Max
Unit
IOZ
OFF-state
output
current
VI = VIH or VIL; VCC = 3.6 V;
VO = 5.5 V or GND;
-
0.1
5
-
20
A
IOFF
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
-
0.1
10
-
20
A
ICC
supply
current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
0.1
10
-
40
A
ICC
additional
supply
current
per input pin;
-
5
500
-
5000
A
VCC = 2.7 V to 3.6 V;
VI = VCC 0.6 V; IO = 0 A
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
-
5.0
-
-
-
pF
CI
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11.
Symbol Parameter
Tamb = 40 C to +85 C 40 C to +125 C Unit
Conditions
Min
tpd
tPHL
propagation
delay
HIGH to LOW
propagation
delay
enable time
CP to Qn; see Figure 7
Product data sheet
Min
Max
-
20
-
-
-
ns
VCC = 1.65 V to 1.95 V
VCC = 1.2 V
2.4
8.4
18.7
2.4
21.5
ns
VCC = 2.3 V to 2.7 V
1.7
4.4
9.6
1.7
11.1
ns
VCC = 2.7 V
1.5
4.1
8.9
1.5
11.5
ns
VCC = 3.0 V to 3.6 V
1.5
3.7
8.0
1.5
10.0
ns
-
15
-
-
-
ns
2.1
9.5
21.4
2.1
24.7
ns
MR to Qn; see Figure 9
VCC = 1.2 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
1.5
4.9
10.5
1.5
12.1
ns
VCC = 2.7 V
1.5
4.7
8.8
1.5
11.0
ns
1.5
4.1
7.9
1.5
10.0
ns
OE to Qn; see Figure 10
[2]
VCC = 1.2 V
74LVC823A
Max
[2]
VCC = 3.0 V to 3.6 V
ten
Typ[1]
-
18
-
-
-
ns
VCC = 1.65 V to 1.95 V
1.7
7.4
16.5
1.7
19.0
ns
VCC = 2.3 V to 2.7 V
1.5
4.2
9.1
1.5
10.5
ns
VCC = 2.7 V
1.5
4.3
8.3
1.5
10.5
ns
VCC = 3.0 V to 3.6 V
1.5
3.4
7.2
1.5
9.0
ns
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Rev. 4 — 8 April 2013
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74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11.
Symbol Parameter
Tamb = 40 C to +85 C 40 C to +125 C Unit
Conditions
Min
tdis
disable time
OE to Qn; see Figure 10
pulse width
Max
Min
Max
[2]
VCC = 1.2 V
tW
Typ[1]
-
8.0
-
-
-
ns
VCC = 1.65 V to 1.95 V
2.3
4.2
10.0
2.3
11.5
ns
VCC = 2.3 V to 2.7 V
1.0
2.3
5.6
1.0
6.5
ns
VCC = 2.7 V
1.5
3.2
7.1
1.5
9.0
ns
VCC = 3.0 V to 3.6 V
1.5
2.9
6.0
1.5
7.5
ns
VCC = 1.65 V to 1.95 V
5.0
-
-
5.0
-
ns
VCC = 2.3 V to 2.7 V
4.0
-
-
4.0
-
ns
VCC = 2.7 V
3.3
-
-
3.3
-
ns
VCC = 3.0 V to 3.6 V
3.3
1.7
-
3.3
-
ns
clock HIGH or LOW; see Figure 7
master reset HIGH or LOW;
see Figure 9
tsu
set-up time
VCC = 1.65 V to 1.95 V
5.0
-
-
5.0
-
ns
VCC = 2.3 V to 2.7 V
4.0
-
-
4.0
-
ns
VCC = 2.7 V
3.3
-
-
3.3
-
ns
VCC = 3.0 V to 3.6 V
3.3
1.7
-
3.3
-
ns
VCC = 1.65 V to 1.95 V
3.0
-
-
3.0
-
ns
VCC = 2.3 V to 2.7 V
2.0
-
-
2.0
-
ns
VCC = 2.7 V
1.0
-
-
1.0
-
ns
VCC = 3.0 V to 3.6 V
+1.8
0.8
-
+1.8
-
ns
VCC = 1.65 V to 1.95 V
3.0
-
-
3.0
-
ns
VCC = 2.3 V to 2.7 V
2.0
-
-
2.0
-
ns
VCC = 2.7 V
1.8
-
-
1.8
-
ns
VCC = 3.0 V to 3.6 V
1.3
0.0
-
1.3
-
ns
3.0
-
-
3.0
-
ns
Dn to CP; see Figure 8
CE to CP; see Figure 8
trec
recovery time
MR; see Figure 9
VCC = 1.65 V to 1.95 V
74LVC823A
Product data sheet
VCC = 2.3 V to 2.7 V
2.5
-
-
2.5
-
ns
VCC = 2.7 V
2.0
-
-
2.0
-
ns
VCC = 3.0 V to 3.6 V
+1.0
0.5
-
+1.0
-
ns
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
9 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 11.
Symbol Parameter
th
hold time
Tamb = 40 C to +85 C 40 C to +125 C Unit
Conditions
Min
Typ[1]
Max
Min
Max
Dn to CP; see Figure 8
VCC = 1.65 V to 1.95 V
3.0
-
-
3.0
-
ns
VCC = 2.3 V to 2.7 V
2.5
-
-
2.5
-
ns
VCC = 2.7 V
2.0
-
-
2.0
-
ns
VCC = 3.0 V to 3.6 V
2.0
0.8
-
2.0
-
ns
VCC = 1.65 V to 1.95 V
3.0
-
-
3.0
-
ns
VCC = 2.3 V to 2.7 V
2.0
-
-
2.0
-
ns
VCC = 2.7 V
1.3
-
-
1.3
-
ns
VCC = 3.0 V to 3.6 V
1.3
0.0
-
1.3
-
ns
VCC = 1.65 V to 1.95 V
100
-
-
80
-
MHz
VCC = 2.3 V to 2.7 V
125
-
-
100
-
MHz
CE to CP; see Figure 8
maximum
frequency
fmax
see Figure 7
VCC = 2.7 V
150
-
-
120
-
MHz
VCC = 3.0 V to 3.6 V
150
200
-
120
-
MHz
-
-
1.0
-
1.5
ns
VCC = 1.65 V to 1.95 V
-
12.4
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
14.5
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
16.4
-
-
-
pF
tsk(o)
output skew
time
VCC = 3.0 V to 3.6 V
[3]
CPD
power
dissipation
capacitance
per input; VI = GND to VCC
[4]
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
[4]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CL VCC2 fo) = sum of the outputs
74LVC823A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
10 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
11. Waveforms
1/f max
VI
CP input
VM
GND
tW
t PHL
t PLH
VOH
VM
Qn output
VOL
mna894
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 7.
Clock to output propagation delays, clock pulse width, and maximum frequency
VI
VM
CP input
GND
t su
t su
th
th
VI
VM
Dn, CE input
GND
VOH
VM
Qn output
VOL
001aaa851
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 8.
Data set-up and hold times for data and clock enable inputs to clock input
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Product data sheet
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NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
VI
VM
CP input
GND
t rem
tW
VI
VM
MR input
VM
GND
t PHL
VOH
VM
Qn output
VOL
001aaa852
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 9.
Master reset pulse width, master reset to clock removal time and master reset to output propagation
delay
VI
OE input
VM
VM
GND
t PLZ
t PZL
VCC
Qn output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
VOH
VY
Qn output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
mgu775
Measurement points are given in Table 8.
VOL and VOH are the typical output voltage drops that occur with the output load.
Fig 10. 3-state outputs enable and disable times
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Product data sheet
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74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Table 8.
Measurement points
Supply voltage
Input
Output
VCC
VI
VM
VM
VX
VY
1.2 V
VCC
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
1.65 V to 1.95 V
VCC
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
2.3 V to 2.7 V
VCC
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH 0.15 V
2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
3.0 V to 3.6 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH 0.3 V
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
RL
CL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 11. Load circuitry for switching times
Table 9.
Test data
Supply voltage
Input
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2 V
VCC
2 ns
30 pF
1 k
open
2 VCC
GND
1.65 V to 1.95 V
VCC
2 ns
30 pF
1 k
open
2 VCC
GND
2.3 V to 2.7 V
VCC
2 ns
30 pF
500
open
2 VCC
GND
2.7 V
2.7 V
2.5 ns
50 pF
500
open
2 VCC
GND
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
open
2 VCC
GND
74LVC823A
Product data sheet
Load
VEXT
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Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
13 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 12. Package outline SOT137-1 (SO24)
74LVC823A
Product data sheet
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Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
14 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
D
SOT340-1
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.8
0.4
8o
o
0
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
SOT340-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 13. Package outline SOT340-1 (SSOP24)
74LVC823A
Product data sheet
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Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
15 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 14. Package outline SOT355-1 (TSSOP24)
74LVC823A
Product data sheet
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Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
16 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
B
D
SOT815-1
A
A
E
A1
c
detail X
terminal 1
index area
C
e1
terminal 1
index area
e
y1 C
v M C A B
w M C
b
2
y
11
L
12
1
e2
Eh
24
13
23
14
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
4.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT815-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
03-04-29
Fig 15. Package outline SOT815-1 (DHVQFN24)
74LVC823A
Product data sheet
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Rev. 4 — 8 April 2013
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17 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC823A v.4
20130408
Product data sheet
-
74LVC823A v.3
-
74LVC823A v.2
Modifications:
74LVC823A v.3
Modifications:
•
Features corrected (errata).
20130327
Product data sheet
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges.
74LVC823A v.2
20040510
Product specification
-
74LVC823A v.1
74LVC823A v.1
19980924
Product specification
-
-
74LVC823A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
18 of 21
74LVC823A
NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC823A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
19 of 21
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NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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NXP Semiconductors
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 April 2013
Document identifier: 74LVC823A