74LVC841A
10-bit transparent latch with 5 V tolerant inputs/outputs;
3-state
Rev. 03 — 24 May 2004
Product data sheet
1. General description
The 74LVC841A is a high performance, low-power, low-voltage Si-gate CMOS device and
superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can
handle 5 V. This feature allows the use of these devices as translators in a mixed
3.3 V and 5 V environment.
The 74LVC841A is a 10-bit transparent latch featuring separate D-type inputs for each
latch and 3-state outputs for bus-oriented applications. A latch enable (pin LE) input and
an output enable (pin OE) input are common to all internal latches. The 74LVC841A
consists of ten transparent latches with 3-state true outputs. When pin LE is HIGH, data at
the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch
output will change each time its corresponding D-input changes. When pin LE is LOW the
latches store the information that was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the ten latches
are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the pin OE input does not affect the state of the latches.
2. Features
■
■
■
■
■
■
■
■
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pin-out architecture
Complies with JEDEC standard JESD8B/JESD36
ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V.
■ Specified from −40 °C to +85 °C and −40 °C to +125 °C.
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CL = 50 pF;
VCC = 3.3 V
-
3.0
-
ns
propagation delay LE to Qn CL = 50 pF;
VCC = 3.3 V
-
3.4
-
ns
tPZH, tPZL
3-state output enable time
OE to Qn
CL = 50 pF;
VCC = 3.3 V
-
3.5
-
ns
tPHZ, tPLZ
3-state output disable time
OE to Qn
CL = 50 pF;
VCC = 3.3 V
-
2.9
-
ns
CI
input capacitance
-
5.0
-
pF
outputs enabled
-
13
-
pF
outputs disabled
-
4
-
pF
tPHL, tPLH propagation delay
Dn to Qn
power dissipation
capacitance per latch
CPD
VCC = 3.3 V
[1] [2]
[1]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2]
The condition is VI = GND to VCC.
4. Ordering information
Table 2:
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74LVC841AD
−40 °C to +125 °C SO24
plastic small outline package; 24 leads; body width
7.5 mm
SOT137-1
74LVC841ADB
−40 °C to +125 °C SSOP24
plastic shrink small outline package; 24 leads; body
width 5.3 mm
SOT340-1
74LVC841APW
−40 °C to +125 °C TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
74LVC841ABQ
−40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals; body
3.5 x 5.5 x 0.85 mm
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
2 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
5. Functional diagram
D0
0
D1
1
D
1
D
0
D
1
D
1
1
D
1
D
1
10
D
1
11
D
1
1
1
001aaa842
Fig 1. Functional diagram.
LE
13
1
2
E
001aaa838
Fig 2. Logic symbol.
EN
23
1
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
001aaa839
Fig 3. IEC Logic symbol.
9397 750 13129
Product data sheet
1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
3 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
D0
D1
D
Q
D2
D
Q
D3
D
Q
D4
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
D5
Q1
D6
D
Q
Q2
D7
D
Q
Q3
D8
D
Q
Q4
D9
D
Q
D
Q
LATCH
6
LATCH
7
LATCH
8
LATCH
9
LATCH
10
LE LE
LE LE
LE LE
LE LE
LE LE
Q5
Q6
Q7
Q8
Q9
001aaa843
Fig 4. Logic diagram
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
4 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
6. Pinning information
OE
24 VCC
6.1 Pinning
1
terina 1
ine area
1
24 VCC
D0
2
23 Q0
D1
3
22 Q1
D2
4
21 Q2
D3
5
20 Q3
D4
6
D5
7
D6
8
17 Q6
D7
9
16 Q7
D8 10
15 Q8
D9 11
14 Q9
GND 12
13 LE
19 Q4
841
18 Q5
D0
2
23 Q0
D1
3
22 Q1
D2
4
21 Q2
D3
5
20 Q3
D4
6
D5
7
D6
8
D7
9
D8 10
19 Q4
841
18 Q5
17 Q6
16 Q7
GND1
15 Q8
14 Q9
GND 12
D9 11
001aaa836
LE 13
OE
001aaa837
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as a
supply pin or input.
Fig 5. Pin configuration for SO24 and
(T)SSOP24.
Fig 6. Pin configuration for DHVQFN24.
6.2 Pin description
Table 3:
Pin description
Pin
Symbol
Description
1
OE
output enable input (active LOW)
2
D0
data input
3
D1
data input
4
D2
data input
5
D3
data input
6
D4
data input
7
D5
data input
8
D6
data input
9
D7
data input
10
D8
data input
11
D9
data input
12
GND
ground (0 V)
13
LE
latch enable input (active LOW)
14
Q9
3-state latch output
15
Q8
3-state latch output
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
5 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Table 3:
Pin description …continued
Pin
Symbol
Description
16
Q7
3-state latch output
17
Q6
3-state latch output
18
Q5
3-state latch output
19
Q4
3-state latch output
20
Q3
3-state latch output
21
Q2
3-state latch output
22
Q1
3-state latch output
23
Q0
3-state latch output
24
VCC
supply voltage
7. Functional description
7.1 Function table
Table 4:
Function table [1]
Operating mode
Input
LE
Dn
Internal
latches
Enable and read register L
(transparent mode)
L
H
L
L
L
H
H
H
H
Latch and read register
L
L
l
L
L
OE
Output
Qn
L
L
h
H
H
Latch register and
disable outputs
H
L
l
L
Z
H
L
h
H
Z
Hold
L
L
X
NC
NC
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care.
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input diode current
VI
input voltage
IOK
output diode current
Conditions
VI < 0 V
[1]
VO > VCC or VO < 0 V
9397 750 13129
Product data sheet
Min
Max
Unit
−0.5
+6.5
V
-
−50
mA
−0.5
+6.5
V
-
±50
mA
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
6 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Table 5:
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VO
Parameter
Conditions
output voltage
IO
output source or sink current
ICC, IGND
VCC or GND current
Tstg
storage temperature
Max
Unit
HIGH or LOW state
−0.5
VCC + 0.5
V
3-state
[1]
−0.5
+6.5
V
-
±50
mA
-
±100
mA
−65
+150
°C
-
500
mW
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
power dissipation
Ptot
Min
[1]
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO24 packages: above 70 °C derate linearly with 8 mW/K.
For (T)SSOP24 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN24 packages: above 60 °C derate linearly with 4.5 mW/K.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
for maximum speed
performance
2.7
3.6
V
VI
input voltage
VO
output voltage
for low-voltage applications
1.2
3.6
V
0
5.5
V
HIGH or LOW state
0
VCC
V
3-state
0
5.5
V
Tamb
operating ambient
temperature
in free air
−40
+125
°C
tr, tf
input rise and fall
times
VCC = 1.2 V to 2.7 V
0
20
ns/V
VCC = 2.7 V to 3.6 V
0
10
ns/V
10. Static characteristics
Table 7:
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Tamb = −40 °C to +85
Conditions
Min
Typ
Max
Unit
VCC = 1.2 V
VCC
-
-
V
°C [1]
VIH
HIGH-level input
voltage
VIL
LOW-level input
voltage
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 1.2 V
-
-
GND
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
7 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VOH
HIGH-level output
voltage
VI = VIH or VIL
VOL
LOW-level output
voltage
Min
Typ
Max
Unit
IO = −100 µA;
VCC = 2.7 V to 3.6 V
VCC − 0.2
VCC [2]
-
V
IO = −12 mA; VCC = 2.7 V
VCC − 0.5
-
-
V
IO = −18 mA; VCC = 3.0 V
VCC − 0.6
-
-
V
IO = −24 mA; VCC = 3.0 V
VCC − 0.8
-
-
V
-
GND
0.2
V
-
-
0.4
V
VI = VIH or VIL
IO = 100 µA;
VCC = 2.7 V to 3.6 V
[2]
IO = 12 mA; VCC = 2.7 V
-
-
0.55
V
ILI
input leakage current
VI = 5.5 V or GND; VCC = 3.6 V
IO = 24 mA; VCC = 3.0 V
-
±0.1
±5
µA
IOZ
3-state output
OFF-state current
VI = VIH or VIL;
VO = 5.5 V or GND; VCC = 3.6 V
-
0.1
±5
µA
Ioff
power-off leakage
supply
VI or VO = 5.5 V; VCC = 0.0 V
-
0.1
±10
µA
ICC
quiescent supply
current
VI = VCC or GND; IO = 0 A;
VCC = 3.6 V
-
0.1
10
µA
∆ICC
additional quiescent
VI = VCC − 0.6 V; IO = 0 A;
supply current per pin VCC = 2.7 V to 3.6 V
-
5
500
µA
CI
input capacitance
-
5.0
-
pF
[2]
Tamb = −40 °C to +125 °C
VIH
VIL
VOH
VOL
HIGH-level input
voltage
LOW-level input
voltage
HIGH-level output
voltage
LOW-level output
voltage
VCC = 1.2 V
VCC
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 1.2 V
-
-
GND
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
IO = −100 µA;
VCC = 2.7 V to 3.6 V
VCC − 0.3
-
-
V
IO = −12 mA; VCC = 2.7 V
VCC − 0.65 -
-
V
IO = −18 mA; VCC = 3.0 V
VCC − 0.75 -
-
V
IO = −24 mA; VCC = 3.0 V
VCC − 1
-
-
V
IO = 100 µA;
VCC = 2.7 V to 3.6 V
-
-
0.3
V
IO = 12 mA; VCC = 2.7 V
-
-
0.6
V
IO = 24 mA; VCC = 3.0 V
-
-
0.8
V
VI = VIH or VIL
VI = VIH or VIL
ILI
input leakage current
VI = 5.5 V or GND; VCC = 3.6 V
-
-
±20
µA
IOZ
3-state output
OFF-state current
VI = VIH or VIL;
VO = 5.5 V or GND; VCC = 3.6 V
-
-
±20
µA
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
8 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Table 7:
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ioff
power-off leakage
supply
VI or VO = 5.5 V; VCC = 0.0 V
-
-
±20
µA
ICC
quiescent supply
current
VI = VCC or GND; IO = 0 A;
VCC = 3.6 V
-
-
40
µA
∆ICC
additional quiescent
VI = VCC − 0.6 V; IO = 0 A;
supply current per pin VCC = 2.7 V to 3.6 V
-
-
5000
µA
Min
Typ
Max
Unit
-
15
-
ns
1.5
-
7.5
ns
1.5
3.0
6.7
ns
-
17
-
ns
1.5
-
8.6
ns
1.5
3.4
7.6
ns
-
19
-
ns
1.5
-
8.5
ns
1.5
3.5
7.2
ns
-
8.0
-
ns
1.5
-
6.6
ns
1.5
2.9
5.9
ns
-
-
-
ns
2.0
-
-
ns
2.0
0.7
-
ns
[1]
All typical values are measured Tamb = 25 °C.
[2]
These typical values are measured at VCC = 3.3 V.
11. Dynamic characteristics
Table 8:
Dynamic characteristics
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
Symbol
Parameter
Tamb = −40 °C to +85
tPHL, tPLH
Conditions
°C [1]
propagation delay
Dn to Qn
see Figure 7 and 11
VCC = 1.2 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
propagation delay
LE to Qn
[2]
see Figure 8 and 11
VCC = 1.2 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tPZH, tPZL
3-state output enable
time OE to Qn
[2]
see Figure 10 and 11
VCC = 1.2 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tPHZ, tPLZ
3-state output disable
time OE to Qn
[2]
see Figure 10 and 11
VCC = 1.2 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
tW
LE pulse width HIGH
[2]
see Figure 8
VCC = 1.2 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
9397 750 13129
Product data sheet
[2]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
9 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
Symbol
Parameter
Conditions
tsu
set-up time Dn to LE
see Figure 9
VCC = 1.2 V
VCC = 2.7 V
[2]
VCC = 3.0 V to 3.6 V
th
hold time Dn to LE
VCC = 2.7 V
CPD
power dissipation
capacitance per latch
Max
Unit
-
-
-
ns
2.0
-
-
ns
2.0
1.0
-
ns
-
-
-
ns
1.0
-
-
ns
[2]
1.0
0.0
-
ns
[3]
-
-
1.0
ns
outputs enabled
-
13
-
pF
outputs disabled
-
4
-
pF
VCC = 3.0 V to 3.6 V
skew
Typ
see Figure 9
VCC = 1.2 V
tsk(0)
Min
VCC = 3.0 V to 3.6 V
[4] [5]
VCC = 3.3 V
Tamb = −40 °C to +125 °C
tPHL, tPLH
propagation delay
Dn to Qn
propagation delay
LE to Qn
tPZH, tPZL
tPHZ, tPLZ
tW
tsu
3-state output enable
time OE to Qn
3-state output disable
time OE to Qn
LE pulse width HIGH
set-up time Dn to LE
see Figure 7 and 11
VCC = 1.2 V
-
-
-
ns
VCC = 2.7 V
1.5
-
9.5
ns
VCC = 3.0 V to 3.6 V
1.5
-
8.5
ns
see Figure 8 and 11
VCC = 1.2 V
-
-
-
ns
VCC = 2.7 V
1.5
-
11.0
ns
VCC = 3.0 V to 3.6 V
1.5
-
9.5
ns
see Figure 10 and 11
VCC = 1.2 V
-
-
-
ns
VCC = 2.7 V
1.5
-
11.0
ns
VCC = 3.0 V to 3.6 V
1.5
-
9.0
ns
see Figure 10 and 11
VCC = 1.2 V
-
-
-
ns
VCC = 2.7 V
1.5
-
8.5
ns
VCC = 3.0 V to 3.6 V
1.5
-
7.5
ns
see Figure 8
VCC = 1.2 V
-
-
-
ns
VCC = 2.7 V
2.0
-
-
ns
VCC = 3.0 V to 3.6 V
2.0
-
-
ns
see Figure 9
VCC = 1.2 V
-
-
-
ns
VCC = 2.7 V
2.0
-
-
ns
VCC = 3.0 V to 3.6 V
2.0
-
-
ns
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
10 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω.
Symbol
Parameter
Conditions
th
hold time Dn to LE
see Figure 9
tsk(0)
[1]
skew
Min
Typ
Max
Unit
VCC = 1.2 V
-
-
-
ns
VCC = 2.7 V
1.0
-
-
ns
VCC = 3.0 V to 3.6 V
1.0
-
-
ns
-
-
1.5
ns
[3]
VCC = 3.0 V to 3.6 V
All typical values are measured Tamb = 25 °C.
[2]
These typical values are measured at VCC = 3.3 V.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
[5]
The condition is VI = GND to VCC.
12. Waveforms
VI
VM
Dn input
GND
tPHL
tPLH
VOH
VM
Qn output
VOL
mna884
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig 7. Input (Dn) to output (Qn) propagation delays.
9397 750 13129
Product data sheet
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Rev. 03 — 24 May 2004
11 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
VI
LE input
VM
GND
tW
t PHL
t PLH
VOH
VM
Qn output
VOL
mna885
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 8. Latch enable input (LE) pulse width, the latch enable input to output (Qn)
propagation delays.
VI
VM
Dn input
GND
th
th
t su
t su
VI
LE input
VM
GND
mna887
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output
performance.
Fig 9. Data setup and hold times for the Dn input to the LE input.
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
12 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
VI
OE input
VM
GND
t PLZ
t PZL
VCC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
VX
VOL
t PZH
t PHZ
VOH
VY
Qn output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
output
enabled
output
enabled
output
disabled
mna886
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VX = VOL + 0.3 V at VCC ≥ 2.7 V;
VX = VOL + 0.1 × VCC at VCC < 2.7 V;
VY = VOH − 0.3 V at VCC ≥ 2.7 V;
VY = VOH − 0.1 × VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 10. 3-state enable and disable times.
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
13 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
VEXT
VCC
PULSE
GENERATOR
VI
RL
VO
D.U.T.
CL
RT
RL
mna616
Test data is given in Table 9.
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse
generator.
Fig 11. Load circuitry for switching times.
Table 9:
Measurement points
Supply voltage Input
Load
VCC
CL
VI
VEXT
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2 × VCC
1.2 V
VCC
50 pF
500
2.7 V
2.7 V
50 pF
500 Ω
open
GND
2 × VCC
3.0 V to 3.6 V
2.7 V
50 pF
500 Ω
open
GND
2 × VCC
[1]
The circuit performs better when RL = 1000 Ω.
9397 750 13129
Product data sheet
Ω [1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
14 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
13. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 12. Package outline SO24.
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
15 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
D
SOT340-1
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
w M
bp
e
detail X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.8
0.4
8
o
0
o
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
SOT340-1
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
Fig 13. Package outline SSOP24.
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
16 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
SOT355-1
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 14. Package outlineTSSOP24.
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
17 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
B
D
SOT815-1
A
A
E
A1
c
detail X
terminal 1
index area
C
e1
terminal 1
index area
e
y1 C
v M C A B
w M C
b
2
y
11
L
12
1
e2
Eh
24
13
23
14
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
4.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT815-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
03-04-29
Fig 15. Package outline DHVQFN24.
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
18 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
14. Revision history
Table 10:
Revision history
Document ID
Release date
Data sheet status
Change notice
Order number
Supersedes
74LVC841A_3
20040524
Product data
-
9397 750 13129
74LVC841A_2
Modifications:
74LVC841A_2
•
The format of this data sheet has been redesigned to comply with the current presentation and
information standard of Phillips Semiconductors.
•
Addition of temperature range Tamb = −40 °C to +125 °C
19980617
Product specification
-
9397 750 13129
Product data sheet
9397 750 04522
74LVC841A_1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
19 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
15. Data sheet status
Level
Data sheet status [1]
Product status [2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
17. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13129
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 24 May 2004
20 of 21
74LVC841A
Philips Semiconductors
10-bit transparant latch with 5 V tolerant inputs/outputs; 3-state
19. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
17
General description . . . . . . . . . . . . . . . . . . . . . 1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . 2
Functional diagram. . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions . . . . . . . 7
Static characteristics . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 9
Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
18
Contact information . . . . . . . . . . . . . . . . . . . . 20
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 24 May 2004
Document order number: 9397 750 13129
Published in The Netherlands
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