74LVCH244AD

74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state Rev. 06 — 13 August 2009 Product data sheet 1. General description The 74LVC244A; 74LVCH244A is an octal non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times. Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V and 5 V environment. The 74LVCH244A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features I I I I I I I I I 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Inputs accept voltages up to 5.5 V High-impedance when VCC = 0 V Bus hold on all data inputs (74LVCH244A only) Complies with JEDEC standard no. 8-1A ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC244AD 74LVCH244AD 74LVC244ADB 74LVCH244ADB 74LVC244APW 74LVCH244APW 74LVC244ABQ 74LVCH244ABQ 74LVC244ABX 74LVCH244ABX −40 °C to +125 °C −40 °C to +125 °C DHVQFN20 −40 °C to +125 °C TSSOP20 −40 °C to +125 °C SSOP20 −40 °C to +125 °C Name SO20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT339-1 SOT360-1 Type number SOT764-1 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm SOT1045-1 DHXQFN20U plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; UTLP based; body 2.5 × 4.5 × 0.5 mm 4. Functional diagram 2 18 17 3 1A0 1Y0 2A0 2Y0 1A1 4 16 1Y1 2A1 15 5 2Y1 1A2 6 14 1Y2 2A2 13 7 2Y2 1A3 1OE 8 1 12 1Y3 2A3 2OE 11 19 9 2Y3 mna874 Fig 1. Logic symbol 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 2 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 2 1A0 1Y0 18 4 1A1 1Y1 16 6 1A2 1Y2 14 1 EN 18 16 14 12 8 1 1A3 1OE 1Y3 12 2 4 6 8 17 2A0 2Y0 3 15 19 EN 13 11 13 15 17 mna873 2A1 2Y1 5 2A2 2Y2 7 9 7 5 3 19 11 2A3 2OE 2Y3 9 mna875 Fig 2. IEC logic diagram Fig 3. Functional diagram 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 3 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 5. Pinning information 5.1 Pinning 74LVC244A 74LVCH244A 1OE 2 3 4 5 6 7 8 9 GND 10 2A3 11 GND (1) 1 1A0 2Y0 terminal 1 index area 74LVC244A 74LVCH244A 1OE 1A0 2Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3 1 2 3 4 5 6 7 8 9 20 VCC 19 2OE 18 1Y0 17 2A0 16 1Y1 15 2A1 14 1Y2 13 2A2 12 1Y3 11 2A3 001aad113 20 VCC 19 2OE 18 1Y0 17 2A0 16 1Y1 15 2A1 14 1Y2 13 2A2 12 1Y3 1A1 2Y1 1A2 2Y2 1A3 2Y3 GND 10 001aad114 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration for SO20 and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20 and DHXQFN20U 5.2 Pin description Table 2. Symbol 1OE, 2OE 1A0, 1A1, 1A2, 1A3 2Y0, 2Y1, 2Y2, 2Y3 GND 2A0, 2A1, 2A2, 2A3 1Y0, 1Y1, 1Y2, 1Y3, VCC Pin description Pin 1, 19 2, 4, 6, 8 3, 5, 7, 9 10 Description output enable input (active low) data input data output ground (0 V) 17, 15, 13, 11 data input 18, 16, 14, 12 data output 20 supply voltage 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 4 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 6. Functional description Table 3. Control nOE L L H [1] Function table [1] Input nAn L H X Output nYn L H Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [2] [2] Max +6.5 +6.5 ±50 VCC + 0.5 +6.5 ±50 100 +150 500 Unit V mA V mA V V mA mA mA °C mW VO > VCC or VO < 0 V output HIGH or LOW output 3-state VO = 0 V to VCC −0.5 −0.5 −100 −65 Tamb = −40 °C to +125 °C [3] - The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SO20 packages: above 70 °C derate linearly with 8 mW/K. For (T)SSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 and DHXQFN20U packages: above 60 °C derate linearly with 4.5 mW/K. 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 5 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 8. Recommended operating conditions Table 5. Symbol VCC Recommended operating conditions Parameter supply voltage Conditions maximum speed performance functional VI VO Tamb ∆t/∆V input voltage output voltage ambient temperature input transition rise and fall rate output HIGH or LOW output 3-state in free air VCC = 1.2 V to 2.7 V VCC = 2.7 V to 3.6 V Min 2.7 1.2 0 0 0 −40 0 0 Typ Max 3.6 3.6 5.5 VCC 5.5 +125 20 10 Unit V V V V V °C ns/V ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage Conditions VCC = 1.2 V VCC = 2.7 V to 3.6 V VCC = 1.2 V VCC = 2.7 V to 3.6 V −40 °C to +85 °C Min VCC 2.0 VCC − 0.2 2.2 2.4 2.2 [2] −40 °C to +125 °C Unit Min VCC 2.0 VCC − 0.3 2.05 2.25 2.0 Max 0 0.8 0.3 0.6 0.8 ±20 ±20 V V V V V V V V V V V µA µA 0 Typ[1] VCC 0 ±0.1 ±0.1 Max 0.8 0.20 0.40 0.55 ±5 ±5 HIGH-level output VI = VIH or VIL voltage IO = −100 µA; VCC = 2.7 V to 3.6 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 2.7 V to 3.6 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II IOZ input leakage current OFF-state output current VI = 5.5 V or GND; VCC = 3.6 V VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - [2][3] IOFF ICC ∆ICC power-off leakage VI or VO = 5.5 V; VCC = 0.0 V current supply current additional supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V per input pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V - ±0.1 0.1 5 ±10 10 500 - ±20 40 5000 µA µA µA 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 6 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol CI IBHL IBHH IBHLO IBHHO Parameter input capacitance bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current VCC = 3.0 V; VI = 0.8 V VCC = 3.0 V; VI = 2.0 V VCC = 3.6 V VCC = 3.6 V [4][5] Conditions −40 °C to +85 °C Min 75 −75 500 −500 Typ[1] 4.0 Max - −40 °C to +125 °C Unit Min 60 −60 500 −500 Max pF µA µA µA µA [4][5] [4][6] [4][6] [1] [2] [3] [4] [5] [6] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. For I/O ports the parameter IOZ includes the input leakage current. Valid for data inputs of bus hold parts only (74LVCH244A). Note that control inputs do not have a bus hold circuit. The specified sustaining current at the data input holds the input below the specified VI level. The specified overdrive current at the data input forces the data input to the opposite input state. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter tpd propagation delay Conditions nAn to nYn; see Figure 6 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V ten enable time nOE to nYn; see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tdis disable time nOE to nYn; see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(o) output skew time [3] [4] [3] [1] [3] [1] [1] −40 °C to +85 °C Min 1.5 1.5 1.5 1.0 1.5 1.5 Typ[2] 17.0 3.3 2.8 24.0 3.3 3.4 9.0 3.2 2.9 Max 6.9 5.9 8.6 7.6 6.8 5.8 1.0 −40 °C to +125 °C Unit Min 1.5 1.5 1.5 1.0 1.5 1.5 Max 9.0 7.5 11 9.5 8.5 7.5 1.5 ns ns ns ns ns ns ns ns ns ns 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 7 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter CPD power dissipation capacitance Conditions per buffer; VI = GND to VCC; VCC = 3.3 V [5] −40 °C to +85 °C Min Typ[2] 10 Max - −40 °C to +125 °C Unit Min Max pF [1] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Typical values are measured at Tamb = 25 °C. Typical values are measured at Tamb = 25 °C and VCC = 3.3 V. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. [2] [3] [4] [5] 11. AC waveforms VI nAn input GND tPLH VOH nYn output VOL VM VM mna171 VM VM tPHL Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. The input (nAn) to output (nYn) propagation delays 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 8 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM outputs disabled outputs enabled mna362 Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 8. VCC 1.2 V 2.7 V 3-state enable and disable times. Measurement points Input VI VCC 2.7 V 2.7 V VM 0.5 × VCC 1.5 V 1.5 V Output VM 0.5 × VCC 1.5 V 1.5 V VX VOL + 0.1 V VOL + 0.3 V VOL + 0.3 V VY VOH − 0.1 V VOH − 0.3 V VOH − 0.3 V Supply voltage 3.0 V to 3.6 V 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 9 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 9. Test circuit for measuring switching times Test data Input VI tr, tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VCC 2.7 V 2.7 V Load CL 50 pF 50 pF 50 pF RL 500 Ω[1] 500 Ω 500 Ω VEXT tPLH, tPHL open open open tPLZ, tPZL 2 × VCC 2 × VCC 2 × VCC tPHZ, tPZH GND GND GND Supply voltage 1.2 V 2.7 V 3.0 V to 3.6 V [1] The circuit performs better when RL = 1 kΩ. 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 10 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT163-1 (SO20) © NXP B.V. 2009. All rights reserved. 74LVC_LVCH244A_6 Product data sheet Rev. 06 — 13 August 2009 11 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 10 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT339-1 (SSOP20) 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 12 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT360-1 (TSSOP20) 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 13 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT764-1 (DHVQFN20) 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 14 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state DHXQFN20U: plastic dual in-line compatible thermal enhanced extremely thin quad flat package; no leads; 20 terminals; UTLP based; body 2.5 x 4.5 x 0.5 mm SOT1045-1 D B A E A A1 detail X terminal 1 index area terminal 1 index area L1 2 e1 e b 9 v w M M CAB C C y1 C y L 1 10 Eh 20 11 e 19 12 Dh X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.30 0.18 D 4.6 4.4 Dh 3.35 3.05 E 2.6 2.4 Eh 1.35 1.05 e 0.5 e1 3.5 L 0.45 0.25 L1 0.13 0.05 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT1045-1 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-01 09-08-04 Fig 13. Package outline SOT1045-1 (DHXQFN20U) 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 15 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date Data sheet status 20090813 Product data sheet Product data sheet Change notice Supersedes 74LVC_LVCH244A_5 74LVC_LVCH244A_4 Document ID 74LVC_LVCH244A_6 Modifications: 74LVC_LVCH244A_5 Modifications: • • • • New SOT1045-1 package outline drawing (DHXQFN20U package). The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type numbers 74LVC244ABX and 74LVCH244ABX (DHXQFN20U package). Product specification Product specification Product specification Product specification 74LVC_LVCH244A_3 74LVC_H244A_2 74LVC244A_74LVCH244A_1 - 20090709 74LVC_LVCH244A_4 74LVC_LVCH244A_3 74LVC_H244A_2 20031030 20030520 19980520 74LVC244A_74LVCH244A_1 19960906 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 16 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 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Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC_LVCH244A_6 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 06 — 13 August 2009 17 of 18 NXP Semiconductors 74LVC244A; 74LVCH244A Octal buffer/line driver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 August 2009 Document identifier: 74LVC_LVCH244A_6