74LVCH322244AEC/G;

74LVCH322244A 32-bit buffer/line driver; 30  series termination resistors; 5 V tolerant input/output; 3-state Rev. 3 — 16 December 2011 Product data sheet 1. General description The 74LVCH322244A is a 32-bit non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs nOE. A HIGH on input nOE causes the outputs to assume a high-impedance OFF-state. The device is designed with 30  series termination resistors in both HIGH and LOW output stages to reduce line noise. To ensure the high-impedance state during power-up or power-down, input nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. 2. Features and benefits            5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Integrated 30  termination resistors All data inputs have bus hold Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2.7 V)  JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state  Packaged in plastic fine-pitch ball grid array package 3. Ordering information Table 1: Ordering information Type number Package Temperature range Name 74LVCH322244AEC 40 C to +85 C LFBGA96 Description Version plastic low profile fine pitch ball grid array package; 96 balls; body 13.5  5.5  1.05 mm SOT536-1 4. Functional diagram A5 A6 B5 B6 A3 C5 C6 D5 D6 A4 1A0 1Y0 1A1 1Y1 1A2 1Y2 1A3 1Y3 A2 E5 A1 E6 B2 F5 B1 F6 1OE H4 2A0 2Y0 2A1 2Y1 2A2 2Y2 2A3 2Y3 2OE C2 G5 C1 G6 D2 H6 D1 H5 H3 3A0 3Y0 3A1 3Y1 3A2 3Y2 3A3 3Y3 E2 J5 E1 J6 F2 K5 F1 K6 3OE J3 4A0 4Y0 4A1 4Y1 4A2 4Y2 4A3 4Y3 4OE G2 L5 G1 L6 H1 M5 H2 M6 J4 5A0 5Y0 5A1 5Y1 5A2 5Y2 5A3 5Y3 J2 N5 J1 N6 K2 P5 K1 P6 5OE T4 6A0 6Y0 6A1 6Y1 6A2 6Y2 6A3 6Y3 6OE L2 R5 L1 R6 M2 T6 M1 T5 T3 7A0 7Y0 7A1 7Y1 7A2 7Y2 7A3 7Y3 N2 N1 P2 P1 7OE 8A0 8Y0 8A1 8Y1 8A2 8Y2 8A3 8Y3 R2 R1 T1 T2 8OE mna472 Fig 1. Logic symbol VCC data input to internal circuit mna473 Fig 2. Bushold circuit 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 2 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state 5. Pinning information 5.1 Pinning mna471 6 1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A2 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A2 5 1A0 1A2 2A0 2A2 3A0 3A2 4A0 4A3 5A0 5A2 6A0 6A2 7A0 7A2 8A0 8A3 4 2OE GND VCC GND GND VCC GND 3OE 6OE GND VCC GND GND VCC GND 7OE 3 1OE GND VCC GND GND VCC GND 4OE 5OE GND VCC GND GND VCC GND 8OE 2 1Y0 1Y2 2Y0 2Y2 3Y0 3Y2 4Y0 4Y3 5Y0 5Y2 6Y0 6Y2 7Y0 7Y2 8Y0 8Y3 1 1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y2 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y2 A B C D E F G H J K L M N P R T Fig 3. Pin configuration 5.2 Pin description Table 2: Pin description Ball Symbol Description nOE (n = 1 to 8) A3, A4, H4, H3, J3 J4, T4, T3 3-state output enable inputs (active LOW) 1A[0:3] A5, A6, B5, B6 data input 2A[0:3] C5, C6, D5, D6 3A[0:3] E5, E6, F5, F6 4A[0:3] G5, G6, H6, H5 5A[0:3] J5, J6, K5, K6 6A[0:3] L5, L6, M5, M6 7A[0:3] N5, N6, P5, P6 8A[0:3] R5, R6, T6, T5 1Y[0:3] A2, A1, B2, B1 2Y[0:3] C2, C1, D2, D1 3Y[0:3] E2, E1, F2, F1 4Y[0:3] G2, G1, H1, H2 5Y[0:3] J2, J1, K2, K1 6Y[0:3] L2, L1, M2, M1 7Y[0:3] N2, N1, P2, P1 8Y[0:3] R2, R1, T1, T2 VCC C3, C4, F3, F4, L3, L4, P3, P4 supply voltage GND B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3, M4, N3, N4, R3, R4 ground (0 V) 74LVCH322244A Product data sheet data output All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 3 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state 6. Functional description Table 3: Functional table[1] Input Output nOE nAn nYn L L L L H H H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 [1] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA output HIGH or LOW state [2] 0.5 VCC + 0.5 V output 3-state [2] 0.5 +6.5 V - 50 mA VO > VCC or VO < 0 IO output current VO = 0 V to VCC ICC supply current - 200 mA IGND ground current 200 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] Above 70 C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Typ Max Unit 1.65 - 3.6 V functional 1.2 - - V 0 - 5.5 V output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V 40 - +125 C Tamb ambient temperature in free air t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 3.6 V - - 10 ns/V 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 4 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH HIGH-level input voltage VCC = 1.2 V LOW-level output voltage Max Min Unit Max 1.08 - - 1.08 - V - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - - 0.12 - 0.12 V - - 0.35  VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC  0.2 VCC - VCC  0.3 - V 1.2 - - 1.05 - V 0.35  VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V IO = 2 mA; VCC = 1.65 V VOL 40 C to +125 C 0.65  VCC VCC = 1.65 V to 1.95 V LOW-level input VCC = 1.2 V voltage VCC = 1.65 V to 1.95 V HIGH-level output voltage Typ[1] IO = 4 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 6 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 12 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 2 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 4 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 6 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 12 mA; VCC = 3.0 V - - 0.55 - 0.8 V VI = VIH or VIL II input leakage current VCC = 3.6 V; VI = 5.5 V or GND [2] - 0.1 5 - 20 A IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND; [2] - 0.1 5 - 20 A IOFF power-off leakage supply VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 40 - 160 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF IBHL bus hold LOW current VCC = 1.65 V; VI = 0.58 V 10 - - 10 - A VCC = 2.3 V; VI = 0.7 V 30 - - 25 - A VCC = 3.0 V; VI = 0.8 V 75 - - 60 - A 74LVCH322244A Product data sheet [3][4] All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 5 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter IBHH IBHLO IBHHO bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max 10 - - 10 - A VCC = 2.3 V; VI = 1.7 V 30 - - 25 - A VCC = 3.0 V; VI = 2.0 V 75 - - 60 - A 200 - - 200 - A 300 - - 300 - A VCC = 1.65 V; VI = 1.07 V [3][4] [3][5] VCC = 1.95 V VCC = 2.7 V 500 - - 500 - A 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A VCC = 3.6 V [3][5] VCC = 1.95 V [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. [2] The bus hold circuit is switched off when VI > VCC, allowing 5.5 V on the input terminal. [3] Valid for data inputs only. Note that control inputs do not have a bus hold circuit. [4] The specified sustaining current at the data input holds the input below the specified VI level. [5] The specified overdrive current at the data input forces the data input to the opposite logic input state. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6. Symbol Parameter tpd propagation delay Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max - 11.0 - - - ns VCC = 1.65 V to 1.95 V 1.5 6.0 15.0 1.5 17.2 ns VCC = 2.3 V to 2.7 V 1.0 3.2 7.4 1.0 8.2 ns VCC = 2.7 V 1.0 3.3 6.7 1.0 8.5 ns 1.0 2.7 5.8 1.0 7.5 ns - 15.0 - - - ns VCC = 1.65 V to 1.95 V 1.7 6.8 15.3 1.7 17.7 ns VCC = 2.3 V to 2.7 V 1.5 3.8 8.0 1.5 8.9 ns VCC = 2.7 V 1.5 4.2 7.6 1.5 9.5 ns VCC = 3.0 V to 3.6 V 1.0 3.1 6.0 1.0 7.5 ns - 10.0 - - - ns VCC = 1.65 V to 1.95 V 2.2 3.9 8.2 2.2 9.5 ns VCC = 2.3 V to 2.7 V 0.5 2.1 4.4 0.5 5.0 ns VCC = 2.7 V 1.5 3.1 4.7 1.5 6.0 ns VCC = 3.0 V to 3.6 V 1.5 2.8 4.5 1.5 6.0 ns nAn to nYn; see Figure 4 [2] VCC = 1.2 V VCC = 3.0 V to 3.6 V ten enable time nOE to nYn; see Figure 5 [2] VCC = 1.2 V tdis disable time nOE to nYn; see Figure 5 VCC = 1.2 V 74LVCH322244A Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 6 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6. Symbol Parameter Tamb = 40 C to +85 C 40 C to +125 C Unit Conditions tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per flip-flop; VI = GND to VCC [4] [1] [2] Min Typ[1] Max Min Max - - 1.0 - 1.5 ns - 4.8 - - - pF outputs enabled VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V - 8.3 - - - pF VCC = 3.0 V to 3.6 V - 11.4 - - - pF Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL  VCC2  fo) = sum of the outputs 11. AC waveforms VI nAn input VM GND t PHL t PLH VOH nYn output VM VOL mna474 VM = 1.5 V at VCC  2.7 V or VM = 0.5  VCC at VCC < 2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Input (nAn) to output (nYn) propagation delay times 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 7 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state VI nOE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled mna478 VM = 1.5 V at VCC  2.7 V; VM = 0.5  VCC at VCC < 2.7 V. VX = VOL + 0.3 V at VCC  2.7 V or VX = VOL + 0.1 V at VCC < 2.7 V. VY = VOH  0.3 V at VCC  2.7 V or VY = VOH  0.1 V at VCC < 2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. 3-state enable and disable times 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 8 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 6. Table 8. Load circuitry for switching times Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC  2 ns 30 pF 1 k open 2  VCC GND 1.65 V to 1.95 V VCC  2 ns 30 pF 1 k open 2  VCC GND 2.3 V to 2.7 V VCC  2 ns 30 pF 500  open 2  VCC GND 2.7 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 9 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 A B D ball A1 index area A A2 E A1 detail X e1 1/2 C e ∅v M e ∅w M b T R P N M L K J H G F E D C B A ball A1 index area y1 C C A B C y e e2 1/2 e 1 2 3 4 5 6 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 4 12 0.15 0.1 0.1 0.2 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 SOT536-1 Fig 7. Package outline SOT536-1 (LFBGA96) 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 10 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 10: Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVCH322244A v.3 20111216 Product data sheet - 74LVCH322244A v.2 Modifications: • The format of this document has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges. 74LVCH322244A v.2 20040519 Product specification - 74LVCH322244A v.1 74LVCH322244A v.1 19991124 Product specification - - 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 11 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 12 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVCH322244A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 December 2011 © NXP B.V. 2011. All rights reserved. 13 of 14 74LVCH322244A NXP Semiconductors 32-bit buffer/line driver; 30  resistors; 5 V tolerance; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 December 2011 Document identifier: 74LVCH322244A