74LVCH32245AEC

74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state Rev. 03 — 20 August 2007 Product data sheet 1. General description The 74LVCH32245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features four output enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction control. Pin nOE controls the outputs so that the buses are effectively isolated. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. To ensure the high-impedance state during power-up or power-down, pin nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features I I I I I I I I I I I 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Inputs accept voltages up to 5.5 V High-impedance when VCC = 0 V All data inputs have bus hold Complies with JEDEC standard JESD8-B / JESD36 ESD protection: N HBM EIA/JESD22-A114-B exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V Specified from −40 °C to +85 °C Packaged in plastic fine-pitch ball grid array package I I NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVCH32245AEC −40 °C to +85 °C Description Version SOT536-1 LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 × 5.5 × 1.05 mm Type number 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 2 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 4. Functional diagram 2DIR 2OE E5 1B0 A6 1A1 1B1 B5 1A2 1B2 B6 1A3 1B3 C5 1A4 1B4 C6 1A5 1B5 D5 1A6 1B6 D6 1A7 1B7 D1 D2 H5 2A7 2B7 H2 C1 H6 2A6 2B6 H1 C2 G6 2A5 2B5 G1 B1 G5 2A4 2B4 G2 B2 F6 2A3 2B3 F1 A1 F5 2A2 2B2 F2 A2 E6 2A1 2B1 E1 2A0 2B0 E2 A3 1DIR H3 1OE A4 H4 A5 1A0 J3 3DIR 3OE T3 J4 N5 3B0 J2 N6 3B1 J1 P5 3B2 K2 P6 3B3 K1 R5 3B4 L2 R6 3B5 L1 T6 3B6 M2 T5 3B7 M1 4DIR 4OE 4A0 4B0 4A1 4B1 4A2 4B2 4A3 4B3 4A4 4B4 4A5 4B5 4A6 4B6 4A7 4B7 mna476 T4 J5 3A0 N2 J6 3A1 N1 K5 3A2 P2 K6 3A3 P1 L5 3A4 R2 L6 3A5 R1 M5 3A6 T1 M6 3A7 T2 Fig 1. Logic symbol 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 3 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state VCC data input to internal circuit mna473 Fig 2. Bus hold circuit 5. Pinning information 5.1 Pinning mna475 6 5 4 3 2 1 1A1 1A0 1A3 1A2 1A5 1A4 1A7 1A6 2A1 2A0 2A3 2A2 2A5 2A4 2A6 2A7 3A1 3A0 3A3 3A2 3A5 3A4 3A7 3A6 4A1 4A0 4A3 4A2 4A5 4A4 4A6 4A7 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR 1B0 1B1 A 1B2 1B3 B 1B4 1B5 C 1B6 1B7 D 2B0 2B1 E 2B2 2B3 F 2B4 2B5 G 2B7 2B6 H 3B0 3B1 J 3B2 3B3 K 3B4 3B5 L 3B6 3B7 M 4B0 4B1 N 4B2 4B3 P 4B4 4B5 R 4B7 4B6 T Fig 3. Pin configuration 5.2 Pin description Table 2. Pin name nDIR (n = 1 to 4) nOE (n = 1 to 4) 1A[0:7] 1B[0:7] 2A[0:7] 2B[0:7] 3A[0:7] 3B[0:7] 4A[0:7] 4B[0:7] GND VCC Pin description Ball A3, H3, J3, T3 A4, H4, J4, T4 A5, A6, B5, B6, C5, C6, D5, D6 A2, A1, B2, B1, C2, C1, D2, D1 E5, E6, F5, F6, G5, G6, H6, H5 E2, E1, F2, F1, G2, G1, H1, H2 J5, J6, K5, K6, L5, L6, M5, M6 J2, J1, K2, K1, L2, L1, M2, M1 N5, N6, P5, P6, R5, R6, T6, T5 N2, N1, P2, P1, R2, R1, T1, T2 Description direction control output enable input (active LOW) input or output input or output input or output input or output input or output input or output input or output input or output B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V) M3, M4, N3, N4, R3, R4 C3, C4, F3, F4, L3, L4, P3, P4 supply voltage 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 4 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 6. Functional description Table 3. Input nOE L L H [1] Function selection[1] Output nDIR L H X nAn A=B inputs Z nBn inputs B=A Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] [4] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [2] [2] Max +6.5 +6.5 ±50 VCC + 0.5 +6.5 ±50 200 +150 1000 Unit V mA V mA V V mA mA mA °C mW VO > VCC or VO < 0 V output HIGH or LOW state output 3-state VO = 0 V to VCC [3] [3] −0.5 −0.5 −200 −65 - Tamb = −40 °C to +85 °C [4] The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. All supply and ground pins connected externally to one voltage source. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate output HIGH or LOW state output 3-state in free air VCC = 1.2 V to 2.7 V VCC = 2.7 V to 3.6 V Conditions for maximum speed performance for low-voltage applications Min 2.7 1.2 0 0 0 −40 Typ Max 3.6 5.5 VCC 5.5 +85 20 10 Unit V V V V V °C ns/V ns/V 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 5 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −12 mA IO = −18 mA IO = −24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA II IOZ IOFF ICC ∆ICC CI CI/O IBHL IBHH IBHLO IBHHO input leakage current OFF-state output current power-off leakage current supply current additional supply current input capacitance input/output capacitance bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current VI = 5.5 V or GND VI = VIH or VIL; VO = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 A per input pin; VI = VCC − 0.6 V; IO = 0 A VI = GND to VCC VI = GND to VCC VI = 0.8 V VI = 2.0 V 2.7 to 3.6 2.7 3.0 3.6 3.6 0.0 3.6 2.7 to 3.6 0 to 3.6 0 to 3.6 3.0 3.0 3.6 3.6 [4][5] [4][5] [4][6] [2] [2][3] Conditions VCC (V) 1.2 2.7 to 3.6 1.2 2.7 to 3.6 2.7 to 3.6 2.7 3.0 3.0 Min VCC 2.0 VCC − 0.2 VCC − 0.5 VCC − 0.6 VCC − 0.8 75 −75 500 −500 Typ[1] VCC GND ±0.1 ±0.1 ±0.1 0.1 5 5.0 10 - Max GND 0.8 0.20 0.40 0.55 ±5 ±5 ±10 40 500 - Unit V V V V V V V V V V V µA µA µA µA µA pF pF µA µA µA µA Tamb = −40 °C to +85 °C [4][6] [1] [2] [3] [4] [5] [6] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. For I/O ports the parameter IOZ includes the input leakage current. Valid for data inputs only. Note that control inputs do not have a bus hold circuit. The specified sustaining current at the data input holds the input below the specified VI level. The specified overdrive current at the data input forces the data input to the opposite input state. 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 6 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6. Symbol Parameter Tamb = −40 °C to +85 °C tpd propagation delay nAn to nBn; nBn to nAn; see Figure 4 1.2 2.7 3.0 to 3.6 ten enable time nOE to nAn, nBn: see Figure 5 1.2 2.7 3.0 to 3.6 tdis disable time nOE to nAn, nBn; see Figure 5 1.2 2.7 3.0 to 3.6 tsk(o) CPD output skew time power dissipation capacitance per buffer; VI = GND to VCC 3.0 to 3.6 3.3 [3] [4] [2] [2] [2] Conditions VCC (V) Min 1.0 1.0 1.5 1.0 1.5 1.5 - Typ[1] 13.0 2.7 2.2 15.0 3.6 2.8 11.0 3.4 3.2 30 Max 4.7 4.5 6.7 5.5 6.6 5.6 1.0 - Unit ns ns ns ns ns ns ns ns ns ns pF [1] [2] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 2.7 V, and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. [3] [4] 11. Waveforms VI nAn, nBn input GND t PHL VOH nBn, nAn output VOL VM mna477 VM t PLH VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5 × VCC at VCC < 2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. The input (nAn, nBn) to output (nBn, nAn) propagation delays 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 7 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM outputs disabled outputs enabled mna362 VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5 × VCC at VCC < 2.7 V. VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.15 V at VCC < 2.7 V. VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.15 V at VCC < 2.7 V. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. 3-state enable and disable times. 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 8 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 6. Load circuitry for switching times Table 8. Test data Input VI 1.2 V 2.7 V 3.0 V to 3.6 V VCC 2.7 V 2.7 V tr, tf ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 50 pF 50 pF 50 pF RL 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open tPLZ, tPZL 2 × VCC 2 × VCC 2 × VCC tPHZ, tPZH GND GND GND Supply voltage 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 9 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 D B A ball A1 index area A E A2 A1 detail X e1 1/2 e C ∅v M C A B e T R P N M L K J H G F E D C B A ball A1 index area y1 C y b ∅w M C e e2 1/2 e 123456 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 13.6 13.4 e 0.8 e1 4 e2 12 v 0.15 w 0.1 y 0.1 y1 0.2 OUTLINE VERSION SOT536-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 Fig 7. Package outline SOT536-1 (LFBGA96) 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 10 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 13. Abbreviations Table 9. Acronym DUT ESD HBM MM TTL Abbreviations Description Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 10. Revision history Release date 20070820 Data sheet status Product data sheet Change notice Supersedes 74LVCH32245A_2 Document ID 74LVCH32245A_3 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Error in Table 2 “Pin description” corrected. Quick Reference Data section deleted. Information (CPD, CI, CI/O) moved from it to Table 6 and Table 7. Some parameter symbols and descriptions have been updated to comply with NXP guidelines. Product specification 74LVC_LVCH32245A_1 - 74LVCH32245A_2 74LVC_LVCH32245A_1 20040511 19990901 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 11 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVCH32245A_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 20 August 2007 12 of 13 NXP Semiconductors 74LVCH32245A 32-bit bus transceiver with direction pin; 5 V tolerant; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 August 2007 Document identifier: 74LVCH32245A_3