74LVCH32373AEC,557

INTEGRATED CIRCUITS DATA SHEET 74LVCH32373A 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state Product specification Supersedes data of 1999 Nov 24 2004 May 19 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A The 74LVCH32373A is a 32-bit transparent D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable input (nLE) and one output enable input (nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. FEATURES • 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 V to 3.6 V • CMOS low power consumption • MULTIBYTE flow-trough standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce The 74LVCH32373A consists of 4 sections of eight D-type transparent latches with 3-state true outputs. When input nLE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • All data inputs have bushold • Complies with JEDEC standard JESD8-B/JESD36 When input nLE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of nLE. When input nOE is LOW, the contents of the eight latches are available at the outputs. When input nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. • ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 °C to +85 °C • Packaged in plastic fine-pitch ball grid array package. The 74LVCH32373A bushold data input circuits eliminate the need for external pull-up resistors to hold unused inputs. DESCRIPTION The 74LVCH32373A is a high-performance, low-power, low-voltage, Si-gate CMOS device superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH PARAMETER CONDITIONS TYPICAL UNIT propagation delay nDn to nQn CL = 50 pF; VCC = 3.3 V 3.0 ns propagation delay nLE to nQn CL = 50 pF; VCC = 3.3 V 3.4 ns tPZH/tPZL 3-state output enable time nOE to nQn CL = 50 pF; VCC = 3.3 V 3.5 ns tPHZ/tPLZ 3-state output disable time nOE to nQn CL = 50 pF; VCC = 3.3 V 3.9 ns CI input capacitance 5.0 pF CPD power dissipation per latch outputs enabled 15 pF outputs disabled 11 pF VCC = 3.3 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; 2004 May 19 2 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A CL = output load capacity in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUT INTERNAL LATCH OPERATING MODE nDn OUTPUT nOE nLE nQn Enable and read register (transparent mode) L H L L L L H H H H Latch and read register L L l L L L L h H H Latch register and disable outputs H L l L Z H L h H Z Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74LVCH32373AEC −40 °C to +85 °C PINNING PINS PACKAGE MATERIAL CODE 96 LFBGA96 plastic SOT536-1 BALL SYMBOL B5 1D2 data input B6 1D3 data input data output C1 1Q5 data output BALL SYMBOL DESCRIPTION A1 1Q1 data output A2 1Q0 DESCRIPTION A3 1OE output enable input (active LOW) C2 1Q4 data output A4 1LE latch enable input (active HIGH) C3 VCC supply voltage A5 1D0 data input C4 VCC supply voltage A6 1D1 data input C5 1D4 data input B1 1Q3 data output C6 1D5 data input B2 1Q2 data output D1 1Q7 data output B3 GND ground (0 V) D2 1Q6 data output B4 GND ground (0 V) D3 GND ground (0 V) 2004 May 19 3 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state BALL SYMBOL D4 GND D5 D6 74LVCH32373A DESCRIPTION BALL SYMBOL DESCRIPTION ground (0 V) L3 VCC supply voltage 1D6 data input L4 VCC supply voltage 1D7 data input L5 3D4 data input E1 2Q1 data output L6 3D5 data input E2 2Q0 data output M1 3Q7 data output E3 GND ground (0 V) M2 3Q6 data output E4 GND ground (0 V) M3 GND ground (0 V) E5 2D0 data input M4 GND ground (0 V) E6 2D1 data input M5 3D6 data input F1 2Q3 data output M6 3D7 data input F2 2Q2 data output N1 4Q1 data output F3 VCC supply voltage N2 4Q0 data output F4 VCC supply voltage N3 GND ground (0 V) F5 2D2 data input N4 GND ground (0 V) F6 2D3 data input N5 4D0 data input G1 2Q5 data output N6 4D1 data input G2 2Q4 data output P1 4Q3 data output G3 GND ground (0 V) P2 4Q2 data output G4 GND ground (0 V) P3 VCC supply voltage G5 2D4 data input P4 VCC supply voltage G6 2D5 data input P5 4D2 data input H1 2Q6 data output P6 4D3 data input H2 2Q7 data output R1 4Q5 data output H3 2OE output enable input (active LOW) R2 4Q4 data output H4 2LE latch enable input (active HIGH) R3 GND ground (0 V) H5 2D7 data input R4 GND ground (0 V) H6 2D6 data input R5 4D4 data input J1 3Q1 data output R6 4D5 data input J2 3Q0 data output T1 4Q6 data output J3 3OE output enable input (active LOW) T2 4Q7 data output J4 3LE latch enable input (active HIGH) T3 4OE output enable input (active LOW) J5 3D0 data input T4 4LE latch enable input (active HIGH) J6 3D1 data input T5 4D7 data input K1 3Q3 data output T6 4D6 data input K2 3Q2 data output K3 GND ground (0 V) K4 GND ground (0 V) K5 3D2 data input K6 3D3 data input L1 3Q5 data output L2 3Q4 data output 2004 May 19 4 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A mna492 6 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6 5 1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7 4 1LE GND VCC GND GND VCC GND 2LE 3 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 2 1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q7 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7 1 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q6 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6 A B C D E F G H 3LE GND VCC GND GND VCC GND 4LE J K L M N P R T Fig.1 Pin configuration. 1D0 D 2D0 1Q0 Q Q LATCH 1 LATCH 9 LE LE LE 1LE 2LE 1OE 2OE to 7 other channels 3D0 D D 4D0 LATCH 17 LE LE to 7 other channels 3Q0 Q 2Q0 D Q 4Q0 LATCH 25 LE LE 3LE 4LE 3OE 4OE to 7 other channels LE to 7 other channels mna493 Fig.2 Logic symbol. 2004 May 19 5 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A VCC handbook, halfpage data input to internal circuit MNA473 Fig.3 Bushold circuit. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage VI input voltage VO output voltage CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low-voltage applications 1.2 3.6 V 0 5.5 V output HIGH or LOW state 0 VCC V output 3-state 0 5.5 V Tamb ambient temperature in free air −40 +85 °C tr, tf input rise and fall times VCC = 1.2 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC supply voltage IIK input diode current CONDITIONS MIN. MAX. UNIT −0.5 +6.5 V VI < 0 V − −50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 V − ±50 mA VO output voltage output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V output 3-state; note 1 −0.5 +6.5 V IO output source or sink current VO = 0 V to VCC − ±50 mA ICC, IGND VCC or GND current note 2 − ±200 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 1000 mW Tamb = −40 °C to +85 °C; note 3 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. All supply and ground pins connected externally to one voltage source. 3. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 2004 May 19 6 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +85 °C; note 1 VIH VIL LOW-level input voltage VOH HIGH-level output voltage VOL 1.2 VCC − − V 2.7 to 3.6 2.0 − − V 1.2 − − GND V 2.7 to 3.6 − − 0.8 V IO = −100 µA 2.7 to 3.6 VCC − 0.2 VCC − V IO = −12 mA 2.7 VCC − 0.5 − − V IO = −18 mA 3.0 VCC − 0.6 − − V IO = −24 mA 3.0 VCC − 0.8 − − V IO = 100 µA 2.7 to 3.6 − GND 0.20 V IO = 12 mA 2.7 − − 0.40 V IO = 24 mA 3.0 − − 0.55 V HIGH-level input voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND; note 2 3.6 − ±0.1 ±5 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; note 2 3.6 − 0.1 ±5 µA Ioff power-off leakage supply current VI or VO = 5.5 V 0.0 − 0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A 3.6 − 0.1 40 µA ∆ICC additional quiescent supply VI = VCC − 0.6 V; current per input pin IO = 0 A 2.7 to 3.6 − 5 500 µA IBH bushold LOW sustaining current VI = 0.8 V; notes 3 and 4 3.0 75 − − µA IBHH bushold HIGH sustaining current VI = 2.0 V; notes 3 and 4 3.0 −75 − − µA IBHLO bushold LOW overdrive current notes 3 and 5 3.6 500 − − µA IBHHO bushold HIGH overdrive current notes 3 and 5 3.6 −500 − − µA Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. 3. For data inputs only, control inputs do not have a bushold circuit. 4. The specified sustaining current at the data inputs holds the input below the specified VI level. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 2004 May 19 7 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω. CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 °C to +85 °C; note 1 tPHL/tPLH propagation delay nDn to nQn propagation delay nLE to nQn tPZH/tPZL tPHZ/tPLZ tW tsu th tsk(0) see Fig 4 and 8 see Fig 5 and 8 3-state output enable time nOE to nQn see Fig 7 and 8 3-state output disable time nOE to nQn see Fig 7 and 8 nLE pulse width HIGH set-up time nDn to nLE hold time nDn to nLE see Fig 5 see Fig 6 see Fig 6 skew Notes 1. All typical values are measured at Tamb = 25 °C. 2. Measured at VCC = 3.3 V. 2004 May 19 8 1.2 − 12 − ns 2.7 1.5 − 4.9 ns 3.0 to 3.6 1.0 3.0(2) 4.4 ns 1.2 − 14 − ns 2.7 1.5 − 5.3 ns 3.0 to 3.6 1.5 3.4(2) 4.8 ns 1.2 − 18 − ns 2.7 1.5 − 5.7 ns 3.0 to 3.6 1.0 3.5(2) 4.9 ns 1.2 − 11 − ns 2.7 1.5 − 6.3 ns 3.0 to 3.6 1.5 3.9(2) 5.4 ns 1.2 − − − ns 2.7 3.0 − − ns 3.0 to 3.6 3.0 2.0(2) − ns 1.2 − − − ns 2.7 2.0 − − ns 3.0 to 3.6 2.0 1.0(2) − ns 1.2 − − − ns 2.7 0.9 − − ns 3.0 to 3.6 0.9 −1.0(2) − ns 3.0 to 3.6 − − 1.0 ns Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A AC WAVEFORMS VI VM nDn input GND t PLH t PHL VOH VM nQn output VOL mna494 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are typical output voltage drop that occur with the output load. Fig.4 Input (nDn) to output (nQn) propagation delay times. VI nLE input VM VM GND tW t PHL t PLH VOH VM nQn output VOL mna495 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 Latch enable inputs (nLE) pulse width and the latch enable input to outputs (nQn) propagation delay times. 2004 May 19 9 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A VI VM nDn input GND th th t su t su VI VM nLE input GND mna496 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. Fig.6 Set-up and hold times for inputs (nDn) to inputs (nLE). VI handbook, full pagewidth nOE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled MNA478 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V. VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.1 V at VCC < 2.7 V; VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.1 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 3-state output enable and disable times. 2004 May 19 10 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A VEXT handbook, full pagewidth VCC VI PULSE GENERATOR RL VO D.U.T. CL RT RL MNA616 VCC VI CL RL Ω(1) VEXT tPLH/tPHL tPZH/tPHZ tPZL/tPLZ open GND 2 × VCC 1.2 V VCC 50 pF 500 2.7 V 2.7 V 50 pF 500 Ω open GND 2 × VCC 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 2 × VCC Note 1. The circuit performs better when RL = 1000 Ω. Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.8 Load circuitry for switching times. 2004 May 19 11 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A PACKAGE OUTLINE LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 A B D ball A1 index area A A2 E A1 detail X e1 C 1/2 e ∅v M C A B e T R P N M L K J H G F E D C B A ball A1 index area y1 C y ∅w M C b e e2 1/2 e 1 2 3 4 5 6 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 4 12 0.15 0.1 0.1 0.2 OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 00-03-04 03-02-05 SOT536-1 2004 May 19 EUROPEAN PROJECTION 12 Philips Semiconductors Product specification 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state 74LVCH32373A DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 May 19 13 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/02/pp14 Date of release: 2004 May 19 Document order number: 9397 750 13227