74LVCH32374AEC,518

74LVCH32374A 32-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Rev. 3 — 18 December 2012 Product data sheet 1. General description The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The device consists of 4 sections of 8 edge-triggered flip-flops. A clock (pin nCP) input and an output enable input (pin nOE) are provided per 8-bit section. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of pin nOE does not affect the state of the flip-flops. The inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, the outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 V or 5 V environment. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits           5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pin-out architecture Multiple low inductance supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold High impedance when VCC = 0 V Latch-up performance exceeds 500 mA per JESD 78 Class II Complies with JEDEC standard:  JESD8-7A (1.65 V to 1.95 V)  JESD8-5A (2.3 V to 2.7 V)  JESD8-C/JESD36 (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-B exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Specified from 40 C to +85 C and 40 C to +125 C  Packaged in plastic fine-pitch ball grid array package 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74LVCH32374AEC 40 C to +125 C Name Description Version LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5  5.5  1.05 mm SOT536-1 4. Functional diagram 1D0 D 1Q0 Q 2D0 D CP FF 9 1CP 2CP 1OE 2OE to 7 other channels D 2Q0 CP FF 1 3D0 Q to 7 other channels 3Q0 Q 4D0 D CP Q 4Q0 CP FF 17 FF 25 3CP 4CP 3OE 4OE to 7 other channels to 7 other channels coa012 Fig 1. Logic symbol VCC data input to internal circuit mna473 Fig 2. Bus hold circuit 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 2 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 5. Pinning information 5.1 Pinning 001aah180 6 1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6 5 1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7 4 1CP GND VCC GND GND VCC GND 2CP 3CP GND VCC GND GND VCC GND 4CP 3 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 2 1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q7 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7 1 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q6 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6 A Fig 3. B C D E F G H J K L M N P R T Pin configuration 5.2 Pin description Table 2. Pin description Symbol Ball Description nOE (n = 1 to 4) A3, H3, J3, T3 output enable input (active LOW) nCP (n = 1 to 4) A4, H4, J4, T4 clock input 1D[0:7] A5, A6, B5, B6, C5, C6, D5, D6 data input 2D[0:7] E5, E6, F5, F6, G5, G6, H6, H5 data input 3D[0:7] J5, J6, K5, K6, L5, L6, M5, M6 data input 4D[0:7] N5, N6, P5, P6, R5, R6, T6, T5 data input 1Q[0:7] A2, A1, B2, B1, C2, C1, D2, D1 data output 2Q[0:7] E2, E1, F2, F1, G2, G1, H1, H2 data output 3Q[0:7] J2, J1, K2, K1, L2, L1, M2, M1 data output 4Q[0:7] N2, N1, P2, P1, R2, R1, T1, T2 data output GND B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3, M4, N3, N4, R3, R4 ground (0 V) VCC C3, C4, F3, F4, L3, L4, P3, P4 supply voltage 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 3 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 6. Functional description Table 3. Function table[1] Operating mode Input Internal flip-flop Output nOE nCP nDn Load and read register L  l L L L  h H H Load register and disable outputs H  l L Z H  h H Z [1] nQn H = HIGH voltage level L = LOW voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition Z = high-impedance OFF-state  = LOW-to-HIGH CP transition 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)[1] Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions Min VI < 0 [2] Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA output HIGH or LOW state [3] 0.5 VCC + 0.5 V output 3-state [3] 0.5 +6.5 V - 50 mA VO > VCC or VO < 0 IO output current ICC supply current - 200 mA IGND ground current 200 - mA Tstg storage temperature 65 +150 C - 1000 mW total power dissipation Ptot VO = 0 V to VCC Tamb = 40 C to +125 C [4] [1] All supply and ground pins connected externally to one voltage source. [2] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [3] The output voltage ratings may be exceeded if the output current ratings are observed. [4] Above 70 C the value of Ptot derate linearly with 1.8 mW/K. 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 4 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate Min Typ Max Unit 1.65 - 3.6 V functional 1.2 - 3.6 V 0 - 5.5 V output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V in free air 40 - +125 C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 3.6 V - - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min VIH VIL VOH VOL II HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current 74LVCH32374A Product data sheet Typ[1] 40 C to +125 C Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V VCC = 1.65 V to 1.95 V 0.65  VCC - - 0.65  VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35  VCC - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V - VCC  0.3 - V - V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 3.6 V VCC  0.2 IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - 0.1 5 - 20 A VI = VIH or VIL VCC = 3.6 V; VI = 5.5 V or GND[2] All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 5 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state Table 6. Static characteristics ...continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min Typ[1] 40 C to +125 C Max Min Unit Max IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND[2] - 0.1 5 - 20 A IOFF power-off VCC = 0 V; VI or VO = 5.5 V leakage current - 0.1 10 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 40 - 160 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC  0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF IBHL bus hold LOW current VCC = 1.65; VI = 0.58 V[3][4] 10 - - 10 - A VCC = 2.3; VI = 0.7 V 30 - - 25 - A VCC = 3.0; VI = 0.8 V 75 - - 60 - A bus hold HIGH current VCC = 1.65; VI = 1.07 V[3][4] 10 - - 10 - A VCC = 2.3; VI = 1.7 V 30 - - 25 - A VCC = 3.0; VI = 2.0 V 75 - - 60 - A IBHH IBHLO IBHHO [1] bus hold LOW overdrive current bus hold HIGH overdrive current 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A 200 - - 200 - A VCC = 2.7 V 300 - - 300 - A VCC = 3.6 V 500 - - 500 - A VCC = 1.95 VCC = 1.95 V[3][5] V[3][5] All typical values are measured at VCC = 3.3 V and Tamb = 25 C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. [3] Valid for data inputs only. Control inputs do not have a bus hold circuit. [4] The specified sustaining current at the data input holds the input below the specified VI level. [5] The specified overdrive current at the data input forces the data input to the opposite logic input state. 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 6 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter tpd ten propagation delay enable time 40 C to +85 C Conditions Min Max Min Max - 14 - - - ns VCC = 1.65 V to 1.95 V 2.1 6.9 13.5 2.1 15.6 ns VCC = 2.3 V to 2.7 V 1.5 3.7 6.7 1.5 7.7 ns VCC = 2.7 V 1.5 3.4 6.0 1.5 7.5 ns VCC = 3.0 V to 3.6 V 1.5 3.1 5.4 1.5 7.0 ns - 20 - - - ns nCP to nQn; see Figure 4 [2] VCC = 1.2 V nOE to nQn; see Figure 6 [2] VCC = 1.2 V VCC = 1.65 V to 1.95 V 1.5 5.9 13.1 1.5 15.1 ns VCC = 2.3 V to 2.7 V 1.5 3.4 6.9 1.5 8.0 ns VCC = 2.7 V 1.5 3.6 6.0 1.5 7.5 ns 1.0 2.7 5.2 1.0 6.5 ns - 12 - - - ns VCC = 1.65 V to 1.95 V 2.8 4.6 9.1 2.8 10.5 ns VCC = 2.3 V to 2.7 V 1.0 2.5 4.9 1.0 5.7 ns VCC = 2.7 V 1.5 3.4 5.1 1.5 6.5 ns VCC = 3.0 V to 3.6 V 1.5 3.1 4.9 1.5 6.5 ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.0 - - 3.0 - ns VCC = 3.0 V to 3.6 V 3.0 1.5 - 3.0 - ns VCC = 3.0 V to 3.6 V tdis disable time nOE to nQn; see Figure 4 VCC = 1.2 V tW tsu th pulse width set-up time hold time 74LVCH32374A Product data sheet 40 C to +125 C Unit Typ[1] [2] nCP HIGH; see Figure 4 nDn to nCP; see Figure 5 VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns VCC = 2.3 V to 2.7 V 3.0 - - 3.0 - ns VCC = 2.7 V 1.9 - - 1.9 - ns VCC = 3.0 V to 3.6 V 1.9 0.3 - 1.9 - ns VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 1.1 - - 1.1 - ns VCC = 3.0 V to 3.6 V 1.5 0.3 - 1.5 - ns nDn to nCP; see Figure 5 All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 7 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state Table 7. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter fmax maximum frequency 40 C to +85 C Conditions Min Typ[1] Max 40 C to +125 C Unit Min Max see Figure 4 VCC = 1.65 V to 1.95 V 100 - - 80 - ns VCC = 2.3 V to 2.7 V 125 - - 100 - ns VCC = 2.7 V 150 - - 120 - MHz 150 300 - 120 - MHz - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 14.1 - - - pF VCC = 2.3 V to 2.7 V - 16.4 - - - pF VCC = 3.0 V to 3.6 V - 18.5 - - - pF VCC = 3.0 V to 3.6 V tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per input; VI = GND to VCC [4] [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] [4] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL  VCC2  fo) = sum of the outputs 11. Waveforms 1/fmax VI nCP input VM VM GND tW t PHL t PLH VOH VM nQn output 001aaa256 VOL Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Clock (nCP) to output (nQn) propagation delays, the clock pulse width and the maximum clock frequency 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 8 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state VI VM nCP input GND t su t su th th VI VM nDn input GND VOH VM nQn output VOL 001aaa257 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Set-up and hold times for inputs (nDn) to inputs (nCP) VI nOE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled mna478 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. 3-state output enable and disable times 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 9 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 1.65 V to 1.95 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 2.3 V to 2.7 V VCC 0.5  VCC 0.5  VCC VOL + 0.15 V VOH  0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to the output impedance Zo of the pulse generator Fig 7. Table 9. Load circuitry for switching times Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH VCC  2 ns 30 pF 1 k open 2  VCC GND 1.65 V to 1.95 V VCC  2 ns 30 pF 1 k open 2  VCC GND 2.3 V to 2.7 V VCC  2 ns 30 pF 500  open 2  VCC GND 2.7 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 3.0 V to 3.6 V 2.7 V  2.5 ns 50 pF 500  open 2  VCC GND 1.2 V 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 10 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 A B D ball A1 index area A A2 E A1 detail X e1 1/2 C e ∅v M e ∅w M b T R P N M L K J H G F E D C B A ball A1 index area y1 C C A B C y e e2 1/2 e 1 2 3 4 5 6 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 4 12 0.15 0.1 0.1 0.2 OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 00-03-04 03-02-05 SOT536-1 Fig 8. EUROPEAN PROJECTION Package outline SOT536-1 (LFBGA96) 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 11 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVCH32374A v.3 20121218 Product data sheet - 74LVCH32374A v.2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6 , Table 7, Table 8 and Table 9: values added for lower voltage ranges. 74LVCH32374A v.2 20040519 Product specification - 74LVCH32374A v.1 74LVCH32374A v.1 19991124 Product specification - - 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 12 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVCH32374A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 13 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVCH32374A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 December 2012 © NXP B.V. 2012. All rights reserved. 14 of 15 74LVCH32374A NXP Semiconductors 32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 December 2012 Document identifier: 74LVCH32374A