74LVT16374A

74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 07 — 22 March 2010 Product data sheet 1. General description The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for VCC operation at 3.3 V. This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic levels set up at the nDn inputs. 2. Features and benefits 16-bit edge-triggered flip-flop 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection: JESD78B Class II exceeds 500 mA ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range 74LVT16374ADL 74LVT16374ADGG 74LVTH16374ADGG 74LVT16374AEV 74LVTH16374ABQ −40 °C to +85 °C −40 °C to +85 °C VFBGA56 HXQFN60U −40 °C to +85 °C −40 °C to +85 °C Name SSOP48 TSSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm plastic thin shrink small outline package; 48 leads; body width 6.1 mm plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 × 7 × 0.65 mm plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 × 6 × 0.5 mm Version SOT370-1 SOT362-1 SOT702-1 SOT1134-1 Type number 4. Functional diagram 47 46 44 43 41 40 38 37 1 1OE 48 1CP 24 2OE 25 2CP 1D0 1D1 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 001aaa254 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1 1CP 1OE EN1 C3 EN2 C4 3D 1 2 3 5 6 8 9 11 12 4D 2 13 14 16 17 19 20 22 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1D2 1D3 2 3 5 6 8 9 11 12 1D4 1D5 36 35 33 32 30 29 27 26 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D0 2D1 2D2 25 24 2CP 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2D3 2D4 2D5 2D6 13 14 16 17 19 20 22 23 2D7 001aac369 Pin numbers are shown for SSOP48 and TSSOP48 packages only. Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 2 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state nD0 D nD1 D nD2 D nD3 D nD4 D nD5 D nD6 D nD7 D CP nCP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 001aac371 Fig 3. Logic diagram 5. Pinning information 5.1 Pinning 74LVT16374A 74LVTH16374A 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1 2 3 4 5 6 7 8 9 48 1CP 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2CP 001aak263 GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24 ball A1 index area A B C D E F G H J K 74LVT16374A 74LVTH16374A 123456 001aak264 Transparent top view Fig 4. Pin configuration for SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) Fig 5. Pin configuration for SOT702-1 (VFBGA56) 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 3 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state terminal 1 index area D1 A32 A31 A30 A29 A28 A27 D4 A1 D5 B20 B19 B18 D8 A26 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 GND(1) B11 B12 B15 B16 B17 A25 A24 A23 A22 74LVT16374A 74LVTH16374A B14 A21 B13 A20 A19 A18 A10 D6 B8 B9 B10 D7 A17 D2 A11 A12 A13 A14 A15 A16 D3 001aak265 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration SOT1134-1 (HXQFN60U) 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 4 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 5.2 Pin description Table 2. Symbol Pin description Pin SOT370-1 and SOT362-1 1OE, 2OE 1CP, 2CP 1Q0 to 1Q7 2Q0 to 2Q7 GND VCC 1D0 to 1D7 2D0 to 2D7 n.c. 1, 24 48, 25 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 SOT702-1 A1, K1 A6, K6 B2, B1, C2, C1, D2, D1, E2, E1 F1, F2, G1, G2, H1, H2, J1, J2 SOT1134-1 A30, A13 A29, A14 output enable input (active LOW) clock input Description B20, A31, D5, D1, A2, data output B2, B3, A5 A6, B5, B6, A9, D2, D6, A12, B8 data output 4, 10, 15, 21, 28, 34, 39, B3, D3, G3, J3, J4, 45 G4, D4, B4 7, 18, 31, 42 47, 46, 44, 43, 41, 40, 38, 37 36, 35, 33, 32, 30, 29, 27, 26 C3, H3, H4, C4 B5, B6, C5, C6, D5, D6, E5, E6 F6, F5, G6, G5, H6, H5, J6, J5 A2, A3, A4, A5, K2, K3, K4, K5 A32, A3, A8, A11, A16, ground (0 V) A19, A24, A27 A1, A10, A17, A26 B18, A28, D8, D4, A25, B16, B15, A22 A21, B13, B12, A18, D3, D7, A15, B10 A4, A7, A20, A23, B1, B4, B7, B9, B11, B14, B17, B19 supply voltage data input data input not connected 6. Functional description Table 3. Function table[1] Input nOE Load and read register Hold Disable outputs L L L H H [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition. Operating mode Internal register nCP ↑ ↑ NC NC ↑ nDn l h X X nDn L H NC NC nDn Output nQ0 to nQ7 L H NC Z Z 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 5 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO Tstg Tj Ptot Parameter supply voltage input voltage output voltage input clamping current output clamping current output current storage temperature junction temperature total power dissipation Tamb = −40 °C to +85 °C (T)SSOP48 package VFBGA56 and HXQFN60U package [1] [2] [3] [4] [3] [4] [2] [1] Conditions Min −0.5 −0.5 −0.5 −50 −50 −64 −65 - Max +4.6 +7.0 +7.0 128 +150 150 500 1000 Unit V V V mA mA mA mA °C °C mW mW output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC VI VIH VIL IOH IOL Recommended operating conditions Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current none current duty cycle ≤ 50 %; fi ≥ 1 kHz Tamb Δt/ΔV ambient temperature in free-air input transition rise and fall rate outputs enabled Conditions Min 2.7 0 2.0 −32 −40 Typ Max 3.6 5.5 0.8 32 64 +85 10 Unit V V V V mA mA mA °C ns/V 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 6 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 °C VIK VOH input clamping voltage VCC = 2.7 V; IIK = −18 mA IOH = −8 mA; VCC = 2.7 V IOH = −32 mA; VCC = 3.0 V VOL LOW-level output voltage VCC = 2.7 V IOL = 100 μA IOL = 24 mA VCC = 3.0 V IOL = 16 mA IOL = 32 mA IOL = 64 mA VOL(pu) II power-up LOW-level output voltage input leakage current VCC = 3.6 V; IO = 1 mA; VI = VCC or GND control pins VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V input data pins VCC = 0 V or 3.6 V; VI = 5.5 V VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V IOFF IBHL IBHH IBHLO IBHHO ILO IO(pu/pd) IOZ power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current output leakage current power-up/power-down output current OFF-state output current VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V input data pins; VI = 0 V to 3.6 V; VCC = 3.6 V input data pins; VI = 0 V to 3.6 V; VCC = 3.6 V output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care VCC = 3.6 V; VI = VIH or VIL output HIGH: VO = 3.0 V output LOW: VO = 0.5 V ICC supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. Conditions Min −1.2 2.4 2.0 [2] Typ[1] −0.85 2.5 2.3 0.07 0.3 0.25 0.3 0.4 0.1 Max 0.2 0.5 0.4 0.5 0.55 0.55 Unit V V V V V V V V V V HIGH-level output voltage IOH = −100 μA; VCC = 2.7 V to 3.6 V VCC − 0.2 VCC - [3] 0.1 0.4 0.4 0.1 −0.4 0.1 135 −135 50 1 ±1 10 10 1 ±100 −75 −500 125 ±100 μA μA μA μA μA μA μA μA μA μA μA μA −5 75 [4] 500 - [4] [5] - −5 [6] 0.5 0.5 0.07 4.0 0.07 5 0.12 6.0 0.12 μA μA mA mA mA - © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 7 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ΔICC CI CO additional supply current input capacitance output capacitance Conditions per input pin; VCC = 3.0 V to 3.6 V; one input at VCC − 0.6 V, other inputs at VCC or GND input pins; VI = 0 V or 3.0 V output pins nQn; outputs disabled; VO = 0 V or VCC [7] Min - Typ[1] 0.1 3 9 Max 0.2 - Unit mA pF pF [1] [2] [3] [4] [5] [6] [7] Typical values are measured at VCC = 3.3 V and at Tamb = 25 °C. For valid test results, data must not be loaded into the flips-flops (or latches) after applying power. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol fmax tPLH Parameter Conditions Min 150 1.5 1.5 1.5 1.5 1.5 1.5 Typ[1] 2.9 3.0 3.2 3.0 3.9 3.4 Max 5.0 5.6 5.0 5.6 4.8 6.0 4.6 5.2 5.4 6.0 4.6 5.0 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns Tamb = −40 °C to +85 °C maximum frequency nCP; VCC = 3.3 V ± 0.3 V; see Figure 7 LOW to HIGH propagation delay nCP to nQn; see Figure 7 VCC = 3.3 V ± 0.3 V VCC = 2.7 V tPHL HIGH to LOW propagation delay nCP to nQn; see Figure 7 VCC = 3.3 V ± 0.3 V VCC = 2.7 V tPZH OFF-state to HIGH propagation delay nOE to nQn; see Figure 8 VCC = 3.3 V ± 0.3 V VCC = 2.7 V tPZL OFF-state to LOW propagation delay nOE to nQn; see Figure 8 VCC = 3.3 V ± 0.3 V VCC = 2.7 V tPHZ HIGH to OFF-state propagation delay nOE to nQn; see Figure 8 VCC = 3.3 V ± 0.3 V VCC = 2.7 V tPLZ LOW to OFF-state propagation delay nOE to nQn; see Figure 8 VCC = 3.3 V ± 0.3 V VCC = 2.7 V 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 8 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol tsu Parameter set-up time Conditions nDn to nCP; HIGH or LOW; see Figure 9 VCC = 3.3 V ± 0.3 V VCC = 2.7 V th hold time nDn to nCP; HIGH or LOW; see Figure 9 VCC = 3.3 V ± 0.3 V VCC = 2.7 V tW pulse width nCP HIGH; see Figure 7 VCC = 3.3 V ± 0.3 V VCC = 2.7 V nCP LOW; see Figure 7 VCC = 3.3 V ± 0.3 V VCC = 2.7 V [1] [2] [3] [4] All typical values are at VCC = 3.3 V and Tamb = 25 °C. tsu is the same as tsu(H) and tsu(L). th is the same as th(H) and th(L). tW is the same as tW(H) and tW(L). [4] [3] [2] Min 2.0 2.0 0.8 0.1 1.5 1.5 3.0 3.0 Typ[1] 0.7 0 0.6 1.6 - Max - Unit ns ns ns ns ns ns ns ns 11. Waveforms 1/fmax VI nCP input GND tW t PHL VOH nQn output VOL VM 001aaa256 VM VM t PLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. Input VM 1.5 V Propagation delay clock input to output, clock pulse width and maximum clock frequency Measurement points Output VM 1.5 V VX VOL + 0.3 V VY VOH − 0.3 V 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 9 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state VI nOE input GND tPZL 3.0 V nYn output VOL t PZH t PHZ VM tPLZ VM VX VOH nYn output 0V 001aae464 VM VY Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Enable and disable times VI nCP input GND t su th VI nDn input GND VM t su th VM VOH nQn output VOL 001aaa257 VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 10 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 10. Test circuit for measuring switching times Table 9. Input VI 2.7 V fi ≤ 10 MHz tW 500 ns tr, tf ≤ 2.5 ns Test data Load CL 50 pF RL 500 Ω VEXT tPHZ, tPZH GND tPLZ, tPZL 6V tPLH, tPHL open 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 11 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE vM A Z 48 25 Q A2 A1 (A 3) θ Lp 1 24 A pin 1 index L wM detail X e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT370-1 (SSOP48) 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 12 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c y HE vMA Z 48 25 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp 24 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT362-1 (TSSOP48) 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 13 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm SOT702-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 b e CAB ∅w M C ∅v M C y1 C y K J H e G F E D C B A ball A1 index area 1 2 3 4 5 6 1/2 e2 e X DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.3 0.2 A2 0.7 0.6 b 0.45 0.35 D 4.6 4.4 E 7.1 6.9 e 0.65 e1 3.25 e2 5.85 v 0.15 w 0.08 y 0.08 y1 0.1 0 2.5 scale 5 mm OUTLINE VERSION SOT702-1 REFERENCES IEC JEDEC MO-225 JEITA EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 Fig 13. Package outline SOT702-1 (VFBGA56) 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 14 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm D B A SOT1134-1 terminal 1 index area E A A1 detail X e2 e1 1/2 e v w L1 CAB C D2 D6 A10 eR B7 e b A11 B8 B10 A16 D7 A17 B11 D3 v w CAB C y1 C C y L e Eh 1/2 e B1 A1 terminal 1 index area D5 D1 B20 A32 Dh k 0 Dimensions Unit mm A A1 b D 4.1 4.0 3.9 Dh 1.90 1.85 1.80 E 6.1 6.0 5.9 Eh 3.90 3.85 3.80 e 0.5 e1 1 2.5 scale e2 2.5 B18 A27 D8 D4 B17 A26 e3 e4 X 5 mm e3 3 e4 4.5 eR 0.5 k L L1 0.125 0.075 0.025 v w y y1 0.1 sot1134-1_po max 0.50 0.05 0.35 nom 0.48 0.02 0.30 min 0.46 0.00 0.25 0.25 0.35 0.20 0.30 0.15 0.25 0.07 0.05 0.08 Outline version SOT1134-1 References IEC --JEDEC --JEITA --- European projection Issue date 08-12-17 09-01-22 Fig 14. Package outline SOT1134-1 (HXQFN60U) 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 15 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 13. Abbreviations Table 10. Acronym BiCMOS DUT ESD HBM MM TTL Abbreviations Description Bipolar Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20100322 Data sheet status Product data sheet Change notice Supersedes 74LVT_LVTH16374A_6 Document ID 74LVT_LVTH16374A_7 Modifications: 74LVT_LVTH16374A_6 Modifications: • • • • 74LVTH16374ABQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. product data sheet 74LVT16374A_5 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type numbers 74LVTH16374ADGG (TSSOP48) and 74LVTH16374ABQ (HUQFN60U) product data sheet product specification product specification product specification 74LVT16374A_4 74LVT16374A_3 74LVT16374A_2 - 20100118 74LVT16374A_5 74LVT16374A_4 74LVT16374A_3 74LVT16374A_2 20040916 20021101 19991018 19980219 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 16 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVT_LVTH16374A_7 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 17 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT_LVTH16374A_7 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 07 — 22 March 2010 18 of 19 NXP Semiconductors 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 March 2010 Document identifier: 74LVT_LVTH16374A_7