74LVT16501ADGG,112

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74LVT16501A 3.3 V LVT 18-bit universal bus transceiver; 3-state Rev. 04 — 19 May 2006 Product data sheet 1. General description The 74LVT16501A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH and OEBA is active LOW). Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features n n n n n n n n n n n n 18-bit bidirectional bus interface 3-state buffers Output capability: +64 mA to −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Positive-edge triggered clock inputs Latch-up protection: u JESD78: exceeds 500 mA n ESD protection: u MIL STD 883, method 3015: exceeds 2000 V u Machine model: exceeds 200 V 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 3. Quick reference data Table 1. Quick reference data GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit tPLH propagation delay An to Bn or Bn to An CL = 50 pF; VCC = 3.3 V - 1.9 - ns tPHL propagation delay An to Bn or Bn to An CL = 50 pF; VCC = 3.3 V - 1.9 - ns Ci input capacitance (control pins) VI = 0 V or 3.0 V - 3 - pF Cio input/output capacitance (I/O pins) outputs disabled; VI/O = 0 V or 3.0 V - 9 - pF ICC quiescent supply current outputs disabled; VCC = 3.6 V - 70 - µA 4. Ordering information Table 2. Ordering information Type number 74LVT16501ADL Package Temperature range Name Description Version −40 °C to +85 °C SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74LVT16501ADGG −40 °C to +85 °C 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 2 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 5. Functional diagram LEAB OEAB CPAB LEBA B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 1 CPBA 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 28 27 55 2 OEBA 1 OEAB 55 CPAB 2 LEAB A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 OEBA 30 CPBA 28 LEBA 3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 001aad339 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 EN1 2C3 C3 G2 EN4 5C6 C6 G5 3D 4 1 1 54 1 6D 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 001aad338 Fig 1. Logic symbol OEAB CPAB LEAB LEBA CPBA OEBA A0 Fig 2. IEC logic symbol 1 55 2 28 30 27 3 ID C1 CLK 54 B0 ID C1 CLK to 17 other channels 001aaf011 Fig 3. Logic diagram 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 3 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 6. Pinning information 6.1 Pinning OEAB 1 56 GND LEAB 2 55 CPAB A0 3 54 B0 GND 4 53 GND A1 5 52 B1 A2 6 51 B2 VCC 7 A3 8 50 VCC 49 B3 A4 9 48 B4 A5 10 47 B5 GND 11 46 GND A6 12 45 B6 A7 13 44 B7 A8 14 A9 15 43 B8 74LVT16501A 42 B9 A10 16 41 B10 A11 17 40 B11 GND 18 39 GND A12 19 38 B12 A13 20 37 B13 A14 21 36 B14 VCC 22 A15 23 35 VCC 34 B15 A16 24 33 B16 GND 25 32 GND A17 26 31 B17 OEBA 27 30 CPBA LEBA 28 29 GND 001aaf010 Fig 4. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description OEAB 1 A-to-B output enable input LEAB 2 A-to-B latch enable input A0 3 data input or output A0 GND 4 ground (0 V) A1 5 data input or output A1 A2 6 data input or output A2 VCC 7 voltage supply A3 8 data input or output A3 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 4 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state Table 3. Pin description …continued Symbol Pin Description A4 9 data input or output A4 A5 10 data input or output A5 GND 11 ground (0 V) A6 12 data input or output A6 A7 13 data input or output A7 A8 14 data input or output A8 A9 15 data input or output A9 A10 16 data input or output A10 A11 17 data input or output A11 GND 18 ground (0 V) A12 19 data input or output A12 A13 20 data input or output A13 A14 21 data input or output A14 VCC 22 voltage supply A15 23 data input or output A15 A16 24 data input or output A16 GND 25 ground (0 V) A17 26 data input or output A17 OEBA 27 B-to-A output enable input (active LOW) LEBA 28 B-to-A latch enable input GND 29 ground (0 V) CPBA 30 B-to-A clock input (active rising edge) B17 31 data input or output B17 GND 32 ground (0 V) B16 33 data input or output B16 B15 34 data input or output B15 VCC 35 voltage supply B14 36 data input or output B14 B13 37 data input or output B13 B12 38 data input or output B12 GND 39 ground (0 V) B11 40 data input or output B11 B10 41 data input or output B10 B9 42 data input or output B9 B8 43 data input or output B8 B7 44 data input or output B7 B6 45 data input or output B6 GND 46 ground (0 V) B5 47 data input or output B5 B4 48 data input or output B4 B3 49 data input or output B3 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 5 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state Table 3. Pin description …continued Symbol Pin Description VCC 50 voltage supply B2 51 data input or output B2 B1 52 data input or output B1 GND 53 ground (0 V) B0 54 data input or output B0 CPAB 55 A-to-B clock input (active rising edge) GND 56 ground (0 V) 7. Functional description 7.1 Function table Table 4. Function table[1] Operating mode Control Input OEAB LEAB CPAB An OEBA LEBA CPBA Bn Output Bn An Disabled L H X X X Z Disabled, latch data L ↓ X h H Z l L Z Disabled, hold data L L H or L X NC Z Disabled, clock data L L ↑ h H Z l L Z H H H L L L Transparent Latch data and display Clock data and display Hold data and display [1] H H H H H ↓ L L X X ↑ H or L h H H l L L h H H l L L X H H X L L H = HIGH voltage level; h = HIGH voltage level one setup time prior to the enable or clock transition; L = LOW voltage level; I = LOW voltage level one setup time prior to the enable or clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↓ = HIGH-to-LOW enable transition; ↑ = LOW-to-HIGH clock transition. 74LVT16501A_4 Product data sheet Internal register © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 6 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +4.6 V VI input voltage [1] −0.5 +7.0 V VO output voltage output in OFF-state or HIGH-state [1] −0.5 +7.0 V IIK input clamping current VI < 0 V - −50 mA IOK output clamping current VO < 0 V - −50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - −64 mA −65 +150 °C - 150 °C storage temperature Tstg [2] junction temperature Tj [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9. Recommended operating conditions Table 6. Recommended operating conditions Min Typ Max Unit VCC Symbol Parameter supply voltage Conditions 2.7 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-state input voltage 2.0 - - V VIL LOW-state input voltage - - 0.8 V IOH HIGH-state output current - - −32 mA IOL LOW-state output current none - - 32 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 64 mA ∆t/∆V input transition rise and fall rate outputs enabled - - 10 ns/V Tamb ambient temperature free air −40 - +85 °C 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 7 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 Conditions Min Typ Max Unit °C[1] VIK input clamping voltage VCC = 2.7 V; IIK = −18 mA - −0.85 −1.2 V VOH HIGH-state output voltage VCC = 2.7 V to 3.6 V; IOH = −100 µA VCC − 0.2 VCC - V VCC = 2.7 V; IOH = −8 mA 2.4 2.55 - V VCC = 3.0 V; IOH = −32 mA 2.0 2.3 - V IOL = 100 µA - 0.07 0.2 V IOL = 24 mA - 0.3 0.5 V IOL = 16 mA - 0.25 0.4 V IOL = 32 mA - 0.3 0.5 V - 0.36 0.55 V - 0.1 0.55 V - 0.1 ±1 µA - 0.1 10 µA VI = 5.5 V - 1.0 20 µA VI = VCC - 0.1 10 µA VOL LOW-state output voltage VCC = 2.7 V VCC = 3.0 V IOL = 64 mA VRST power-up output low voltage ILI input leakage current control pins VCC = 3.6 V; IO = 1 mA; VI = VCC or GND [2] VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V I/O data pins VCC = 3.6 V [3] VI = 0 V IOFF IHOLD power-off leakage current bus hold current data input VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 3.0 V VI = 2.0 V external current into output output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OEAB or OEBA don’t care ICC quiescent supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A [5] outputs HIGH-state outputs LOW-state outputs disabled 74LVT16501A_4 Product data sheet −5 µA ±100 µA 75 130 - µA −75 −130 - µA ±500 - - µA - 50 125 µA - 40 ±100 µA - 0.07 0.12 mA - 4 5 mA - 0.07 0.12 mA [4] VI = 0 V to 3.6 V IEX +0.1 1.0 [4] VI = 0.8 V VCC = 3.6 V - [6] © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 8 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit - 0.1 0.2 mA ∆ICC additional quiescent supply current per input pin; VCC = 3.0 V to 3.6 V; one input at VCC − 0.6 V, other inputs at VCC or GND Ci input capacitance (control pins) VI = 0 V or 3.0 V - 3 - pF Cio input/output capacitance (I/O pins) outputs disabled; VI/O = 0 V or 3.0 V - 9 - pF [7] [1] Typical values are at VCC = 3.3 V and Tamb = 25 °C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at VCC or GND. [4] This is the bus hold overdrive current required to force the input to the opposite logic state. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [6] ICC is measured with outputs pulled to VCC or GND. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions Min Typ Max Unit An to Bn or Bn to An see Figure 5 - - 5.4 ns CPAB to Bn or CPBA to An see Figure 6 - - 6.4 ns LEAB to Bn or LEBA to An see Figure 7 - - 6.4 ns - - An to Bn or Bn to An see Figure 5 - - 5.4 ns CPAB to Bn or CPBA to An see Figure 6 - - 6.4 ns LEAB to Bn or LEBA to An see Figure 7 - - 6.4 ns VCC = 2.7 V; Tamb = −40 °C to +85 °C tPLH tPHL propagation delay propagation delay tPZH output enable time to HIGH-state see Figure 8 - - 5.5 ns tPZL output enable time to LOW-state see Figure 9 - - 5.2 ns tPHZ output disable time from HIGH-state see Figure 8 - - 6.3 ns tPLZ output disable time from LOW-state see Figure 9 - - 5.6 ns tsu(H) setup time HIGH see Figure 10 An to CPAB or Bn to CPBA 2.4 - - ns An to LEAB with CPAB LOW or Bn to LEBA with CPBA LOW 2.0 - - ns An to LEAB with CPAB HIGH or Bn to LEBA with CPBA HIGH 1.5 - - ns 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 9 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions tsu(L) see Figure 10 th(H) th(L) tWH tWL Min Typ Max Unit An to CPAB or Bn to CPBA 2.4 - - ns An to LEAB with CPAB LOW or Bn to LEBA with CPBA LOW 2.0 - - ns An to LEAB with CPAB HIGH or Bn to LEBA with CPBA HIGH 1.5 - - ns An to CPAB or Bn to CPBA 0 - - ns An to LEAB or Bn to LEAB 0.4 - - ns setup time LOW hold time HIGH see Figure 10 hold time LOW see Figure 10 An to CPAB or Bn to CPBA 0 - - ns An to LEAB or Bn to LEAB 0.4 - - ns pulse width HIGH - CPAB or CPBA see Figure 6 1.5 - - ns LEAB or LEBA see Figure 7 1.5 - - ns pulse width LOW see Figure 6 1.5 - - ns An to Bn or Bn to An see Figure 5 0.5 1.9 4.2 ns CPAB to Bn or CPBA to An see Figure 6 1.0 3.2 5.4 ns LEAB to Bn or LEBA to An see Figure 7 1.0 2.4 5.4 ns An to Bn or Bn to An see Figure 5 0.5 1.9 4.2 ns CPAB to Bn or CPBA to An see Figure 6 1.0 3.2 5.4 ns LEAB to Bn or LEBA to An see Figure 7 1.0 2.9 5.4 ns CPAB or CPBA VCC = 3.3 V ± 0.3 V; Tamb = −40 °C to +85 tPLH tPHL - °C[1] propagation delay propagation delay tPZH output enable time to HIGH-state see Figure 8 1.0 2.4 4.8 ns tPZL output enable time to LOW-state see Figure 9 1.0 2.2 4.8 ns tPHZ output disable time from HIGH-state see Figure 8 1.0 2.8 5.8 ns tPLZ output disable time from LOW-state see Figure 9 1.0 3.2 5.2 ns tsu(H) setup time HIGH see Figure 10 An to CPAB or Bn to CPBA 2.1 1.0 - ns An to LEAB with CPAB LOW or Bn to LEBA with CPBA LOW 1.8 1.6 - ns An to LEAB with CPAB HIGH or Bn to LEBA with CPBA HIGH 2.0 1.6 - ns An to CPAB or Bn to CPBA 2.1 0.7 - ns An to LEAB with CPAB LOW or Bn to LEBA with CPBA LOW 1.8 1.6 - ns An to LEAB with CPAB HIGH or Bn to LEBA with CPBA HIGH 2.0 1.6 - ns tsu(L) setup time LOW see Figure 10 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 10 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions Min Typ Max Unit th(H) see Figure 10 0.3 0 - ns 0.2 0 - ns An to CPAB or Bn to CPBA 0.3 0 - ns An to LEAB or Bn to LEAB 0.2 0 - ns hold time HIGH An to CPAB or Bn to CPBA An to LEAB or Bn to LEAB hold time LOW th(L) see Figure 10 pulse width HIGH tWH CPAB or CPBA see Figure 6 1.2 0.8 - ns LEAB or LEBA see Figure 7 1.2 0.8 - ns see Figure 6 1.2 0.8 - ns see Figure 6 150 - - MHz tWL pulse width LOW fmax maximum input clock frequency CPAB or CPBA [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 12. Waveforms VI input An or Bn VM VM 0V t PLH t PHL VOH output Bn or An VM VM VOL 001aad308 Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 11 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 1/f max VI input CPBA or CPAB VM VM VM 0V t WH t WL t PHL t PLH VOH output An or Bn VM VM VOL 001aad254 Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay clock (CPAB, CPBA) to output (An, Bn), clock (CPAB, CPBA) pulse width and maximum clock frequency (CPAB, CPBA) VI input LEAB or LEBA VM VM VM 0V t WH t PHL t PLH VOH output An or Bn VM VM VOL 001aad310 Measurement points are given in Table 9. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable (LEAB, LEBA) pulse width OEBA VI VM input OEAB VM 0V t PZH t PHZ VOH output An or Bn VY VM 0V 001aad344 Measurement points are given in Table 9. VOH is typical voltage output drop that occur with the output load. Fig 8. 3-state output enable time to HIGH-state and output disable time from HIGH-state 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 12 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state VI OEBA VM input VM 0V OEAB t PZL t PLZ 3.0 V or VCC output An or Bn VM VX VOL 001aad346 Measurement points are given in Table 9. VOL is typical voltage output drop that occur with the output load. Fig 9. 3-state output enable time to LOW-state and output disable time from LOW-state VI LEAB or LEBA VM VM input CPAB or CPBA 0 V t su(H) t h(H) t su(L) t h(L) VI input An, Bn VM VM VM VM 0V 001aad342 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. Data setup and hold times Table 9. Measurement points Supply voltage Input Output VM VM VX VY 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.3 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 13 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 10. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 11. Load circuitry for switching times Table 10. Test data Input Load fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 74LVT16501A_4 Product data sheet VEXT VI 6V open © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 14 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 13. Package outline SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE v M A Z 29 56 Q A2 A1 A (A 3) θ pin 1 index Lp L 28 1 bp e 0 detail X w M 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-118 Fig 12. Package outline SOT371-1 (SSOP56) 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 15 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 13. Package outline SOT364-1 (TSSOP56) 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 16 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 14. Abbreviations Table 11. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT16501A_4 20060519 Product data sheet - 74LVT16501A_3 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • • • • Section 2: replaced JESD17 with JESD78. Figure 3: corrected clock names. Table 7: changed IHOLD conditions VCC = 0 V to 3.6 V into VI = 0 V to 3.6 V. Table 8: – Changed values for output enable and output disable times. – Added new parameters and changed values for setup and hold times. 74LVT16501A_3 19980219 Product specification - 74LVT16501A_2 74LVT16501A_2 19970612 Product specification - 74LVT16501A_1 74LVT16501A_1 - - - - 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 17 of 19 74LVT16501A Philips Semiconductors 3.3 V LVT 18-bit universal bus transceiver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74LVT16501A_4 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 04 — 19 May 2006 18 of 19 Philips Semiconductors 74LVT16501A 3.3 V LVT 18-bit universal bus transceiver; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 19 May 2006 Document identifier: 74LVT16501A_4