74LVT273DB

74LVT273 3.3 V octal D-type flip-flop Rev. 03 — 10 September 2008 Product data sheet 1. General description The 74LVT273 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where only the true output is required and the CP and MR are common elements. 2. Features I I I I I I I I Eight edge-triggered D-type flip-flops Buffered common clock and asynchronous master reset Input and output interface capability to systems at 5 V supply TTL input and output switching levels Input and output interface capability to systems at 5 V supply Output capability: +64 mA/−32 mA Latch-up protection N JESD78 Class II exceeds 500 mA ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs Live insertion/extraction permitted Power-up reset No bus current loading when output is tied to 5 V bus I I I I NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVT273D 74LVT273DB 74LVT273PW 74LVT273BQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SO20 SSOP20 TSSOP20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT339-1 SOT360-1 SOT764-1 Type number DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 4. Functional diagram 11 1 CP MR 11 3 4 7 8 13 14 17 18 CP D0 D1 D2 D3 D4 D5 D6 D7 MR 1 mna763 C1 R Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 1D 2 5 6 9 12 15 16 19 mna764 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 2 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop D0 D1 D2 D3 D Q D Q D Q D Q CP FF1 RD CP CP FF2 RD CP FF3 RD CP FF4 RD MR Q0 D4 D5 Q1 D6 Q2 D7 Q3 D Q D Q D Q D Q CP FF5 RD CP FF6 RD CP FF7 RD CP FF8 RD Q4 Q5 Q6 Q7 001aae056 Fig 3. Logic diagram 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 3 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop 5. Pinning information 5.1 Pinning 74LVT273 terminal 1 index area 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 GND(1) GND 10 CP 11 13 D4 12 Q4 MR 2 3 4 5 6 7 8 9 1 74LVT273 MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP 001aai737 Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 10 001aai738 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration for SO20 and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Symbol MR Q0 to Q7 D0 to D7 GND CP VCC Pin description Pin 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 Description master reset input (active LOW) data output data input ground (0 V) clock pulse input (active on rising edge) positive supply voltage 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 4 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop 6. Functional description Table 3. Inputs MR L H H H [1] Function selection Outputs CP X ↑ ↑ L Dn X h l X Qn L H L Q0 Reset (clear) Load 1 Load 0 Retain state Operating mode H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition; X = Don’t care; ↑ = LOW-to-HIGH clock transition; Q0 = output as it was. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO Tstg Tj Ptot [1] [2] [3] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current storage temperature junction temperature total power dissipation Conditions [1] Min −0.5 −0.5 −0.5 −50 −50 −64 −65 [2] Max +4.6 +7.0 +7.0 128 +150 150 500 Unit V V V mA mA mA mA °C °C mW Output in OFF or HIGH state VI < 0 V VO < 0 V output in LOW state output in HIGH state [1] - Tamb = −40 °C to +85 °C [3] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. For SO20 packages: above 70 °C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC VI IOH Recommended operating conditions Parameter supply voltage input voltage HIGH-level output current Conditions Min 2.7 0 −32 Typ Max 3.6 5.5 Unit V V mA 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 5 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop Table 5. Symbol IOL Tamb ∆t/∆V Recommended operating conditions …continued Parameter LOW-level output current ambient temperature input transition rise and fall rate; output enabled in free air Conditions Min −40 Typ Max 64 +85 10 Unit mA °C ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIK VIH VIL VOH input clamping voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 2.7 V to 3.6V; IOH = −100 µA VCC = 2.7 V; IOH = −8 mA VCC = 3.0 V; IOH = −32 mA VOL LOW-level output voltage VCC = 2.7 V; IOL = 100 µA VCC = 2.7 V; IOL = 24 mA VCC = 3.0 V; IOL = 16 mA VCC = 3.0 V; IOL = 32 mA VCC = 3.0 V; IOL = 64 mA VOL(pu) II power-up LOW-level output voltage input leakage current VCC = 3.6 V; IO = 1 mA; VI = GND or VCC input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND data pins VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V IOFF ILO IBHL IBHH IBHHO IBHLO power-off leakage current output leakage current bus hold LOW current bus hold HIGH current bus hold HIGH overdrive current bus hold LOW overdrive current VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 3.0 V; VO = 5.5 V; output HIGH VCC = 3.0 V; VI = 0.8 V VCC = 3.0 V; VI = 2.0 V VCC = 3.6 V; VI = 0 V to 3.6 V VCC = 3.6 V; VI = 0 V to 3.6 V [4] [3] [2] Conditions VCC = 2.7V; IIK = –18 mA −40 °C to +85 °C Min −1.2 2.0 2.4 2.0 Typ[1] −0.9 2.5 2.2 0.1 0.3 0.25 0.3 0.4 0.13 Max 0.8 0.2 0.5 0.4 0.5 0.55 0.55 Unit V V V V V V V V V V V VCC − 0.2 VCC − 0.1 −5 75 −500 1 ±0.1 0.1 −1 1 60 150 −150 - 10 ±1 1 − ±100 125 −75 500 - µA µA µA µA µA µA µA µA µA µA 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 6 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC supply current Conditions VCC = 3.6 V; VI = VCC or GND; IO = 0 A outputs HIGH outputs LOW ∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input = VCC − 0.6 V other inputs at VCC or GND VI = 0 V or 3.0 V [5] −40 °C to +85 °C Min Typ[1] 0.13 3 0.1 Max 0.19 12 0.2 Unit mA mA mA CI [1] [2] [3] [4] [5] input capacitance - 4 - pF All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. For valid test results data must not be loaded into the flip-flops (or latches) after applying the power. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. Increase in supply current for each input at the specified voltage level other than VCC or GND 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tPLH LOW to HIGH propagation delay Conditions CP to Qn; Figure 6 VCC = 2.7 V VCC = 3.3 V ± 0.3 V tPHL HIGH to LOW propagation delay CP to Qn; Figure 6 VCC = 2.7 V VCC = 3.3 V ± 0.3 V MR to Qn; see Figure 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V tsu set-up time Dn to CP HIGH; see Figure 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V Dn to CP LOW; see Figure 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V th hold time Dn to CP HIGH; see Figure 8 VCC = 2.7 V VCC = 3.3 V ± 0.3 V Dn to CP LOW; see Figure 8 VCC = 2.7 V VCC = 3.3 V ± 0.3 V 74LVT273_3 −40 °C to +85 °C Min 1.7 1.9 1.3 [2] Unit Typ[1] 3.5 3.5 3.2 1.0 1.0 −0.6 −0.6 Max 6.3 5.5 5.9 5.5 6.2 6.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2.7 2.3 2.7 2.3 [3] 0 0 0 0 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 7 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tW pulse width Conditions CP input HIGH or LOW; see Figure 6 VCC = 2.7 V VCC = 3.3 V ± 0.3 V MR input LOW; see Figure 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V trec recovery time see Figure 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V fmax [1] [2] [3] [4] [4] −40 °C to +85 °C Min 3.3 3.3 3.3 3.3 3.2 2.7 150 Typ[1] 1.5 1.5 1.0 Max - Unit ns ns ns ns ns ns MHz maximum frequency CP input; see Figure 7 Typical values are measured at Tamb = 25 °C and VCC = 3.3 V tsu is the same as tsu(L) and tsu(H) th is the same as th(L) and th(H) tW is the same as tWL and tWH 11. Waveforms 1/fmax VI CP input GND tWH tPHL VOH Qn output VOL VM 001aai739 VM tWL tPLH see Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Table 8. Input VI 2.7 V CP Input to Qn output propagation delays and clock pulse width and maximum frequency Measurement points Output VM 1.5 V VM 1.5 V 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 8 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop VI MR input GND VM tWL VI CP input GND trec VM tPHL VOH Qn output VOL 001aai740 VM see Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. MR pulse width, MR to CP recovery time and MR to Qn delay VI CP input GND tsu(H) th(H) VI Dn input GND VM tsu(L) th(L) VM VOH Qn output VOL 001aai741 VM see Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 8. Data set-up and hold times 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 9 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VCC PULSE GENERATOR VI DUT RT CL RL VO 001aaf615 Test data is given in given in Table 9. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Table 9. Input VI 2.7 V Load circuitry for switching times Test data Load Repetition rate ≤ 10 MHz tW 500 ns tr, tf ≤ 2.5 ns RL 500 Ω CL 50 pF 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 10 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT163-1 (SO20) 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 11 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 10 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT339-1 (SSOP20) 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 12 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT360-1 (TSSOP20) 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 13 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT764-1 (DHVQFN20) 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 14 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop 13. Abbreviations Table 10. Acronym BiCMOS CDM DUT ESD HBM TTL Abbreviations Description Integrated Bipolar junction transistors and CMOS Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20080910 Data sheet status Product data sheet Change notice Supersedes 74LVT273_2 Document ID 74LVT273_3 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Title changed to 3.3 V octal D-type flip-flop Section 3 “Ordering information” and Section 12 “Package outline” DHVQFN20 package added. Table 4 “Limiting values” Tj and Ptot values added. Product specification - 74LVT273_2 19980219 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 15 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop 15. Legal information 16. Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.2 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 16 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 September 2008 Document identifier: 74LVT273_3