74LVT273PW,118

74LVT273 3.3 V octal D-type flip-flop Rev. 03 — 10 September 2008 Product data sheet 1. General description The 74LVT273 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independent of the clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where only the true output is required and the CP and MR are common elements. 2. Features n n n n n n n n n n n n Eight edge-triggered D-type flip-flops Buffered common clock and asynchronous master reset Input and output interface capability to systems at 5 V supply TTL input and output switching levels Input and output interface capability to systems at 5 V supply Output capability: +64 mA/−32 mA Latch-up protection u JESD78 Class II exceeds 500 mA ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs Live insertion/extraction permitted Power-up reset No bus current loading when output is tied to 5 V bus 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT273D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVT273DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 74LVT273PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVT273BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm SOT764-1 4. Functional diagram CP MR 11 1 C1 R 11 3 4 7 8 13 14 17 18 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D0 2 D1 5 6 D2 9 D3 12 D4 15 D5 16 D6 19 MR 1 Fig 1. Logic symbol D7 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 mna763 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna764 Fig 2. IEC logic symbol 74LVT273_3 Product data sheet 3 © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 2 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop D0 D1 D Q D2 D Q D3 D Q D Q CP FF1 CP FF2 CP FF3 CP FF4 RD RD RD RD CP MR Q0 D4 Q1 D5 D Q Q2 D6 D Q Q3 D7 D Q D Q CP FF5 CP FF6 CP FF7 CP FF8 RD RD RD RD Q4 Q5 Q6 Q7 001aae056 Fig 3. Logic diagram 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 3 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop 5. Pinning information 5.1 Pinning 1 terminal 1 index area Q0 2 19 Q7 D0 3 18 D7 20 VCC 19 Q7 D1 4 17 D6 5 16 Q6 15 Q5 1 Q0 2 D0 3 18 D7 Q1 Q2 6 4 17 D6 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP D2 7 D3 8 Q3 9 14 D5 GND(1) 13 D4 12 Q4 GND 10 D1 Q1 CP 11 74LVT273 MR 20 VCC MR 74LVT273 001aai738 Transparent top view 001aai737 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration for SO20 and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 master reset input (active LOW) Q0 to Q7 2, 5, 6, 9, 12, 15, 16, 19 data output D0 to D7 3, 4, 7, 8, 13, 14, 17, 18 data input GND 10 ground (0 V) CP 11 clock pulse input (active on rising edge) VCC 20 positive supply voltage 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 4 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop 6. Functional description Table 3. Function selection Inputs Outputs Operating mode MR CP Dn Qn L X X L Reset (clear) H ↑ h H Load 1 H ↑ l L Load 0 H L X Q0 Retain state [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the prior to the LOW-to-HIGH clock transition; X = Don’t care; ↑ = LOW-to-HIGH clock transition; Q0 = output as it was. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage [1] VO output voltage Output in OFF or HIGH state [1] IIK input clamping current VI < 0 V IOK output clamping current VO < 0 V −50 - mA IO output current output in LOW state - 128 mA output in HIGH state −64 - mA −65 +150 °C - 150 °C 500 mW storage temperature Tstg Tj junction temperature Ptot total power dissipation [2] Tamb = −40 °C to +85 °C Min Max Unit −0.5 +4.6 V −0.5 +7.0 V −0.5 +7.0 V −50 - mA [3] [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] For SO20 packages: above 70 °C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V IOH HIGH-level output current −32 - - mA 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 5 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop Table 5. Recommended operating conditions …continued Symbol Parameter IOL LOW-level output current Tamb ambient temperature ∆t/∆V input transition rise and fall rate; output enabled Conditions in free air Min Typ Max Unit - - 64 mA −40 - +85 °C - - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIK input clamping voltage −40 °C to +85 °C Conditions VCC = 2.7V; IIK = –18 mA Unit Min Typ[1] Max −1.2 −0.9 - V V VIH HIGH-level input voltage 2.0 - - VIL LOW-level input voltage - - 0.8 VOH HIGH-level output voltage VOL LOW-level output voltage VCC = 2.7 V to 3.6V; IOH = −100 µA VCC − 0.2 VCC − 0.1 VCC = 2.7 V; IOH = −8 mA 2.4 VCC = 3.0 V; IOH = −32 mA 2.0 VCC = 2.7 V; IOL = 100 µA 2.5 - V - V 2.2 - V 0.1 0.2 V VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 64 mA - 0.4 0.55 V - 0.13 0.55 V - 1 10 µA - ±0.1 ±1 µA VCC = 3.6 V; VI = VCC - 0.1 1 µA VCC = 3.6 V; VI = 0 V −5 −1 − µA - 1 ±100 µA VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = GND or VCC II input leakage current input pins [2] VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND data pins IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V ILO output leakage current VCC = 3.0 V; VO = 5.5 V; output HIGH IBHL bus hold LOW current VCC = 3.0 V; VI = 0.8 V IBHH bus hold HIGH current IBHHO IBHLO [3] - 60 125 µA 75 150 - µA VCC = 3.0 V; VI = 2.0 V - −150 −75 µA bus hold HIGH overdrive current VCC = 3.6 V; VI = 0 V to 3.6 V - - 500 µA bus hold LOW overdrive current VCC = 3.6 V; VI = 0 V to 3.6 V −500 - - µA 74LVT273_3 Product data sheet [4] © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 6 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC supply current −40 °C to +85 °C Conditions Unit Min Typ[1] Max outputs HIGH - 0.13 0.19 mA outputs LOW - 3 12 mA - 0.1 0.2 mA - 4 - pF VCC = 3.6 V; VI = VCC or GND; IO = 0 A ∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input = VCC − 0.6 V other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V [5] [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. [2] For valid test results data must not be loaded into the flip-flops (or latches) after applying the power. [3] Unused pins at VCC or GND. [4] This is the bus hold overdrive current required to force the input to the opposite logic state. [5] Increase in supply current for each input at the specified voltage level other than VCC or GND 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tPLH LOW to HIGH propagation delay −40 °C to +85 °C Conditions VCC = 3.3 V ± 0.3 V HIGH to LOW propagation delay Min Max - - 6.3 ns 1.7 3.5 5.5 ns CP to Qn; Figure 6 VCC = 2.7 V tPHL Unit Typ[1] CP to Qn; Figure 6 VCC = 2.7 V - - 5.9 ns 1.9 3.5 5.5 ns - - 6.2 ns 1.3 3.2 6.2 ns VCC = 2.7 V 2.7 - - ns VCC = 3.3 V ± 0.3 V 2.3 1.0 - ns 2.7 - - ns 2.3 1.0 - ns VCC = 3.3 V ± 0.3 V MR to Qn; see Figure 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V tsu set-up time Dn to CP HIGH; see Figure 7 [2] Dn to CP LOW; see Figure 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V th hold time Dn to CP HIGH; see Figure 8 [3] VCC = 2.7 V 0 - - ns VCC = 3.3 V ± 0.3 V 0 −0.6 - ns VCC = 2.7 V 0 - - ns VCC = 3.3 V ± 0.3 V 0 −0.6 - ns Dn to CP LOW; see Figure 8 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 7 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter −40 °C to +85 °C Conditions Min tW pulse width CP input HIGH or LOW; see Figure 6 Unit Typ[1] Max [4] VCC = 2.7 V 3.3 - - ns VCC = 3.3 V ± 0.3 V 3.3 1.5 - ns VCC = 2.7 V 3.3 - - ns VCC = 3.3 V ± 0.3 V 3.3 1.5 - ns VCC = 2.7 V 3.2 - - ns VCC = 3.3 V ± 0.3 V 2.7 1.0 - ns CP input; see Figure 7 150 - - MHz MR input LOW; see Figure 7 recovery time trec see Figure 7 maximum frequency fmax [1] Typical values are measured at Tamb = 25 °C and VCC = 3.3 V [2] tsu is the same as tsu(L) and tsu(H) [3] th is the same as th(L) and th(H) [4] tW is the same as tWL and tWH 11. Waveforms 1/fmax VI CP input VM GND tWH tWL tPLH tPHL VOH VM Qn output VOL 001aai739 see Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Table 8. CP Input to Qn output propagation delays and clock pulse width and maximum frequency Measurement points Input Output VI VM VM 2.7 V 1.5 V 1.5 V 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 8 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop VI VM MR input GND tWL trec VI CP input VM GND tPHL VOH VM Qn output VOL 001aai740 see Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. MR pulse width, MR to CP recovery time and MR to Qn delay VI VM CP input GND tsu(H) tsu(L) th(H) th(L) VI VM Dn input GND VOH VM Qn output VOL 001aai741 see Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig 8. Data set-up and hold times 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 9 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in given in Table 9. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Table 9. Load circuitry for switching times Test data Input Load VI Repetition rate tW tr, tf RL CL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω 50 pF 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 10 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT163-1 (SO20) 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 11 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT339-1 (SSOP20) 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 12 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT360-1 (TSSOP20) 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 13 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT764-1 (DHVQFN20) 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 14 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Integrated Bipolar junction transistors and CMOS CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT273_3 20080910 Product data sheet - 74LVT273_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. • 74LVT273_2 Title changed to 3.3 V octal D-type flip-flop Section 3 “Ordering information” and Section 12 “Package outline” DHVQFN20 package added. Table 4 “Limiting values” Tj and Ptot values added. 19980219 Product specification 74LVT273_3 Product data sheet - - © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 15 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop 15. Legal information 16. Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.2 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 10 September 2008 16 of 17 74LVT273 NXP Semiconductors 3.3 V octal D-type flip-flop 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 September 2008 Document identifier: 74LVT273_3