74LVT373PW,118

74LVT373 3.3 V octal D-type transparent latch; 3-state Rev. 3 — 21 November 2011 Product data sheet 1. General description The 74LVT373 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by latch enable (LE) and output enable (OE) control gates. The data on the Dn inputs are transferred to the latch outputs when the latch enable (LE) input is HIGH. The latch remains transparent to the data inputs while LE is HIGH, and stores the data that is present one setup time before the HIGH-to-LOW enable transition. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active-low output enable (OE) controls all eight 3-state buffers independent of the latch operation. When OE is LOW, the latched or transparent data appears at the outputs. When OE is HIGH, the outputs are in the high-impedance OFF-state, which means they will neither drive nor load the bus. The 74LVT373 is functionally identical to the 74LVT573, but has a different pin arrangement. 2. Features and benefits            Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state Latch-up protection  JESD78 class II exceeds 500 mA  ESD protection:  HBM JESD22-A114E exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT373D 40 C to +85 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVT373PW 40 C to +85 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 4. Functional diagram 1 OE LE EN 11 C1 11 3 4 7 8 13 14 17 18 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 2 6 D4 15 D5 16 D6 19 D7 1 Q 8 9 13 12 14 15 17 16 18 19 D2 D Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae049 Fig 2. D1 D 6 001aae048 Logic symbol D0 7 D3 12 Q0 5 D2 9 2 1D 4 D1 5 OE Fig 1. 3 D0 LE D3 D Q IEC logic symbol D4 D Q D5 D Q D6 D Q D7 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae052 Fig 3. Logic diagram 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state 5. Pinning information 5.1 Pinning 74LVT373 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 LE aaa-000410 Fig 4. Pin configuration for SO20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) D0 to D7 3, 4, 7, 8, 13, 14, 17, 18 data input GND 10 ground (0 V) LE 11 latch enable (active HIGH) Q0 to Q7 2, 5, 6, 9, 12, 15, 16, 19 data output VCC 20 supply voltage 6. Functional description 6.1 Function table Table 3. Function table [1] Operating mode Control OE Control LE Input Dn Internal register Output Qn Load and read register enable L H L L L H H H Latch and read register L l L L h H H  Hold L L X NC NC Disable outputs H L X NC Z H Dn Dn Z [1] H = HIGH voltage level; L = LOW voltage level; 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state  = HIGH-to-LOW latch enable transition; h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition; l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition; Z = high-impedance OFF-state; NC = no change; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +4.6 V 0.5 +7.0 V input voltage [1] VO output voltage output in OFF-state or HIGH-state [1] 0.5 +7.0 V IIK input clamping current VI < 0 V - 50 mA IOK output clamping current VO < 0 V - 50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - 64 mA Tstg storage temperature 65 +150 C Tj junction temperature [2] - 150 C [3] - 500 mW VI Tamb = 40 C to +85 C total power dissipation Ptot [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] For SO20 packages: above 70 C derate linearly with 8 mW/K. For TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Min Typ Max Unit supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current - - 32 mA IOL LOW-level output current - - 32 mA current duty cycle  50 %; fi  1 kHz - - 64 mA Tamb ambient temperature in free air 40 - +85 C t/V input transition rise and fall rate outputs enabled - - 10 ns/V 74LVT373 Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIK input clamping voltage VCC = 2.7 V; IIK = 18 mA VOH HIGH-level output voltage VCC = 2.7 V to 3.6 V; IOH = 100 A VOL Tamb = 40 C to +85 C Conditions LOW-level output voltage Min Typ[1] 1.2 0.9 VCC  0.2 VCC  0.1 VCC = 2.7 V; IOH = 8 mA 2.4 2.5 Unit Max - V - V - V VCC = 3.0 V; IOH = 32 mA 2.0 2.2 - V VCC = 2.7 V; IOL = 100 A - 0.1 0.2 V VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V VCC = 3.0 V IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V IOL = 32 mA - 0.3 0.5 V VCC = 3.0 V IOL = 64 mA - 0.4 0.55 V - 0.13 0.55 V - 1 10 A - 0.1 1 A - 0.1 1 A 5 1 - A - 1 100 A VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = GND or VCC II input leakage current all input pins; [2] VCC = 0 V or 3.6 V; VI = 5.5 V control pins; VCC = 3.6 V; VCC or GND data pins VCC = 3.6 V; VI = VCC [3] VCC = 3.6 V; VI = 0 V IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V 75 150 - A - 150 75 A - - 500 A 500 - - A - 60 125 A - 1 100 A output HIGH: VO = 3.0 V - 1 5 A output LOW: VO = 0.5 V 5 1 - A - 0.13 0.19 mA IBHL bus hold LOW current Dn input; VCC = 3 V; VI = 0.8 V IBHH bus hold HIGH current Dn input; VCC = 3 V; VI = 2.0 V IBHHO bus hold HIGH overdrive current Dn input; VCC = 3.6 V; VI = 0 V to 3.6 V IBHLO bus hold LOW overdrive current Dn input; VCC = 3.6 V; VI = 0 V to 3.6 V ILO output leakage current Qn output HIGH when VO = 5.5 V and VCC = 3.0 V IO(pu/pd) power-up/power-down output current VCC  1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OE = don’t care IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL ICC supply current [4] [4] [5] VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 [6] - 3 12 mA - 0.13 0.19 mA © NXP B.V. 2011. All rights reserved. 5 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Conditions Unit Min Typ[1] Max - 0.1 0.2 mA ICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC  0.6 V and other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF [7] [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C. [2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. [3] Unused pins at VCC or GND. [4] This is the bus hold overdrive current required to force the input to the opposite logic state. [5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V  0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. [6] ICC is measured with outputs pulled to VCC or GND. [7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 10. Symbol Parameter tPLH LOW to HIGH propagation delay Conditions Tamb = 40 C to +85 C Unit Min Typ[1] Max VCC = 3.0 V to 3.6 V 1.9 3.1 4.9 ns VCC = 2.7 V 2.6 3.7 5.3 ns LE to Qn; see Figure 5 Dn to Qn; see Figure 6 tPHL HIGH to LOW propagation delay VCC = 3.0 V to 3.6 V 1.9 3.0 4.8 ns VCC = 2.7 V 2.6 3.4 5.2 ns VCC = 3.0 V to 3.6 V 1.9 3.3 4.7 ns VCC = 2.7 V 1.9 3.4 5.0 ns VCC = 3.0 V to 3.6 V 1.8 3.0 4.8 ns VCC = 2.7 V 2.4 3.6 5.0 ns VCC = 3.0 V to 3.6 V 1.8 3.4 5.7 ns VCC = 2.7 V 3.0 4.5 6.0 ns LE to Qn; see Figure 5 Dn to Qn; see Figure 6 tPZH tPZL OFF-state to HIGH propagation delay OFF-state to LOW propagation delay 74LVT373 Product data sheet OE to Qn; see Figure 7 OE to Qn; see Figure 8 VCC = 3.0 V to 3.6 V 1.9 3.3 5.3 ns VCC = 2.7 V 2.7 4.0 5.6 ns All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 10. Symbol Parameter Tamb = 40 C to +85 C Conditions Min tPHZ HIGH to OFF-state propagation delay tPLZ VCC = 3.0 V to 3.6 V 1.8 3.2 5.1 ns 1.9 3.5 5.3 ns 2.1 3.2 4.6 ns 2.0 3.0 4.6 ns 1.1 - - ns 1.0 - - ns 1.4 - - ns 1.4 - - ns LOW to OFF-state propagation delay OE to Qn; see Figure 8 set-up time Dn to LE; see Figure 9 VCC = 3.0 V to 3.6 V [2] VCC = 2.7 V hold time Dn to LE; see Figure 9 [3] VCC = 3.0 V to 3.6 V VCC = 2.7 V pulse width tW [1] Max VCC = 2.7 V VCC = 3.0 V to 3.6 V th Unit OE to Qn; see Figure 7 VCC = 2.7 V tsu Typ[1] LE input HIGH; see Figure 5 [4] VCC = 3.0 V to 3.6 V 3.0 - - ns VCC = 2.7 V 3.0 - - ns Typical values are measured at Tamb = 25 C and VCC = 3.3 V and 2.7 V respectively. [2] tsu is the same as tsu(L) and tsu(H). [3] th is the same as th(L) and th(H). [4] tW is the same as tWL and tWH. 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state 11. Waveforms VI LE input VI VM VM Dn input 0V tWH 0V tWL tPHL VOH VOH VOL VOL 001aai743 Measurement points are given in Table 8. Fig 6. Propagation delay data input (Dn) to output (Qn) VI VI VM VM VM VM OE input 0V 0V tPZH tPHZ VOH Qn output 001aai742 Measurement points are given in Table 8. Propagation delays latch enable input (LE) to output (Qn), and latch enable (LE) pulse width OE input VM Qn output VM Qn output Fig 5. tPLH tPHL tPLH tPZL tPLZ 3.0 V VY Qn output VM VM VX VOL 0V 001aai745 001aai746 Measurement points are given in Table 8. Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Output enable time to HIGH-state and output disable time from HIGH-state Fig 8. Output enable time to LOW-state and output disable time from LOW-state VI VM Dn input 0V th(L) th(H) tsu(H) tsu(L) VI LE input VM 0V 001aai744 Measurement points are given in Table 8. Remark: The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Table 8. Data setup and hold times for data (Dn) and latch enable (LE) inputs Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 10. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V  10 MHz 500 ns  2.5 ns 50 pF 500  GND 6V open 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT163-1 (SO20) 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT360-1 (TSSOP20) 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT373 v.3 20111121 Product data sheet - 74LVT373 v.2 Modifications: • Legal pages updated. 74LVT373 v.2 20110916 Product data sheet - 74LVT373 v.1 74LVT373 v.1 19930701 Product data sheet - - 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Export might require a prior authorization from competent authorities. 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVT373 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 15 74LVT373 NXP Semiconductors 3.3 V octal D-type transparent latch; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 November 2011 Document identifier: 74LVT373