74LVTH125PW,112

74LVT125; 74LVTH125 3.3 V quad buffer; 3-state Rev. 7 — 31 May 2016 Product data sheet 1. General description The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device combines low static and dynamic power dissipation with high speed and high output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one of the 3-state outputs. 2. Features and benefits           Quad bus interface 3-state buffers Output capability: +64 mA and 32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up 3-state Latch-up protection:  JESD78: exceeds 500 mA  ESD protection:  MIL STD 883 method 3015: exceeds 2000 V  Machine model: exceeds 200 V 74LVT125; 74LVTH125 NXP Semiconductors 3.3 V quad buffer; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVT125D Temperature range Name Description Version 40 C to +85 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +85 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +85 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5  3  0.85 mm 74LVTH125D 74LVT125DB 74LVTH125DB 74LVT125PW 74LVTH125PW 74LVT125BQ 74LVTH125BQ 4. Functional diagram  $  2(  $  2( <   <     (1     $ <    2(  $  2(   <  Q$  Q<   Q2( PQD Fig 1. Logic symbol 74LVT_LVTH125 Product data sheet PQD Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 May 2016 PQD Fig 3. Logic diagram (one buffer) © NXP Semiconductors N.V. 2016. All rights reserved. 2 of 16 74LVT125; 74LVTH125 NXP Semiconductors 3.3 V quad buffer; 3-state 5. Pinning information   9&& WHUPLQDO LQGH[DUHD $   2( $  <   $  2(  9&& 2( 5.1 Pinning  <   $ *1'   <  $  *1' <   2(  $  <  2(   $  <  <    < 2( *1'  2(  2( $ DDF 7UDQVSDUHQWWRSYLHZ DDF (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14, SSOP14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1OE 1 1 output enable input (active LOW) 1A 2 1 data input 1Y 3 1 data output 2OE 4 2 output enable input (active LOW) 2A 5 2 data input 2Y 6 2 data output GND 7 ground (0 V) 3Y 8 3 data output 3A 9 3 data input 3OE 10 3 output enable input (active LOW) 4Y 11 4 data output 4A 12 4 data input 4OE 13 4 output enable input (active LOW) VCC 14 supply voltage 74LVT_LVTH125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 3 of 16 74LVT125; 74LVTH125 NXP Semiconductors 3.3 V quad buffer; 3-state 6. Functional description 6.1 Function table Table 3. Function table[1] Control Input Output nOE nA nY L L L L H H H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current IOK IO Min 0.5 +4.6 V 0.5 +7.0 V [1] 0.5 +7.0 V VI < 0 V - 50 mA output clamping current VO < 0 V - 50 mA output current output in LOW-state - 128 mA output in HIGH-state - 64 mA 65 +150 C - 150 C [2] junction temperature Tj Unit [1] storage temperature Tstg Max [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VIH Conditions Min Typ Max Unit 2.7 - 3.6 V 0 - 5.5 V HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current - - 32 mA IOL LOW-level output current none - - 32 mA current duty cycle  50 %; f  1 kHz - - 64 mA 0 - 10 ns/V 40 - +85 C t/V input transition rise and fall rate Tamb ambient temperature 74LVT_LVTH125 Product data sheet in free air All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 4 of 16 74LVT125; 74LVTH125 NXP Semiconductors 3.3 V quad buffer; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 Conditions VIK input clamping voltage IIK = 18 mA; VCC = 2.7 V VOH HIGH-level output voltage IOH = 100 A; VCC = 2.7 V to 3.6 V VOL Min Typ Max Unit - 0.9 1.2 V - V C[1] LOW-level output voltage VCC  0.2 VCC  0.1 IOH = 8 mA; VCC = 2.7 V 2.4 2.5 - V IOH = 32 mA; VCC = 3.0 V 2.0 2.2 - V IOL = 100 A - 0.1 0.2 V IOL = 24 mA - 0.3 0.5 V IOL = 16 mA - 0.25 0.4 V IOL = 32 mA - 0.3 0.5 V IOL = 64 mA - 0.4 0.55 V - 1 10 A - 0.1 1 A VCC = 3.6 V; VI = VCC - 0.1 1 A VCC = 3.6 V; VI = 0 V - 1 5 A - 1 100 A VCC = 2.7 V VCC = 3.0 V II input leakage current all input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND [2] data pins IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V 75 150 - A - 150 75 A VCC = 3.6 V; VI = 0 V to 3.6 V 500 - - A bus hold HIGH overdrive current VCC = 3.6 V; VI = 0 V to 3.6 V - - 500 A ILO output leakage current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V - 60 125 A IO(pu/pd) power-up/power-down output VCC  1.2 V; VO = 0.5 V to VCC; current VI = GND or VCC; nOE = don’t care - 1 100 A IOZ OFF-state output current output HIGH: VO = 3.0 V - 1 5 A output LOW: VO = 0.5 V - 1 5 A IBHL bus hold LOW current VCC = 3 V; VI = 0.8 V IBHH bus hold HIGH current VCC = 3 V; VI = 2.0 V IBHLO bus hold LOW overdrive current IBHHO 74LVT_LVTH125 Product data sheet [3] [4] VCC = 3.6 V; VI = VIH or VIL All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 5 of 16 74LVT125; 74LVTH125 NXP Semiconductors 3.3 V quad buffer; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions ICC VCC = 3.6 V; VI = GND or VCC; IO = 0 A supply current Min Typ Max Unit outputs HIGH - 0.13 0.19 mA outputs LOW - 2 7 mA [5] - 0.13 0.19 mA [6] - 0.1 0.2 mA outputs disabled ICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC  0.6 V and other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 C. [2] Unused pins at VCC or GND. [3] This is the bus hold overdrive current required to force the input to the opposite logic state. [4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.0 V to 3.6 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. [5] ICC is measured with outputs pulled to VCC or GND. [6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Tamb = 40 C to +85 tPLH Conditions LOW to HIGH propagation delay VCC = 2.7 V HIGH to LOW propagation delay VCC = 3.0 V to 3.6 V OFF-state to HIGH propagation delay VCC = 3.0 V to 3.6 V OFF-state to LOW propagation delay VCC = 3.0 V to 3.6 V HIGH to OFF-state propagation delay VCC = 2.7 V Product data sheet - 4.5 ns 2.7 4.0 ns - - 4.9 ns 1.0 2.9 3.9 ns - - 6.0 ns 1.0 3.4 4.7 ns - - 6.5 ns 1.1 3.4 4.7 ns - - 5.7 ns 1.8 3.7 5.1 ns nOE to nY; see Figure 7 VCC = 3.0 V to 3.6 V 74LVT_LVTH125 1.0 nOE to nY; see Figure 7 VCC = 2.7 V tPHZ Unit nOE to nY; see Figure 7 VCC = 2.7 V tPZL Max nAn to nY; see Figure 6 VCC = 2.7 V tPZH Typ nAn to nY; see Figure 6 VCC = 3.0 V to 3.6 V tPHL Min C[1] All information provided in this document is subject to legal disclaimers. Rev. 7 — 31 May 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 6 of 16 74LVT125; 74LVTH125 NXP Semiconductors 3.3 V quad buffer; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions tPLZ nOE to nY; see Figure 7 LOW to OFF-state propagation delay Min Typ Max Unit - - 4.0 ns 1.3 2.6 4.5 ns VCC = 2.7 V VCC = 3.0 V to 3.6 V [1] Typical values are at VCC = 3.3 V and Tamb = 25 C. 11. Waveforms 9, Q$LQSXW 90 90 *1' W3/+ W3+/ 92+ 90 Q