74LVTH16374ABQ,518

74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Rev. 07 — 23 March 2010 Product data sheet 1. General description The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits „ „ „ „ „ „ „ „ „ „ 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pin-out architecture Low inductance multiple supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH16374A only) High-impedance outputs when VCC = 0 V Complies with JEDEC standard JESD8-B/JESD36 ESD protection: ‹ HBM JESD22-A114F exceeds 2000 V ‹ CDM JESD22-C101D exceeds 1000 V „ Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 3. Ordering information Table 1. Ordering information Type number Package 74LVC16374ADL Temperature range Name Description Version −40 °C to +125 °C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 −40 °C to +125 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 −40 °C to +125 °C HXQFN60U plastic thermal enhanced extremely thin quad flat SOT1134-1 package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm 74LVCH16374ADL 74LVC16374ADGG 74LVCH16374ADGG 74LVC16374ABQ 74LVCH16374ABQ 4. Functional diagram 1 24 1OE 2OE 1 1OE 48 1CP 24 2OE 25 2CP 47 1D0 1Q0 2 46 1D1 1Q1 3 1D0 44 1D2 1Q2 5 1D1 43 1D3 1Q3 6 1D2 41 1D4 1Q4 8 1D3 40 1D5 1Q5 9 1D4 38 1D6 1Q6 11 1D5 37 1D7 1Q7 12 1D6 36 2D0 2Q0 13 1D7 35 2D1 2Q1 14 33 2D2 2Q2 16 32 2D3 2Q3 17 30 2D4 2Q4 19 29 27 26 2Q5 2D5 2Q6 2D6 2Q7 2D7 1CP 2D0 2D1 2D2 2D3 20 2D4 22 2D5 23 2D6 2CP 2D7 48 25 Logic symbol 74LVC_LVCH16374A_7 Product data sheet C3 EN2 C4 3D 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 4D 2 13 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 001aaa254 001aaa253 Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 1. 47 EN1 Pin numbers are shown for SSOP48 and TSSOP48 packages only. Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 2 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 1D0 D 1Q0 Q 2D0 D CP 2Q0 Q CP FF1 FF2 1CP 2CP 1OE 2OE to 7 other channels to 7 other channels 001aaa255 Fig 3. Logic diagram VCC data input to internal circuit mna705 Fig 4. Bus hold circuit 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 3 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 5. Pinning information 5.1 Pinning 74LVC16374A 74LVCH16374A 1OE 1 48 1CP 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2CP 001aaa231 Fig 5. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 4 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state terminal 1 index area 74LVC16374A 74LVCH16374A D1 A32 A1 D5 A31 A30 B20 A29 B19 A28 B18 A27 D4 D8 A26 A2 A25 B1 B17 B2 B16 A3 A24 A4 A23 B15 B3 A5 A22 B4 B14 B5 B13 B6 B12 A6 A21 A7 A20 A8 A19 B7 B11 A9 A18 GND(1) A10 D6 D2 A11 A12 B10 B9 B8 A13 A14 A15 D7 A17 A16 D3 001aaj618 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration SOT1134-1 (HXQFN60U) 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 5 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description SOT370-1 and SOT362-1 SOT1134-1 1OE, 2OE 1, 24 A30, A13 output enable input (active LOW) GND 4, 10, 15, 21, 28, 34, 39, 45 A32, A3, A8, A11, A16, A19, A24, A27 ground (0 V) VCC 7, 18, 31, 42 A1, A10, A17, A26 supply voltage 1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12 B20, A31, D5, D1, A2, B2, B3, A5 data output 2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 A6, B5, B6, A9, D2, D6, A12, B8 data output 1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 B18, A28, D8, D4, A25, B16, B15, A22 data input 2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 A21, B13, B12, A18, D3, D7, A15, B10 data input 1CP, 2CP A29, A14 48, 25 clock input 6. Functional description Table 3. Function selection[1] Operating mode Load and read register Load register and disable outputs [1] Input Internal flip-flop Output nQ0 to nQ7 nOE nCP nDn L ↑ l L L L ↑ h H H H ↑ l L Z H ↑ h H Z H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition; ↑ = LOW-to-HIGH transition; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current Conditions VI < 0 V [1] Min Max Unit −0.5 +6.5 V −50 - mA −0.5 +6.5 V VI input voltage IOK output clamping current VO > VCC or VO < 0 V - ±50 mA VO output voltage output HIGH-or LOW-state [2] −0.5 VCC + 0.5 V output 3-state [2] −0.5 +6.5 V - ±50 mA IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 6 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Ptot total power dissipation Tamb = −40 °C to +125 °C Min Max Unit (T)SSOP48 package [3] - 500 mW HXQFN60U package [4] - 1000 mW [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. [4] Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V active mode 0 - VCC V power-down mode; VCC = 0 V 0 - 5.5 V −40 - +125 °C VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V functional Tamb ambient temperature Δt/ΔV input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage −40 °C to +85 °C Conditions Min Max Min Max VCC - - VCC - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V - - GND - GND V - - 0.8 - 0.8 V - VCC − 0.3 - V LOW-level input VCC = 1.2 V voltage VCC = 2.7 V to 3.6 V VOH HIGH-level output voltage Product data sheet Unit VCC = 1.2 V VIL 74LVC_LVCH16374A_7 −40 °C to +125 °C Typ[1] VI = VIH or VIL IO = −100 μA; VCC = 2.7 V to 3.6 V VCC − 0.2 IO = −12 mA; VCC = 2.7 V VCC − 0.5 - - VCC − 0.65 - V IO = −18 mA; VCC = 3.0 V VCC − 0.6 - - VCC − 0.75 - V IO = −24 mA; VCC = 3.0 V VCC − 0.8 - - VCC − 1.0 - V All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 7 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max IO = 100 μA; VCC = 2.7 V to 3.6 V - - 0.2 - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V VI = VIH or VIL IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - ±0.1 ±5 - ±20 μA - ±0.1 ±5 - ±20 μA II input leakage current VCC = 3.6 V; VI = 5.5 V or GND [2] IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND; [2] IOFF power-off VCC = 0 V; VI or VO = 5.5 V leakage current - ±0.1 ±10 - ±20 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 20 - 80 μA ΔICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A - 5 500 - 5000 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF IBHL bus hold LOW current VCC = 3.0 V; VI = 0.8 V [4][5] 75 - - 60 - μA IBHH bus hold HIGH current VCC = 3.0 V; VI = 2.0 V [4][5] −75 - - −60 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V [4][6] 500 - - 500 - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V [4][6] −500 - - −500 - μA [3] [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. [2] The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. [3] For non bus hold parts only (74LVC16374A). [4] Valid for data inputs only. Control inputs do not have a bus hold circuit. [5] The specified sustaining current at the data input holds the input below the specified VI level. [6] The specified overdrive current at the data input forces the data input to the opposite logic input state. 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 8 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10. Symbol Parameter propagation delay tpd −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.2 V - 14 - - - ns VCC = 2.7 V 1.5 - 6.0 1.5 7.5 ns 1.5 3.4 5.4 1.5 7.0 ns VCC = 1.2 V - 20 - - - ns VCC = 2.7 V 1.5 - 6.0 1.5 7.5 ns 1.0 3.5 5.2 1.0 6.5 ns VCC = 1.2 V - 12 - - - ns VCC = 2.7 V 1.5 - 5.1 1.5 6.5 ns VCC = 3.0 V to 3.6 V 1.5 3.9 4.9 1.5 6.5 ns VCC = 1.2 V - - - - - ns VCC = 2.7 V 3.0 - - 3.0 - ns VCC = 3.0 V to 3.6 V 3.0 1.5 - 3.0 - ns VCC = 1.2 V - - - - - ns VCC = 2.7 V 1.9 - - 1.9 - ns VCC = 3.0 V to 3.6 V 1.9 0.3 - 1.9 - ns VCC = 1.2 V - - - - - ns VCC = 2.7 V 1.1 - - 1.1 - ns VCC = 3.0 V to 3.6 V 1.5 −0.3 - 1.5 - ns 80 - - 80 - MHz 100 150 - 100 - MHz - - 1.0 - 1.5 nCP to nQn; see Figure 7 [2] VCC = 3.0 V to 3.6 V enable time ten nOE to nQn; see Figure 9 [2] VCC = 3.0 V to 3.6 V disable time tdis pulse width tW set-up time tsu hold time th maximum frequency fmax nOE to nQn; see Figure 7 [2] nCP HIGH; see Figure 7 nDn to nCP; see Figure 8 nDn to nCP; see Figure 8 see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V tsk(o) output skew time −40 °C to +125 °C Unit Typ[1] VCC = 3.0 V to 3.6 V [3] [1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. ns ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 9 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 11. Waveforms 1/fmax VI nCP input VM VM GND tW t PHL t PLH VOH VM nQn output 001aaa256 VOL Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 7. Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency VI VM nCP input GND t su t su th th VI VM nDn input GND VOH VM nQn output VOL 001aaa257 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable performance. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 8. Data set-up and hold times for the nDn input to the nCP input 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 10 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs enabled outputs disabled mna362 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 9. Table 8. 3-state enable and disable times Measurement points Supply voltage Input VCC VI VM VM VX VY 1.2 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.1 V VOH − 0.1 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74LVC_LVCH16374A_7 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 11 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2.5 ns 50 pF 500 Ω[1] open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND [1] Load VEXT The circuit performs better when RL = 1 kΩ. 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 12 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Fig 11. Package outline SOT370-1 (SSOP48) 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 13 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 12. Package outline SOT362-1 (TSSOP48) 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 14 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm B D SOT1134-1 A terminal 1 index area E A A1 detail X e2 e1 1/2 e e C A B C v w L1 D2 D6 A11 eR y D7 B10 A10 L y1 C D3 A16 B8 C C A B C v w b A17 e B11 B7 e3 Eh e4 1/2 e B1 B17 A1 terminal 1 index area A26 D5 D1 B20 B18 A32 D8 A27 X D4 Dh k 0 2.5 Dimensions Unit mm 5 mm scale A A1 b max 0.50 0.05 0.35 nom 0.48 0.02 0.30 min 0.46 0.00 0.25 D Dh E Eh e e1 e2 e3 e4 eR 4.1 4.0 3.9 1.90 1.85 1.80 6.1 6.0 5.9 3.90 3.85 3.80 0.5 1 2.5 3 4.5 0.5 k L 0.25 0.35 0.20 0.30 0.15 0.25 L1 0.125 0.075 0.025 v w y 0.07 0.05 0.08 y1 0.1 sot1134-1_po References Outline version IEC JEDEC JEITA SOT1134-1 --- --- --- European projection Issue date 08-12-17 09-01-22 Fig 13. Package outline SOT1134-1 (HXQFN60U) 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 15 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC_LVCH16374A_7 20100323 Product data sheet - 74LVC_LVCH16374A_6 • Modifications: 74LVC_LVCH16374A_6 74LVC16374ABQ and 74LVCH16374ABQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. 20090212 Modifications: Product data sheet - 74LVC_LVCH16374A_5 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Added: type numbers 74LVC16374ABQ and 74LVCH16374ABQ (HUQFN60U package). 74LVC_LVCH16374A_5 20031212 Product specification - 74LVC_H16374A_4 74LVC_H16374A_4 19980317 Product specification - 74LVC16374A_ 74LVCH16374A_3 74LVC16374A_ 74LVCH16374A_3 19980317 Product specification - 74LVC16374A_2 74LVC16374A_2 19970822 Product specification - 74LVC16374A_1 74LVC16374A_1 - - - - 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 16 of 19 74LVC16374A; 74LVCH16374A NXP Semiconductors 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVC_LVCH16374A_7 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 17 of 19 NXP Semiconductors 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC_LVCH16374A_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 07 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 18 of 19 NXP Semiconductors 74LVC16374A; 74LVCH16374A 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 March 2010 Document identifier: 74LVC_LVCH16374A_7