74LVTH322245

74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state Rev. 01 — 24 January 2007 Product data sheet 1. General description The 74LVTH322245 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. The 74LVTH322245 is designed with 30 Ω series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers/transmitters. The 74LVTH322245 is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features four output enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction control. Pin nOE controls the outputs so that the buses are effectively isolated. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features I I I I I I I I I I I 32-bit bidirectional bus interface 3-state buffers Output capability: +12 mA and −12 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Outputs include series resistance of 30 Ω making external resistors unnecessary Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection: N JESD78 Class II level A exceeds 500 mA I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVTH322245EC −40 °C to +125 °C Description Version SOT536-1 LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 × 5.5 × 1.05 mm Type number NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state 4. Functional diagram A3 1DIR H3 1OE A4 E5 1B0 A2 E6 1B1 A1 F5 1B2 B2 F6 1B3 B1 G5 1B4 C2 G6 1B5 C1 H6 1B6 D2 H5 1B7 D1 2DIR 2OE 2A0 2B0 2A1 2B1 2A2 2B2 2A3 2B3 2A4 2B4 2A5 2B5 2A6 2B6 2A7 2B7 H2 H1 G1 G2 F1 F2 E1 E2 H4 A5 1A0 A6 1A1 B5 1A2 B6 1A3 C5 1A4 C6 1A5 D5 1A6 D6 1A7 J3 3DIR 3OE T3 J4 N5 3B0 J2 N6 3B1 J1 P5 3B2 K2 P6 3B3 K1 R5 3B4 L2 R6 3B5 L1 T6 3B6 M2 T5 3B7 M1 4DIR 4OE 4A0 4B0 4A1 4B1 4A2 4B2 4A3 4B3 4A4 4B4 4A5 4B5 4A6 4B6 4A7 4B7 mna476 T4 J5 3A0 N2 J6 3A1 N1 K5 3A2 P2 K6 3A3 P1 L5 3A4 R2 L6 3A5 R1 M5 3A6 T1 M6 3A7 T2 Fig 1. Logic symbol 74LVTH322245_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 24 January 2007 2 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state VCC 27 Ω output 27 Ω VCC data input to internal circuit 001aah684 mna473 Fig 2. Schematic of each output Fig 3. Bus hold circuit 5. Pinning information 5.1 Pinning mna475 6 5 4 3 2 1 1A1 1A0 1A3 1A2 1A5 1A4 1A7 1A6 2A1 2A0 2A3 2A2 2A5 2A4 2A6 2A7 3A1 3A0 3A3 3A2 3A5 3A4 3A7 3A6 4A1 4A0 4A3 4A2 4A5 4A4 4A6 4A7 1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 1DIR GND VCC GND GND VCC GND 2DIR 3DIR GND VCC GND GND VCC GND 4DIR 1B0 1B1 A 1B2 1B3 B 1B4 1B5 C 1B6 1B7 D 2B0 2B1 E 2B2 2B3 F 2B4 2B5 G 2B7 2B6 H 3B0 3B1 J 3B2 3B3 K 3B4 3B5 L 3B6 3B7 M 4B0 4B1 N 4B2 4B3 P 4B4 4B5 R 4B7 4B6 T Fig 4. Pin configuration 5.2 Pin description Table 2. Symbol nDIR (n = 1 to 4) nOE (n = 1 to 4) 1A[0:7] 1B[0:7] 2A[0:7] 2B[0:7] 3A[0:7] 3B[0:7] 74LVTH322245_1 Pin description Ball A3, H3, J3, T3 A4, H4, J4, T4 A5, A6, B5, B6, C5, C6, D5, D6 A2, A1, B2, B1, C2, C1, D2, D1 E5, E6, F5, F6, G5, G6, H6, H5 E2, E1, F2, F1, G2, G1, H1, H2 J5, J6, K5, K6, L5, L6, M5, M6 J2, J1, K2, K1, L2, L1, M2, M1 Rev. 01 — 24 January 2007 Description direction control output enable input (active LOW) input or output input or output input or output input or output input or output input or output © NXP B.V. 2008. All rights reserved. Product data sheet 3 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state Table 2. Symbol 4A[0:7] 4B[0:7] GND VCC Pin description …continued Ball N5, N6, P5, P6, R5, R6, T6, T5 N2, N1, P2, P1, R2, R1, T1, T2 Description input or output input or output B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, ground (0 V) M3, M4, N3, N4, R3, R4 C3, C4, F3, F4, L3, L4, P3, P4 supply voltage 6. Functional description Table 3. Input nOE L L H [1] Function selection[1] Input/output nDIR L H X nAn nAn = nBn inputs Z nBn inputs nBn = nAn Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)[1][2] Symbol Parameter VCC VI VO IIK IOK IO Tstg Tj [1] Conditions [3] Min −0.5 −0.5 −0.5 −50 −50 −64 −65 - Max +4.6 +7.0 +7.0 128 +150 150 Unit V V V mA mA mA mA °C °C supply voltage input voltage output voltage input clamping current output clamping current output current storage temperature junction temperature output in OFF or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state [3] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond indicated under Section 8 “Recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] [3] 74LVTH322245_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 24 January 2007 4 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state 8. Recommended operating conditions Table 5. Symbol VCC VI IOH IOL Tamb ∆t/∆V Ptot [1] Recommended operating conditions Parameter supply voltage input voltage HIGH-level output current LOW-level output current ambient temperature input transition rise and fall rate total power dissipation in free air outputs enabled [1] Conditions Min 2.7 0 −12 −40 - Typ - Max 3.6 5.5 12 +85 10 1000 Unit V V mA mA °C ns/V mW Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIK VIH VIL VOH VOL II °C[1] VCC = 2.7 V; IIK = −18 mA −1.2 2.0 VCC = 3.0 V; IOH = −12 mA VCC = 3.0 V; IOL = 12 mA control pins VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V input/output data pins; VCC = 3.6 V VI = VCC VI = 0 V IOFF ILO IO(pu/pd) IBHL IBHH IBHLO IBHHO ICC power-off leakage current output leakage current power-up/power-down output current bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current supply current VCC = 0 V; VI or VO = 0 V to 4.5 V output HIGH; VO = 5.5 V; VCC = 3.0 V VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V VCC = 0 V to 3.6 V; VI = 3.6 V VCC = 0 V to 3.6 V; VI = 3.6 V VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled 74LVTH322245_1 Conditions Min Typ −0.85 2.5 0.3 0.1 0.1 0.5 −0.1 0.1 75 40 135 −135 - Max 0.8 0.8 ±1 10 10 ±100 125 ±100 −75 −500 Unit V V V V V µA µA µA µA µA µA µA µA µA µA µA input clamping voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current 2.0 [2] −5 [4] 75 - [3] 500 - [3] [5] 0.14 8.4 0.14 0.24 12 0.24 mA mA mA - © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 24 January 2007 5 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ∆ICC additional supply current Conditions per input pin; VCC = 3 V to 3.6 V; one input at VCC − 0.6 V; other inputs at VCC or GND control pins; VO = 0 V or 3.0 V input/output data pins; outputs disabled; VCC = 3.6 V; IO = 0 A; VI = GND or VCC [6] Min - Typ 0.1 Max 0.2 Unit mA CI CI/O input capacitance input/output capacitance - 3 9 - pF pF [1] [2] [3] [4] [5] [6] All typical values are at VCC = 3.3 V and Tamb = 25 °C unless otherwise specified. Unused pins at VCC or GND. This is the bus-hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for load circuit see Figure 7. Symbol tPLH Parameter LOW to HIGH propagation delay Conditions nAn to nBn or nBn to nAn; see Figure 5 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHL HIGH to LOW propagation delay nAn to nBn or nBn to nAn; see Figure 5 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZH OFF-state to HIGH propagation delay nOE to nAn or nBn; see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPZL OFF-state to LOW propagation delay nOE to nAn or nBn; see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPHZ HIGH to OFF-state propagation delay nOE to nAn or nBn; see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V tPLZ LOW to OFF-state propagation delay nOE to nAn or nBn; see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V [1] All typical values are at VCC = 3.3 V and Tamb = 25 °C. © NXP B.V. 2008. All rights reserved. Min Typ[1] Max Unit Tamb = −40 °C to +85 °C 1.0 2.5 3.9 3.5 ns ns 1.0 1.5 1.5 1.5 1.5 2.2 3.5 3.2 3.5 4.3 3.9 3.5 6.4 5.3 5.0 4.4 5.1 4.8 5.9 6.7 ns ns ns ns ns ns ns ns ns ns 74LVTH322245_1 Product data sheet Rev. 01 — 24 January 2007 6 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state 11. Waveforms VI nAn, nBn input GND t PHL VOH nBn, nAn output VOL VM mna477 VM t PLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Input to output propagation delays VI nOE input GND tPLZ 3.0 V output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aah683 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. enable and disable times Table 8. VCC 2.7 V to 3.6 V Measurement points Input VM 1.5 V Output VM 1.5 V VX VOL + 0.3 V VY VOH − 0.3 V Supply voltage 74LVTH322245_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 24 January 2007 7 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Load circuitry for switching times Table 9. Input VI 2.7 V fi ≤ 10 MHz tW 500 ns tr, tf ≤ 2.5 ns Test data Load RL 500 Ω CL 50 pF VEXT tPHZ, tPZH GND tPLZ, tPZL 6V tPLH, tPHL open 74LVTH322245_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 24 January 2007 8 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 D B A ball A1 index area A E A2 A1 detail X e1 1/2 e C ∅v M C A B e T R P N M L K J H G F E D C B A ball A1 index area y1 C y b ∅w M C e e2 1/2 e 123456 X 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 13.6 13.4 e 0.8 e1 4 e2 12 v 0.15 w 0.1 y 0.1 y1 0.2 OUTLINE VERSION SOT536-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 Fig 8. Package outline SOT536-1 (LFBGA96) 74LVTH322245_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 24 January 2007 9 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state 13. Abbreviations Table 10. Acronym BiCMOS DUT ESD HBM MM TTL Abbreviations Description Bipolar Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20080124 Data sheet status Product data sheet Change notice Supersedes Document ID 74LVTH322245_1 74LVTH322245_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 24 January 2007 10 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVTH322245_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 24 January 2007 11 of 12 NXP Semiconductors 74LVTH322245 3.3 V 32-bit bus transceiver with 30 Ω termination resistors; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 January 2007 Document identifier: 74LVTH322245_1