Freescale Semiconductor
Technical Data
Document Number: A2T09VD300N
Rev. 0, 8/2015
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 79 W RF power LDMOS transistor is designed for cellular base station
applications covering the frequency range of 716 to 960 MHz.
A2T09VD300NR1
900 MHz
Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQ(A+B) = 1200 mA, Pout = 79 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
920 MHz
21.5
34.4
7.1
–34.6
–13
940 MHz
21.6
34.7
7.0
–33.5
–14
960 MHz
21.5
34.7
6.8
–33.6
–14
716–960 MHz, 79 W AVG., 48 V
AIRFAST RF POWER LDMOS
TRANSISTOR
TO--270WB--6A
PLASTIC
800 MHz
Typical Single--Carrier W--CDMA Performance: VDD = 48 Vdc,
IDQ(A+B) = 1200 mA, Pout = 79 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
IRL
(dB)
790 MHz
21.4
35.3
7.2
–35.1
–18
806 MHz
21.6
35.7
7.1
–34.5
–19
GND 2
821 MHz
21.6
36.0
6.9
–34.3
–16
RFinB/VGSB 3
RFinA/VGSA 1
6 RFoutA/VDSA
5 GND
4 RFoutB/VDSB
Features
Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
Designed for Digital Predistortion Error Correction Systems
Optimized for Doherty Applications
Freescale Semiconductor, Inc., 2015. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
(Top View)
Note: Exposed backside of the package is
the source terminal for the transistors.
Figure 1. Pin Connections
A2T09VD300NR1
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain--Source Voltage
Rating
VDSS
–0.5, +105
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
55, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +150
C
TJ
–40 to +225
C
Symbol
Value (2,3)
Unit
RJC
0.66
C/W
Operating Junction Temperature
Range (1,2)
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 98C, 79 W CW, 48 Vdc, IDQ(A+B) = 1200 mA, 940 MHz
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
A
Charge Device Model (per JESD22--C101)
IV
Table 4. Moisture Sensitivity Level
Test Methodology
Per JESD22--A113, IPC/JEDEC J--STD--020
Rating
Package Peak Temperature
Unit
3
260
C
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 105 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 55 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 116 Adc)
VGS(th)
1.3
1.8
2.3
Vdc
Gate Quiescent Voltage
(VDS = 48 Vdc, IDQ(A+B) = 1200 mAdc)
VGS(Q)
—
2.5
—
Vdc
Fixture Gate Quiescent Voltage (5)
(VDD = 48 Vdc, IDQ(A+B) = 1200 mAdc, Measured in Functional Test)
VGG(Q)
4.0
5.0
6.0
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 1.16 Adc)
VDS(on)
0.1
0.21
0.5
Vdc
Characteristic
Off Characteristics (4)
On Characteristics (4)
1.
2.
3.
4.
5.
Continuous use at maximum temperature will affect MTTF.
MTTF calculator available at http://www.freescale.com/rf/calculators.
Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
Each side of device measured separately.
VGG = 2 VGS(Q). Parameter measured on Freescale Test Fixture, due to resistor divider network on the board. Refer to Test Fixture Layout.
(continued)
A2T09VD300NR1
2
RF Device Data
Freescale Semiconductor, Inc.
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1,2) (In Freescale Test Fixture, 50 ohm system) VDD = 48 Vdc, IDQ(A+B) = 1200 mA, Pout = 79 W Avg., f = 920 MHz,
Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz
Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
20.0
21.5
23.0
dB
Drain Efficiency
D
31.5
34.4
—
%
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
PAR
6.6
7.1
—
dB
ACPR
—
–34.6
–32.0
dBc
IRL
—
–13
–10
dB
Input Return Loss
Load Mismatch (In Freescale Test Fixture, 50 ohm system) IDQ(A+B) = 1200 mA, f = 940 MHz, 12 sec(on), 10% Cycle
VSWR 10:1 at 52 Vdc, 420 W Pulsed CW Output Power
(3 dB Input Overdrive from 363 W Pulsed CW Rated Power)
No Device Degradation
Typical Performance (In Freescale Test Fixture, 50 ohm system) VDD = 48 Vdc, IDQ(A+B) = 1200 mA, 920–960 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
250
—
W
Pout @ 3 dB Compression Point (3)
P3dB
—
398
—
W
—
–19
—
VBWres
—
90
—
MHz
Gain Flatness in 40 MHz Bandwidth @ Pout = 79 W Avg.
GF
—
0.5
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.012
—
dB/C
P1dB
—
0.001
—
dB/C
AM/PM
(Maximum value measured at the P3dB compression point across
the 920–960 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C)
Table 6. Ordering Information
Device
A2T09VD300NR1
Tape and Reel Information
R1 Suffix = 500 Units, 44 mm Tape Width, 13--inch Reel
Package
TO--270WB--6A
1. Part internally input matched.
2. Measurement made with device in single--ended configuration.
3. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
3
A2T09VD300N
Rev. 0
D60035
VGG
R1
C16
R2
C8
VDD
C18
R3
C5
C20
C7
C10
C2
CUT OUT AREA
C1
C9
C15
C13
C3
C4
C6
C11
C14
C12
C21
R4
C17
C19
Figure 2. A2T09VD300NR1 Test Circuit Component Layout
Table 7. A2T09VD300NR1 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1, C3, C4
3.3 pF Chip Capacitors
ATC800B3R3BT500XT
ATC
C2
2.7 pF Chip Capacitor
ATC800B2R7BT500XT
ATC
C5, C6, C7, C15, C16, C17
47 pF Chip Capacitors
ATC800B470JT500XT
ATC
C8, C9
1 F Chip Capacitors
C5750X7R2A105K230KM
TDK
C10, C11
15 pF Chip Capacitors
ATC800B150JT500XT
ATC
C12, C13
3 pF Chip Capacitors
ATC800B3R0BT500XT
ATC
C14
5.6 pF Chip Capacitor
ATC800B5R6BT500XT
ATC
C18, C19
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C20, C21
220 F, 100 V Electrolytic Capacitors
MCGPR100V227M16X26--RH
Multicomp
R1, R2
1000 , 1/4 W Chip Resistors
CRCW12061K00FKEA
Vishay
R3, R4
10 , 1/4 W Chip Resistors
CRCW120610R0JNEA
Vishay
PCB
Rogers RO4350B, 0.020, r = 3.66
D60035
MTL
A2T09VD300NR1
4
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS
30
D
21
Gps
PARC
20
25
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
20.5
ACPR
19.5
–33
5
–34
0
–35
19
–36
IRL
18.5
18
820
840
860
–37
880
900
920
f, FREQUENCY (MHz)
940
–38
980
960
–5
–10
–15
–20
–2.4
–2.6
–2.8
–3
–3.2
PARC (dB)
21.5
35
IRL, INPUT RETURN LOSS (dB)
40
ACPR (dBc)
Gps, POWER GAIN (dB)
22.5 VDD = 48 Vdc, Pout = 79 W (Avg.), IDQ(A+B) = 1200 mA
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
22
D, DRAIN
EFFICIENCY (%)
45
23
–3.4
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 79 Watts Avg.
–10
VDD = 48 Vdc, Pout = 158 W (PEP)
IDQ(A+B) = 1200 mA, Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 940 MHz
–20
IM3--U
–30
IM3--L
IM5--U
–40
IM5--L
IM7--U
–50
–60
IM7--L
1
200
100
10
TWO--TONE SPACING (MHz)
23
0
22.5
22
21.5
21
20.5
VDD = 48 Vdc, IDQ(A+B) = 1200 mA, f = 940 MHz
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
–1
–3
ACPR
–5
20
Gps
–3 dB = 79.1 W
40
40
–30
30
–2 dB = 59.7 W
–4
–25
35
D
–1 dB = 41.9 W
–2
45
60
80
Pout, OUTPUT POWER (WATTS)
25
–35
–40
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
23.5
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
–45
20
–50
15
120
–55
PARC
100
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
Gps, POWER GAIN (dB)
24
D
22
20 920 MHz
960 MHz
940 MHz
18
16
14
Gps
940 MHz
960 MHz
920 MHz
ACPR
10
Pout, OUTPUT POWER (WATTS) AVG.
0
50
–10
40
30
20
10
920 MHz
960 MHz 940 MHz
1
60
100
0
200
–20
–30
–40
ACPR (dBc)
VDD = 48 Vdc, IDQ(A+B) = 1200 mA, Single--Carrier W--CDMA
3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
D, DRAIN EFFICIENCY (%)
26
–50
–60
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
26
5
VDD = 48 Vdc
Pin = 0 dBm
IDQ(A+B) = 1200 mA
24
0
–5
Gain
–10
20
18
IRL (dB)
GAIN (dB)
22
–15
IRL
16
14
600
–20
700
800
900
1000 1100
f, FREQUENCY (MHz)
1200
1300
–25
1400
Figure 7. Broadband Frequency Response
A2T09VD300NR1
6
RF Device Data
Freescale Semiconductor, Inc.
Table 8. Single Side Load Pull Performance — Maximum Power Tuning
VDD = 48 Vdc, IDQ = 582 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
920
2.52 – j4.77
2.79 + j5.52
940
2.87 – j5.36
2.92 + j6.17
960
3.52 – j5.36
2.87 + j6.65
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2.53 + j0.15
20.3
53.1
202
60.0
–13
2.46 – j0.13
20.3
53.1
202
60.3
–12
2.24 – j0.21
20.3
53.0
200
60.3
–11
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
2.52 – j4.77
2.58 + j5.79
2.76 – j0.03
18.1
53.8
239
61.3
–18
940
2.87 – j5.36
2.68 + j6.48
2.68 – j0.25
18.2
53.8
238
61.5
–17
960
3.52 – j5.36
2.65 + j7.01
2.60 – j0.48
18.1
53.7
236
60.8
–16
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 9. Single Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 48 Vdc, IDQ = 582 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
2.52 – j4.77
2.43 + j5.57
1.96 + j2.30
22.7
50.9
124
70.1
–18
940
2.87 – j5.36
2.56 + j6.19
1.89 + j2.08
22.8
50.8
121
70.8
–18
960
3.52 – j5.36
2.55 + j6.68
1.83 + j1.71
22.4
51.0
125
70.2
–16
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2.31 + j1.99
20.3
52.3
170
71.6
–25
2.45 + j6.49
2.15 + j1.71
20.3
52.2
167
71.5
–25
2.42 + j7.01
2.02 + j1.46
20.2
52.2
165
71.2
–24
f
(MHz)
Zsource
()
Zin
()
920
2.52 – j4.77
2.37 + j5.85
940
2.87 – j5.36
960
3.52 – j5.36
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
7
P1dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
4
4
50.5
E
2
50
51
51.5
52
1
52.5
0
P
1.5
1
2
2.5
4
3
3.5
REAL ()
4.5
68
64
66
62
0
–2
5
60
P
58
56
54
1.5
1
2
2.5
3
3.5
REAL ()
4
4
23
23.5
22
E
2
21.5
21
1
20.5
0
P
20
–1
1.5
2
2.5
–10
3
3.5
REAL ()
4
–22
2
–20
1
–14
E
–12
–18
–16
0
P
–1
19.5
1
5
3
22.5
IMAGINARY ()
3
4.5
Figure 9. P1dB Load Pull Efficiency Contours (%)
4
IMAGINARY ()
70
1
–1
Figure 8. P1dB Load Pull Output Power Contours (dBm)
–2
54
E
2
53
–1
–2
56
3
IMAGINARY ()
IMAGINARY ()
49.5
49
3
4.5
5
Figure 10. P1dB Load Pull Gain Contours (dB)
NOTE:
–2
1
1.5
2
2.5
3
3.5
REAL ()
4
4.5
5
Figure 11. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD300NR1
8
RF Device Data
Freescale Semiconductor, Inc.
P3dB – TYPICAL LOAD PULL CONTOURS — 940 MHz
4
4
50
50.5
51
51.5
58
52
2
52.5
E
1
53
0
P
–1
–2
1
52
1.5
2
2.5
3
3.5
REAL ()
4
4.5
66
0
64
60
62
P
1
1.5
3
20.5
21
2
19.5
20
E
IMAGINARY ()
IMAGINARY ()
68
58
56
2
2.5
4
3
3.5
REAL ()
4.5
5
4
21.5
19
1
18.5
0
P
18
–1
1.5
2
2.5
3
3.5
REAL ()
4
4.5
5
Figure 14. P3dB Load Pull Gain Contours (dB)
NOTE:
–26
–22
–28
–24
2
–20
–18
–14
–16
E
1
0
P
–1
17.5
1
70
Figure 13. P3dB Load Pull Efficiency Contours (%)
3
–2
E
1
–2
5
Figure 12. P3dB Load Pull Output Power Contours (dBm)
4
2
–1
53.5
51.5
56
3
IMAGINARY ()
IMAGINARY ()
3
–2
1
1.5
2
2.5
3
3.5
REAL ()
4
4.5
5
Figure 15. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
9
A2T09VD300N
Rev. 0
D60035
VGG
R1
C16
R2
C8
VDD
C18
R3
C5
C20
C7
C3 C22
C4 C23
C2
C9
C6
C13
CUT OUT AREA
C1
C15
C24
C10
C11
C14
C12
C21
R4
C17
C19
Figure 16. A2T09VD300NR1 Test Circuit Component Layout — 790–821 MHz
Table 10. A2T09VD300NR1 Test Circuit Component Designations and Values — 790–821 MHz
Part
Description
Part Number
Manufacturer
C1, C3, C4, C22, C23
3.3 pF Chip Capacitors
ATC800B3R3BT500XT
ATC
C2
3.9 pF Chip Capacitor
ATC800B3R9BT500XT
ATC
C5, C6, C7, C15, C16, C17
47 pF Chip Capacitors
ATC800B470JT500XT
ATC
C8, C9
1 F Chip Capacitors
C5750X7R2A105K230KM
TDK
C10, C11
18 pF Chip Capacitors
ATC800B180JT500XT
ATC
C12, C13
3.6 pF Chip Capacitors
ATC800B3R6BT500XT
ATC
C14
6.8 pF Chip Capacitor
ATC800B6R8BT500XT
ATC
C18, C19
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C20, C21
220 F, 100 V Electrolytic Capacitors
MCGPR100V227M16X26--RH
Multicomp
C24
0.5 pF Chip Capacitor
ATC800B0R5BT500XT
ATC
R1, R2
1000 , 1/4 W Chip Resistors
CRCW12061K00FKEA
Vishay
R3, R4
10 , 1/4 W Chip Resistors
CRCW120610R0JNEA
Vishay
PCB
Rogers RO4350B, 0.020, r = 3.66
D60035
MTL
A2T09VD300NR1
10
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS — 790–821 MHz
35
D
23
22
30
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
Gps
25
21
20
PARC
19
800
–4
–36
IRL
780
–30
–34
17
16
760
0
–32
ACPR
18
–28
820
840 860 880 900
f, FREQUENCY (MHz)
–12
–16
–20
–38
960
940
920
–8
–2
–2.5
–3
–3.5
–4
PARC (dB)
40
IRL, INPUT RETURN LOSS (dB)
24
D, DRAIN
EFFICIENCY (%)
25
Gps, POWER GAIN (dB)
45
VDD = 48 Vdc, Pout = 79 W (Avg.), IDQ(A+B) = 1200 mA
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
ACPR (dBc)
26
–4.5
Figure 17. Single--Carrier Output Peak--to--Average Ratio
Compression (PARC) Broadband Performance @ Pout = 79 Watts Avg.
Gps, POWER GAIN (dB)
24
Gps
22
790 MHz
20
806 MHz 821 MHz
D
806 MHz
14
–10
40
20
790 MHz
10
–20
–30
–40
–50
806 MHz
10
Pout, OUTPUT POWER (WATTS) AVG.
1
50
ACPR
16
821 MHz
0
30
821 MHz
790 MHz
18
60
ACPR (dBc)
VDD = 48 Vdc, IDQ(A+B) = 1200 mA, Single--Carrier W--CDMA
3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
D, DRAIN EFFICIENCY (%)
26
100
0
200
–60
Figure 18. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
GAIN (dB)
22
Gain
5
VDD = 48 Vdc
Pin = 0 dBm
0
IDQ(A+B) = 1200 mA
20
–5
18
–10
16
–15
14
IRL (dB)
24
–20
IRL
12
500
600
700
800
900
1000
f, FREQUENCY (MHz)
1100
1200
–25
1300
Figure 19. Broadband Frequency Response
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
11
Table 11. Single Side Load Pull Performance — Maximum Power Tuning
VDD = 48 Vdc, IDQ = 588 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
790
3.02 – j2.72
2.66 + j3.14
806
3.29 – j2.85
2.58 + j3.43
821
3.26 – j3.34
2.47 + j3.75
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2.84 + j1.14
19.9
53.5
223
63.7
–10
2.70 + j1.24
20.1
53.4
218
62.9
–11
2.65 + j1.27
20.3
53.3
215
63.3
–11
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
790
3.02 – j2.72
2.48 + j3.26
2.94 + j1.04
17.9
54.1
259
65.9
–14
806
3.29 – j2.85
2.42 + j3.58
2.99 + j1.01
18.0
54.1
255
64.8
–14
821
3.26 – j3.34
2.31 + j3.89
2.82 + j0.99
18.0
54.0
253
64.3
–14
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 12. Single Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 48 Vdc, IDQ = 588 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
790
3.02 – j2.72
2.12 + j3.24
2.51 + j4.27
22.9
50.6
115
76.2
–17
806
3.29 – j2.85
2.22 + j3.55
2.82 + j3.70
22.4
51.5
141
74.7
–15
821
3.26 – j3.34
2.19 + j3.86
2.83 + j3.42
22.3
51.7
148
74.1
–15
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
3.54 + j3.22
19.7
52.8
189
74.2
–18
2.14 + j3.73
3.06 + j3.78
20.3
52.1
164
74.5
–20
2.07 + j4.04
2.96 + j3.63
20.4
52.2
165
74.8
–21
f
(MHz)
Zsource
()
Zin
()
790
3.02 – j2.72
2.29 + j3.37
806
3.29 – j2.85
821
3.26 – j3.34
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T09VD300NR1
12
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL LOAD PULL CONTOURS — 806 MHz
6
6
49.5
5
50.5
4
51
51.5
E
3
52
52.5
2
53
P
1
1
1.5
2
3
2.5
3.5
4
REAL ()
4.5
5
5.5
3
72
70
68
66
64
2
–1
6
62
P
60
58
1
1.5
2
3
2.5
3.5
4
REAL ()
4.5
5
5.5
6
Figure 21. P1dB Load Pull Efficiency Contours (%)
6
6
5
23.5
4
5
22.5
23
E
22
3
IMAGINARY ()
IMAGINARY ()
E
0
Figure 20. P1dB Load Pull Output Power Contours (dBm)
21.5
21
2
20.5
P
1
19.5
0
–1
60
74
4
1
0
–1
58
5
IMAGINARY ()
IMAGINARY ()
50
1
1.5
2
2.5
3
3.5
4
REAL ()
–18
–16
4
E –14
3
–12
2
20
–10
P
1
0
4.5
5
5.5
6
Figure 22. P1dB Load Pull Gain Contours (dB)
NOTE:
–1
1
1.5
2
2.5
3
3.5
4
REAL ()
4.5
5
5.5
6
Figure 23. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
13
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 806 MHz
7
7
5
IMAGINARY ()
50.5
50
6
51
5
51.5
4
52
E
52.5
3
53
2
1
P
2
1
3
4
REAL ()
20
6
21
20.5
19
18.5
2
–1
18
P
2
3
1
2
4
REAL ()
60
62
58
3
4
REAL ()
6
5
7
–8
–20
–18
–16
–14
–12
–10
–24 –22
4
E
3
2
1
17.5
1
66
5
3
0
64
P
6
E
1
68
7
19.5
21.5
4
70
Figure 25. P3dB Load Pull Efficiency Contours (%)
IMAGINARY ()
IMAGINARY ()
5
74 72
2
–1
7
Figure 24. P3dB Load Pull Output Power Contours (dBm)
7
E
3
0
6
5
4
1
53.5
54
0
–1
IMAGINARY ()
6
P
0
5
6
7
–1
1
2
3
4
5
6
7
REAL ()
Figure 26. P3dB Load Pull Gain Contours (dB)
NOTE:
Figure 27. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T09VD300NR1
14
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
15
A2T09VD300NR1
16
RF Device Data
Freescale Semiconductor, Inc.
A2T09VD300NR1
RF Device Data
Freescale Semiconductor, Inc.
17
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
Electromigration MTTF Calculator
RF High Power Model
s2p File
Development Tools
Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
Aug. 2015
Description
Initial Release of Data Sheet
A2T09VD300NR1
18
RF Device Data
Freescale Semiconductor, Inc.
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A2T09VD300NR1
Document
Number:
RF
Device
Data A2T09VD300N
Rev. 0, 8/2015Semiconductor, Inc.
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