A71CH
Plug & Trust Secure Element
Rev. 1.2 — 27 September 2018
449312
Data sheet
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1. Introduction
The A71CH is a ready-to-use solution providing a root of trust at the IC level and proven,
chip-to-cloud security right out of the box. It is a platform capable of securely storing and
provisioning credentials, securely connecting IoT devices to cloud services and
performing cryptographic node authentication.
The A71CH solution provides basic security measures protecting the IC against many
physical and logical attacks. It can be used with various host platforms and host operating
systems to secure a broad range of applications. It is complemented by a comprehensive
product support package, offering easy design-in with plug & play host application code,
easy to use development kits, reference designs, and extensive documentation for
product evaluation.
MCU
A71CH
OpenSSL/ Mbed TLS ENGINE
IoT APPLET
I2C
i.MX/ KINETIS HOST LIBRARY
JAVA CARD OPERATING SYSTEM
A71 HARDWARE
A71CH delivery
Fig 1.
A71CH block diagram
aaa-029324
A71CH
NXP Semiconductors
Plug & Trust Secure Element
2. General description
2.1 A71CH naming conventions
The following table explains the naming conventions of the commercial product name of
the A71CH products. Every A71CH product gets assigned such a commercial name,
which includes also customer and application specific data.
The A71CH commercial names have the following format.
A71CHxagpp(p)/mvsrrff
The ‘A71CH’ is a constant, all other letters are variables, which are explained in Table 1.
Table 1.
A71CH commercial name format
Variable
Meaning
Values
Description
x
IC hardware specification 1
code
standard operational ambient temperature:
−25 °C to +85 °C
I2C interface supported
2
standard operational ambient temperature:
−40 °C to +90 °C
I2C interface supported
a
embedded operating
system code
C
Java card operating system
g
embedded application
firmware (applet) code
H
H is a fixed value = IoT security applet pre
installed
pp(p)
package type code
dd(d)= Delivery Type,
TK2= HVSON8 (4x4),
UK= WLCSP12
m
Manufacturing Site Code
T
v
Silicon Version Code
0
s
Silicon Version Subcode
B
rr
ROM Code ID
ff
FabKey ID
2.2 I2C interface
The A71CH has an I2C interface in slave mode, supporting data rates up to 400 kbit/s
operating in Fast-Mode (FM). The I2C interface is using the Smartcard I2C protocol as
defined in Ref. 3 which is based on SMBus.
2.3 Security licensing
NXP Semiconductors has obtained a patent license for SPA and DPA countermeasures
from Cryptography Research Incorporated (CRI). This license covers both hardware and
software countermeasures. It is important to customers that countermeasures within the
operation system are covered under this license agreement with CRI. Further details can
be obtained on request.
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3. Features and benefits
3.1 Key benefits
Secure, zero-touch connectivity
End-to-end security, from chip to edge to cloud
Secure credential injection for IC-level root of trust
Fast design-in with complete product support package
Easy to integrate with different MCU platforms
3.2 Security features
The A71CH security concepts includes many security measures to protect the chip.
The A71CH operates fully autonomously based on an integrated Javacard operating
system and applet. Direct memory access is possible by the fixed functionalities of the
applet only. With that, the content from the memory is fully isolated from the host system.
Attack protection by integrated design measures in the chip layout, the logic and the
functional blocks.
3.3 Cryptography features
The A71CH Secure Element provides the following functionality:
Protected Access storage, generation, insertion or deletion of 4 key pairs (ECC NIST
P-256)
Systematic enforced authentication
Secure key management
Protected Access storage, insertion or deletion of 3 public keys
Signature generation and verification (ECDSA)
Shared secret calculation for Key Agreement (ECDH or ECDH-E)
Protected Access storage and use of 2 monotonic counters (32 bits each)
Protected Access storage, insertion or deletion of symmetric secrets (8x 128 bits);
longer keys can be used by using a ConstructedSecret type
Content protected access to keys
A unique chip ID (18 bytes)
HKDF key derivation using the symmetric secrets as key, Extract & Expand or Expand
only modes
HMAC SHA256 calculation in one shot or sequential
Freezing of credentials (= OTP behavior)
Secure channel SCPO3 GP support
(Optional) trust provisioning of key pairs, public keys, symmetric secrets, etc.
Possibility to lock the A71CH module as transport lock mechanism
ECC keys and operations support the following ECC curve:
NIST P-256
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Protected key storage & provisioning of credentials
3.4 Functional features
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Dedicated MX51 security CPU
400 kbit/s I2C Fast-mode interface
−40 °C to +90 °C operational ambient temperature (A7102)
On-chip Javacard operating system
40 μA typical sleep mode current with I2C pads in tristate mode
10 μA max deep sleep mode current with I2C pads in tristate mode
High-performance Public Key Infrastructure (PKI)
EEPROM with min 500,000 cycles endurance and min 25 years retention time
HVSON8 package and small WLCSP available
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4. Applications
4.1 Use Cases and target applications
A710xCH EXAMPLE USE CASES
Secure connection to public/private clouds, edge computing platforms,
infrastructure
Secure Amazon Web Services-compliant connectivity
Secure commissioning
Device-to-device authentication
Proof of origin / anti-counterfeiting
Key storage and data protection
Secure provisioning of credentials
Ecosystem protection
A710xCH TARGET APPLICATIONS
Connected industrial devices
Sensor networks
IP cameras
Home gateways
Home appliances
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5. Ordering information
5.1 Ordering options
Table 2.
Ordering information
Type number[1]
A7101agTK2/...
Package
Name
Description
Version
HVSON-8
plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 4 × 4 × 0.85 mm
SOT909-1
WLCSP12
wafer level chip scale package, 12 bumping, 0.5 mm ball pitch
not applicable
A7102agTK2/...
A7101agUK/...
A7102agUK/...
[1]
a = A or C, g = G, C or A, according to the A71CH type classification see Section 2.1 “A71CH naming conventions”
Table 3.
A71CH type table
12NC
Type number
Product
Configuration Package
Orderable part no
9353 68
097118
A7101CHTK2/T0BC2V6
A71(01)CH
customer
programmable
HVSON8
A7101CHTK2/T0BC2VJ
9353 635
15118
A7102CHTK2/T0BC2A5
A71(02)CH
customer
programmable
HVSON8
A7102CHTK2/T0BC2AJ
9353 694
82023
A7101CHUK/T0BC2HA
A71(01)CH
customer
programmable
WLCSP
A7101CHUK/T0BC2HAZ
9353 695
02023
A7102CHUK/T0BC2VA
A71(02)CH
customer
programmable
WLCSP
A7102CHUK/T0BC2VAZ
9353 737
63118
A7101CHTK2/T0BC2BM
A71(01)CH
Provisioned & HVSON8
Programmable
‘Ready for IBM
Watson IoT’
A7101CHTK2/T0BC2BJ
9353 741
46118
A7102CHTK2/T0BC2CH
A71(02)CH
Provisioned & HVSON8
Programmable
‘Ready for IBM
Watson IoT’
A7102CHTK2/T0BC2CJ
Table 4.
A71CH development tools type table
12NC
Type number
Development kit
Description
935368997598
OM3710/A71CHARD
OM3710/A71CHARD
Arduino compatible development kit
935369302598
OM3710/A71CHPCB
OM3710/A71CHPCB
Mini PCB
Table 5 gives an overview of available A71CH product types.
Table 5.
A71CH feature table
Product type[1]
Operational ambient temperature
Interface option
A7101Cgpp(p)
−25 °C to +85 °C
I2C
A7102Cgpp(p)
−40 °C to +90 °C
[1]
g = G, C, or A; pp(p) = UA or HN1, according the A71CH type classification see Section 2.1 “A71CH naming conventions”
5.1.1 Samples and final products
Section 5.1.2, gives details of how to order samples and final products.
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5.1.2 Ordering A71CH samples
Samples can be ordered from NXP Semiconductors via nxp.com using the "Buy Direct"
button.
Note that NXP Semiconductors can provide up to 5 pieces free of charge. Larger
quantities have to be ordered separately.
5.2 Configuration
The A71CH is available in configurations as specified in Table 3. The Configuration
defines the default memory and key contents. The table below describes the default
configuration "customer programmable". Other configurations will be described in
addenda to this data sheet.
Table 6.
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A71CH type table
Credential/ State
Amount
Description
Asymmetric Key Pairs
4 x ECDSA NIST P-256 private Not set, not locked
+ public key
Asymmetric Public Keys
3 x ECDSA NIST P-256 public
keys
Not set, not locked
Config Keys
3 x AES128
Not set, cannot be locked
Symmetric Secret
8 x 128 bit key data
Not set, cannot be locked
Monotonic Counter
2 x upcounting counter with
32 bit
Counter set to 0, cannot be
locked
SCP channel
SCP03 keyset with 3 AES128
keys
Keys not set, SCP03 not active
GP Data
128 segments of 32 bytes each All bytes set to 0x00
Plain Injection Mode
Plain secrets can be inserted
Debug Mode
Debug Mode is active
TransportLock
Module can be set to
"LOCKED"
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6. Marking
Table 7.
Marking codes
Type number
Marking code
A710x..TK2/... Line A: 710* (* = ‘1’ for A7101, ‘2’ for A7102, ‘3’ for A7103)
Line B: **** (**** = 4 digit Batch code[1])
Line C: ZnD***0 (*** = 3 digit Date code[2])
Z: diffusion center, SSMC Systems on Silicon Manufactoring (SSMC), Singapore
n: assembly center
D: code to indicate conformance to RHF-2006
0: Mask version code
[1]
Batch code: 5 digits available, 2 for DBSN, 2 for ASID: mark "YY ZZ" or 4 digits available, 2 for DBSN, 2 for
ASID: mark “YYZZ”
The Assembly Sequence ID (ASID) is a 2-digit indicator that counts the number of assembly batches
(transport lots) within one diffusion batch id and one weekly date code. The week start and end dates are
defined by the assembly center algorithm. The ASID is assigned sequentially starting with 01 and ranging
through 99, then each digit ranges upper case alphabet letters in combination with numeric, then numeric in
combination with upper case alphabet letters, then upper case alphabet letters in combination with upper
case alphabet letters providing 1175 possible values within a week-code. The numeric zero ‘0’ is only
allowed within the sequence of 01 to 99. The alphabet letter ‘O’ is not allowed to avoid confusion with
numeric ‘0’.
The Diffusion Batch Sequence Number (DBSN) is a 2-digit indicator that counts the number of diffusion
batches (DBID) within one Package Type (i.e. HVSON8) and one weekly date code. The DBSN is assigned
sequentially starting with 01 and ranging through 99, then each digit ranges upper case alphabet letters in
combination with numeric, then numeric in combination with upper case alphabet letters, then upper case
alphabet letters in combination with upper case alphabet letters providing 1175 possible values within a
week-code. The numeric zero ‘0’ is only allowed within the sequence of 01 to 99. The alphabet letter ‘O’ is
not allowed to avoid confusion with numeric ‘0’.
[2]
3 digit Date code: “YWW”
“Y” is a code indicating the year in which the IC is assembled. Examples: for year 1999 is Y = 9, for year
2000 is Y = 0, for year 2001 is Y = 1. ”WW” is a code indicating the week in which the IC is assembled. It is
determined from the date the assembly transport lot is created or alternately the date die is issued from die
stores to assembly start or the date die attach (Diebond) occurs or the date encapsulation occurs.
Examples: for week 01 is WW = 01, for week 52 is WW = 52, for week 53 is WW = 53.
In the case of bumped die (WL-CSP) the code indicates the week in which the IC was bumped.
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7. Functional description
7.1 Functional diagram
i.MX 6 UL
MQTT TCP/IP
APPLICATION
key management
commands
CLOUD EMBEDDED SDK
OpenSSL ENGINE
OpenSSL
A71CH/HLSE API
HOST LIBRARY
CRYPTO
LIB API
OS (LINUX)
SCI2C
I2C DRIVER
HARDWARE
I2C
A71CH SECURE ELEMENT
IoT APPLET
JAVA CARD OPERATING SYSTEM
A71 HARDWARE
aaa-029325
Fig 3.
A71CH functional diagram - example Open SSL
The A71CH uses I2C as communication interface as described in the following section.
The A71CH commands are wrapped using the Smartcard I2 protocol (SCI2C). The
detailed documentation for the A71CH commands [ref to APDU Spec] and SCI2C
encapsulation (Ref. 3) is available in NXP docstore.”
In order to simplify the product usage a host library was created which takes care for the
A71CH commands and SCI2C protocol encapsulation. The host library for various
platforms is available for download with complete sources on the A71CH website.
7.2 Credential Storage & Memory
The I2C interface of the A71CH is supporting a Smart Card I²C (SCIIC) Protocol using an
Inter-IC (I²C) based physical interface and data link layer using Fast-mode (FM) up to 400
kBit/s, a SMBus based network layer and bus protocol as well as a mapping layer to
convey [ISO/IEC 7816-4] based communication. This protocol is specified in [Ref to
SCI²C].
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• A71CH is compliant to Ref. 3 and implements the following
SCIIC protocol options:
•
•
•
•
Usage of the optional error detection code supported
CDBMS_MAX of 255 and a CDBSM_MAX of 252
Default Frame Waiting Time is 320 ms
Protocol binding selection is not supported (not needed as only 7816-4 APDU
mapping is supported)
• The I2C address is 90h (8-bit address) equals 48h (7-bit address) and optional 92h
(8-bit address) which equals 49h (7-bit address)
7.3 I2C Interface
The A71CH has an I2C interface in slave mode, supporting data rates up to 400 kbit/s
operating in Fast-Mode (FM). The I2C interface is using the Smartcard I2C protocol as
defined in Ref. 3 which is based on SMBus. The default I2C address after power-on-reset
depends on the bootup condition as shown in Table 8.
7.4 Automatic Communication Mode detection at Power on
The IC configures its interface according to the pin state as shown in the table below. The
host system must keep the voltage levels stable at these pins for at least 500 μs after
power-on-reset.
Table 8.
I2C address
I2C address
Value at startup
7.5
IF0
IF1
I2C_SCL
I2C_SDA
Write
Read
0
x
0
0
n.a.
n.a.
1
0
1
1
0x90
0x91
1
1
1
1
0x92
0x93
Power-saving modes
The device provides two power-saving operation modes, the SLEEP mode and the DEEP
SLEEP mode. These modes are activated via pad RST_N (DEEP SLEEP mode) or by the
device.
7.5.1 SLEEP mode
The SLEEP mode has the following properties:
•
•
•
•
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all internal clocks are frozen,
CPU enters power saving mode with program execution being stopped,
CPU registers keep their contents,
RAM keeps its contents,
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The A71CH enters automatically into SLEEP mode after 312 ms of inactivity on the I²C
lines and also wakes up automatically from SLEEP mode. In SLEEP mode, all internal
clocks are stopped. The IOs hold the logical states they had at the time IDLE was
activated. During SLEEP mode security sensors HVS, LVS, LTS, HTS, Light Sensors,
Glitch Sensors and Active Shielding are disabled.
There are two ways to exit from the SLEEP mode:
• A reset signal on RST_N
• An External Interrupt edge triggered by a falling edge on I2C_SDA
7.5.2 DEEP SLEEP mode
The A71CHx provides a special sleep mode offering maximum power saving. It is reached
by pulling RST_N to a logic zero level for more than 500 μs.
While in deep sleep mode the internal power is completely switched off and only the IO
pads stay supplied. All digital pads will stay in high-Z mode.
To leave the DEEP SLEEP mode RST_N has to be released and set to a logic „1“ level.
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8. Pinning information
8.1 Pinning
8.1.1 Pinning HVSON8
terminal 1
index area
I2C_SCL
1
VSS
2
8
I2C_SDA
7
VCC
A71CH
IF0
3
6
RST_N
n.c.
4
5
IF1
aaa-029366
Transparent top view
Fig 4.
Table 9.
Pin configuration for HVSON-8 (SOT909-1)
Pin description HVSON8
Symbol
Pin
Description
I2C_SCL
1
I2C clock
VSS
2
ground
IF0
3
interface activation, apply high on startup
n.c.
4
not connected
IF1
5
I2C address selection
RST_N
6
reset input, active LOW
VCC
7
power supply voltage input
I2C_SDA
8
I2C data
The center pad of the IC is not connected, although it is recommended to connect it to
ground for thermal reasons.
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8.1.2 Pinning WLCSP
bump A1
index area
1
2
3
4
A
1
2
3
4
A
n.c.
VSS
I2C_SCL
I2C_SDA
B
n.c.
VCC
n.c.
IF1
C
n.c.
i.c.
RST_N
IF0
B
C
Transparent top view
aaa-029334
Fig 5.
Transparent top view
Pin configuration for WLCSP12
Table 10.
Fig 6.
aaa-029335
Ball mapping for WLCSP12
Pin description WLCSP
Symbol
Pin
Description
n.c.
A1
not connected
VSS
A2
ground
I2C_SCL
A3
I2C Clock
I2C_SDA
A4
I2C Data
n.c.
B1
not connected
VCC
B2
Power supply voltage input
n.c.
B3
not connected
IF1
B4
I2C address selection
n.c.
C1
not connected
i.c.
C2
internally connected; connect to ground
RST_N
C3
Reset input, active LOW
IF0
C4
interface activation, apply high on startup
The pins/balls A1, B1, C1, and B3 are not connected internally. These pins/balls can be
used for routing to connect to B2 (VCC) in order to have an easier PCB layout.
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9. Package outline
Fig 7.
Package outline SOT909-1
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Fig 8.
Package outline WLCSP12
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10. Packing information
10.1 Reel packing
The A71CH product is available on 7” tape on reel and 13” tape on reel. Details are
provided in Table 11.
Table 11.
Reel packing options
Package type
Reel type
HVSON8
7” tape on reel
Minimum packing quantity
HVSON8
13” tape on
WLCSP12
7” tape on reel
[1]
1500
reel[1]
6000
3000
For details about packing method, product orientation, tape dimensions and labeling for A71 parts in
HVSON8 package having an ordering code (12NC) ending 118 refer to Ref. 2.
11. Electrical and timing characteristics
The electrical interface characteristics of static (DC) and dynamic (AC) parameters for
pads and functions used for I2C are in accordance with the NXP I2C specification (see
Ref. 1).
12. Limiting values
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
VSS (ground = 0 V).
449312
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Symbol
Parameter
Conditions
Min
Max
Unit
VDD
supply voltage
VI
input voltage
any signal pad
-0.3
+4.6
V
-0.3
+4.6
V
II
input current
pad I2C_SDA,
I2C_SCL
-
10
mA
IO
output current
pad I2C_SDA,
I2C_SCL
-
10
mA
Ilu
latch-up current
VI < 0 V or VI > VDD
-
100
mA
Vesd_hbm
electrostatic discharge
voltage (Human Body
Model)
pads VCC, VSS,
RST_N, I2C_SDA,
I2C_SCL
[1]
± 2.0
kV
Vesd_cdm
electrostatic discharge
voltage (Charge Device
Model)
pads VCC, VSS,
RST_N, I2C_SDA,
I2C_SCL
[3]
± 500
V
Ptot
Total power dissipation
-
1
W
Tstg
Storage temperature
-55
+125
°C
[2]
[1]
MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 kΩ; Tamb = −25 °C to +85 °C.
[2]
Depending on appropriate thermal resistance of the package.
[3]
JESD22-C101, JEDEC Standard Field induced charge device model test method.
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13. Recommended operating conditions
The A71CH offers two operation modes, the so-called 1V8 mode and the 3V3 mode
targeted for battery supplied applications.
Table 13.
Recommended operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage range
3V3 mode range
CPU in free
runing mode
2.50
3.3
3.6
V
1V8 mode
1.62
1.8
1.98
V
DC input voltage on digital I/O
pads I2C_SCL, I2C_SDA
3V3 mode
0
3.6
V
1V8 mode
0
3.6
V
DC input voltage on digital
input pad RST_N
3V3 mode
0
3.6
V
1V8 mode
0
3.6
V
Operating ambient
temperature
A7101
-25
+85
°C
A7102
-40
+90
°C
VI
VI
Tamb
1.62 V
1.98 V
2.5 V
operating conditions
Fig 9.
449312
Data sheet
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3.6 V
aaa-029326
Recommended operating conditions over voltage range
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14. Characteristics
14.1 DC characteristics
Measurement conventions
Testing measurements are performed at the contact pads of the device under test. All
voltages are defined with respect to the ground contact pad VSS. All currents flowing into
the device are considered positive.
14.1.1 General and I2C I/O interface
Table 14.
Symbol
Electrical DC characteristics of I2C_SCL, I2C_SDA and RST_N
Parameter
Conditions
Min
Typ
Max
Unit
Input/Output: I2C_SCL, I2C_SDA in push-pull mode
VIH
HIGH level input voltage
0.7 VDD
VImax[1]
V
VIL
LOW level input voltage
-0.5
0.3 VDD
V
IIH
HIGH level input current in input VIHmin < VI < VIHmax
mode
± 10
μA
IIL
LOW level input current
VILmin < VI < VILmax
± 10
μA
VOH
HIGH level output voltage
IOH = −3.0 mA;
[2]
0.7 VDD
V
[2]
0.7 VDD
V
3V3 mode
IOH = −3.0 mA;
1V8 mode
VOL
LOW level output voltage
IOL = 3.0 mA
0.4
V
0.2 VDD
V
3V3 mode
IOL = 2.0 mA
1V8 mode
Input/Output: I2C_SCL, I2C_SDA in open-drain mode
VIH
HIGH level input voltage
0.7 VDD
VImax[1]
V
VIL
LOW level input voltage
-0.5
0.3 VDD
V
IIH
HIGH level input current in input VIHmin < VI < VIHmax
mode
± 10
μA
IIL
LOW level input current
VILmin < VI < VILmax
± 10
μA
VOL
LOW level output voltage
IOL = 3.0 mA
0.4
V
0.2 VDD
V
0.7 VDD
VImax[1]
V
-0.3
3V3 mode
IOL = 2.0 mA
1V8 mode
Input: RST_N
VIH1
HIGH level input voltage
VIL1
LOW level input voltage
IIH1
IIL1
[1]
0.3 VDD
V
HIGH level RST_N input current VIH1min ≤ VI ≤ VDD
[3]
± 20
μA
LOW level RST_N input current 0 V ≤ VI ≤ VIL1max;
[3]
± 20
μA
Maximum value according to Table 13 “Recommended operating conditions”
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[2]
: External pull-up resistor 20 kΩ to VDD. The worst case test condition for parameter VOH is present at minimum VDD. For class A supply
voltage conditions VDD = 4.5 V is the worst case with respect to the fix specification limit VOHmin = 3.8 V (0.844 VDD). The supply voltage
related limit “0.7 VDD“is a stricter requirement than the fix value 3.8 V at high VDD (0.7 VDD = 3.85 V at VDD = 5.5 V). So, in the VDD
range 4.5 V to 5.5 V, VOHmin is specified as “the larger value of 0.7 VDD and 3.8 V, respectively”.
[3]
The active low RST_N input internally has a resistive pull-down device to VSS. Accordingly a current is flowing into the pad voltages
above 0 V. Figure 10 shows the RST_N input characteristic.
9,
,,
,,/PD[X
9
,,+PD[X
9''
9,/PD[
,,/,PD[,
9,+PLQ
,,+,PD[,
DDD
Fig 10. Input characteristic of RST_N
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14.1.2 I2C interface at 3V3 mode operation[1]
Table 15.
Symbol
Electrical characteristics of IC supply voltage VDD; VSS = 0 V; Tamb = -40 to +90 °C
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage range
3V3 mode range
CPU in free running mode
2.50
3.3
3.6
V
IDD
no coprocessor active
CPU in free running mode
6.3
7.0
mA
EPROM programming in progress CPU in free running mode
7.3
8.0
mA
AES coprocessor active
CPU in free running mode
9.3
10.3
mA
ECC coprocessor active
CPU in free running mode
13.7
15.1
mA
supply current SLEEP mode
Tamb = 25 °C
45
150
μA
RST_N at 0V, Tamb = 25 °C
10
μA
RST_N at 0V, Tamb = 90 °C
10
μA
Supply
IDD(SLP)
IDD(DSLP) supply current deep sleep mode
[1]
All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.
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14.1.3 I2C interface at 1V8 mode operation[1]
Table 16.
Symbol
Electrical characteristics of IC supply voltage VDD; VSS = 0 V; Tamb = -40 to +90 °C
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage range
1V8 mode range
1.62
1.8
1.98
V
IDD
no coprocessor active
CPU in free running mode
2.45
mA
AES coprocessor active
CPU in free running mode
2.7
mA
ECC coprocessor active
CPU in free running mode
7.5
mA
supply current SLEEP mode
Tamb = 25 °C
40
Supply
IDD(SLP)
IDD(DSLP) supply current deep sleep mode
[1]
80
μA
RST_N at 0V, Tamb = 25 °C
10
μA
RST_N at 0V, Tamb = 90 °C
10
μA
All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.
14.2 AC characteristics
Table 17.
Non-volatile memory timing characteristics; VDD = 1.8 V ± 10% or 3 V ± 10% V; VSS = 0 V;
Tamb = -40 to 90 °C
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tEEP
EEPROM erase + program time
2.7
ms
tEEE
EEPROM erase time
1.7
ms
tEEW
EEPROM program time
1.0
ms
tEER
EEPROM data retention time
NEEC
Table 18.
Tamb = +55 °C
25
5×
EEPROM endurance
(number of programming cycles)
years
105
cycles
Electrical AC characteristics of I2C_SDA, I2C_SCL, and RST_N[1];
VDD = 1.8 V ± 10% or 3 V ± 10% V; VSS = 0 V; Tamb = -40 to 90 °C
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Input/Output: I2C_SDA, I2C_SCL in open-drain mode
trIO
tfIO
I/O Input rise time
I/O Input fall time
Input/reception mode
[4]
1
μs
Input/reception mode
[4]
1
μs
Output/transmission mode;
CL = 30 pF
[4]
0.3
μs
-
400
kHz
40
60
%
400
μs
tfOIO
I/O Output fall time
fCLK
External clock frequency in I2C tCLKW, Tamb and VDD in their
applications
spec'd limits
tCLKW
Clock pulse width i.r.t. clock
period (positive pulse duty
cycle of CLK)
[3]
Inputs: RST_N
tRW
Reset pulse width (RST_N low)
without entering deep sleep
mode
40
tRDSLP
Reset pulse width (RST_N low)
to enter deep sleep mode
500
tWKP
Wake-up time from SLEEP
mode
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fCLKmin < fCLK < fCLKmax
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449312
-
μs
8
10
μs
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Table 18.
Electrical AC characteristics of I2C_SDA, I2C_SCL, and RST_N[1];
VDD = 1.8 V ± 10% or 3 V ± 10% V; VSS = 0 V; Tamb = -40 to 90 °C
Symbol Parameter
Conditions
Min
Typ
Max
Unit
tWKPIO
level triggered ext.int.
-
8
10
μs
edge triggered ext.int.
-
8
10
μs
-
μs
100
ns
10
pF
Pad LOW time for wake-up
from SLEEP mode
tWKPRST RST_N LOW time for wake-up
from SLEEP mode
tWKWT
Time from SLEEP mode
wake/up event to I2C_SDA
valid
CPIN
Pin capacitances RST_N,
I2C_SDA, /I2C_SCL
[1]
[2]
40
50
Test frequency = 1 MHz;
Tamb = 25 °C
-
All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.
tr is defined as rise time between 20% and 80% of the signal amplitude.
tf is defined as fall time between 80% and 20% of the signal amplitude.
[3]
[4]
During AC testing the inputs RST_N, I2C_SDA, I2C_SCL are driven at 0 V to +0.3 V for a LOW input level and at VDD −0.3 V to VDD for
a HIGH input level. Clock period and signal pulse (duty cycle) timing is measured at 50% of VDD.
tr is defined as rise time between 30% and 70% of the signal amplitude.
tf is defined as fall time between 70% and 30% of the signal amplitude.
Fig 11. External clock drive and AC test timing reference points of I2C_SDA, I2C_SCL, and RST_N (see Table
note [3] and Table note [4]) in open drain mode
14.3 EMC/EMI
EMC and EMI resistance according to IEC 61967-4.
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15. Abbreviations
Table 19.
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Abbreviations
Acronym
Description
AES
Advanced Encryption Standard
CRC
Cyclic Redundancy Check
DES
Digital Encryption Standard
DPA
Differential Power Analysis
DSS
Digital Signature Standard
ECC
Elliptic Curve Cryptography
EEPROM
Electrically Erasable Programmable Read-Only Memory
I/O
Input/Output
MAC
Message Authentication Code
OS
Operating System
PKI
Public Key Infrastructure
SFI
Single Fault Injection
SHA
Secure Hash Algorithm
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16. References
449312
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[1]
I2C-bus specification and user manual, Rev. 3.0 — June-19-2007, NXP
Semiconductors
[2]
SOT909-1; HVSON8; Reel pack; Ordering code (12NC) ending 118; Packing
Information; Rev. 2 — 19 April 2013
[3]
Application note SCIIC Protocol Specification, Application note, Rev 1.x, AN12207
(document number an19501x)
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17. Revision history
Table 20.
Revision history
Document ID
Release date
Data sheet status
449312
20180927
Data sheet
Modifications:
•
•
•
•
•
•
•
•
•
Section 3.4 “Functional features”: Added WLCSP
Section 8.1.1 “Pinning HVSON8”: Added paragraph
Section 8.1.2 “Pinning WLCSP”: Added section
Figure 5 “Pin configuration for WLCSP12”: Added pin configuration
Figure 6 “Ball mapping for WLCSP12”: Updated
Table 10 “Pin description WLCSP”: Updated
Table 11 “Reel packing options”: Added WLCSP
20180801
Data sheet
20180221
Objective short data sheet
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449311
Table 3 “A71CH type table”: Updated
449310
•
Supersedes
Table 1 “A71CH commercial name format”: Added WLCSP
449311
Modifications:
Change notice
449310
Initial version
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
18.4 Licenses
ICs with DPA Countermeasures functionality
NXP ICs containing functionality
implementing countermeasures to
Differential Power Analysis and Simple
Power Analysis are produced and sold
under applicable license from
Cryptography Research, Inc.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
FabKey — is a trademark of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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20. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
A71CH commercial name format . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .6
A71CH type table . . . . . . . . . . . . . . . . . . . . . . . .6
A71CH development tools type table . . . . . . . . .6
A71CH feature table . . . . . . . . . . . . . . . . . . . . . .6
A71CH type table . . . . . . . . . . . . . . . . . . . . . . . .7
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .8
I2C address. . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin description HVSON8 . . . . . . . . . . . . . . . . .12
Pin description WLCSP . . . . . . . . . . . . . . . . . .13
Reel packing options . . . . . . . . . . . . . . . . . . . .16
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .16
Recommended operating conditions . . . . . . . .17
Electrical DC characteristics of I2C_SCL,
I2C_SDA and RST_N . . . . . . . . . . . . . . . . . . . 18
Table 15. Electrical characteristics of IC supply voltage VDD;
VSS = 0 V; Tamb = -40 to +90 °C . . . . . . . . . . . 20
Table 16. Electrical characteristics of IC supply voltage VDD;
VSS = 0 V; Tamb = -40 to +90 °C . . . . . . . . . . . 21
Table 17. Non-volatile memory timing characteristics;
VDD = 1.8 V ± 10% or 3 V ± 10% V; VSS = 0 V;
Tamb = -40 to 90 °C. . . . . . . . . . . . . . . . . . . . . . 21
Table 18. Electrical AC characteristics of I2C_SDA,
I2C_SCL, and RST_N[1];
VDD = 1.8 V ± 10% or 3 V ± 10% V; VSS = 0 V;
Tamb = -40 to 90 °C. . . . . . . . . . . . . . . . . . . . . . 21
Table 19. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 20. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25
21. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
A71CH block diagram . . . . . . . . . . . . . . . . . . . . . .1
Protected key storage & provisioning of credentials
4
A71CH functional diagram - example Open SSL. .9
Pin configuration for HVSON-8 (SOT909-1) . . . .12
Pin configuration for WLCSP12 . . . . . . . . . . . . . .13
Ball mapping for WLCSP12 . . . . . . . . . . . . . . . .13
Package outline SOT909-1 . . . . . . . . . . . . . . . . .14
Fig 8.
Fig 9.
Package outline WLCSP12. . . . . . . . . . . . . . . . . 15
Recommended operating conditions over voltage
range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Fig 10. Input characteristic of RST_N . . . . . . . . . . . . . . . 19
Fig 11. External clock drive and AC test timing reference
points of I2C_SDA, I2C_SCL, and RST_N (see
Table note [3] and Table note [4]) in open drain
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
22. Contents
1
2
2.1
2.2
2.3
3
3.1
3.2
3.3
3.4
4
4.1
5
5.1
5.1.1
5.1.2
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General description . . . . . . . . . . . . . . . . . . . . . .
A71CH naming conventions . . . . . . . . . . . . . . .
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
Security licensing . . . . . . . . . . . . . . . . . . . . . . .
Features and benefits . . . . . . . . . . . . . . . . . . . .
Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . .
Security features. . . . . . . . . . . . . . . . . . . . . . . .
Cryptography features . . . . . . . . . . . . . . . . . . .
Functional features . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Cases and target applications . . . . . . . . . .
Ordering information . . . . . . . . . . . . . . . . . . . . .
Ordering options . . . . . . . . . . . . . . . . . . . . . . . .
Samples and final products . . . . . . . . . . . . . . .
Ordering A71CH samples. . . . . . . . . . . . . . . . .
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
1
2
2
2
2
3
3
3
3
4
5
5
6
6
6
7
7
6
7
7.1
7.2
7.3
7.4
7.5
7.5.1
7.5.2
8
8.1
8.1.1
8.1.2
9
10
10.1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . . 9
Functional diagram . . . . . . . . . . . . . . . . . . . . . 9
Credential Storage & Memory . . . . . . . . . . . . . 9
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Communication Mode detection at
Power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-saving modes . . . . . . . . . . . . . . . . . . 10
SLEEP mode . . . . . . . . . . . . . . . . . . . . . . . . . 10
DEEP SLEEP mode. . . . . . . . . . . . . . . . . . . . . 11
Pinning information . . . . . . . . . . . . . . . . . . . . 12
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pinning HVSON8 . . . . . . . . . . . . . . . . . . . . . . 12
Pinning WLCSP . . . . . . . . . . . . . . . . . . . . . . . 13
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 14
Packing information . . . . . . . . . . . . . . . . . . . . 16
Reel packing . . . . . . . . . . . . . . . . . . . . . . . . . 16
continued >>
449312
Data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 27 September 2018
449312
© NXP B.V. 2018. All rights reserved.
28 of 29
A71CH
NXP Semiconductors
Plug & Trust Secure Element
11
12
13
14
14.1
14.1.1
14.1.2
14.1.3
14.2
14.3
15
16
17
18
18.1
18.2
18.3
18.4
18.5
19
20
21
22
Electrical and timing characteristics . . . . . . .
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .
Recommended operating conditions. . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
DC characteristics . . . . . . . . . . . . . . . . . . . . .
General and I2C I/O interface. . . . . . . . . . . . .
I2C interface at 3V3 mode operation[1] . . . . . .
I2C interface at 1V8 mode operation[1] . . . . . .
AC characteristics. . . . . . . . . . . . . . . . . . . . . .
EMC/EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
18
18
18
20
21
21
22
23
24
25
26
26
26
26
27
27
27
28
28
28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 September 2018
449312
