ADC0808S125

ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz Rev. 03 — 24 February 2009 Product data sheet 1. General description The ADC0808S is a differential, high-speed, 8-bit Analog-to-Digital Converter (ADC) optimized for telecommunication transmission control systems and tape drive applications. It allows signal sampling frequencies up to 250 MHz. The ADC0808S clock inputs are selectable between 1.8 V Complementary Metal Oxide Semiconductor (CMOS) or Low-Voltage Differential Signals (LVDS). The data output signal levels are 1.8 V CMOS. All static digital inputs (CLKSEL, CCSSEL, CE_N, OTC, DEL0 and DEL1) are 1.8 V CMOS compatible. The ADC0808S offers the most flexible acquisition control system possible due to its programmable Complete Conversion Signal (CCS) which allows the delay time of the acquisition clock and acquisition clock frequency to be adjusted. The ADC0808S is supplied in an HTQFP48 package. 2. Features I I I I I I I I I I I I I I 8-bit resolution High-speed sampling rate up to 250 MHz Maximum analog input frequency up to 560 MHz Programmable acquisition output clock (complete conversion signal) Differential analog input Integrated voltage regulator or external control for analog input full-scale Integrated voltage regulator for input common-mode reference Selectable 1.8 V CMOS or LVDS clock input 1.8 V CMOS digital outputs 1.8 V CMOS compatible static digital inputs Binary or 2’s complement CMOS outputs Only 2 clock cycles latency Industrial temperature range from −40 °C to +85 °C HTQFP48 package 3. Applications I 2.5G and 3G cellular base infrastructure radio transceivers I Wireless access systems I Fixed telecommunications NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz I Optical networking I Wireless Local Area Network (WLAN) infrastructure I Tape drive applications 4. Ordering information Table 1. Ordering information Sampling frequency Package (MHz) Name 125 250 Description Version Type number ADC0808S125HW/C1 ADC0808S250HW/C1 HTQFP48 plastic thermal enhanced thin quad flat package; SOT545-2 48 leads; body 7 × 7 × 1 mm; exposed die pad 5. Block diagram CLKSEL 36 CLK+ CLK− 37 38 39 40 DEL0 DEL1 CLOCK DRIVER ADC0808S LATCH 17 26 CCS CCSSEL IN INN 33 32 TRACK AND HOLD 8 RESISTOR LADDERS ADC CORE LATCH 8 D0 to D7 21 OTC FSIN/ REFSEL 30 U/I LATCH 20 IR INTERNAL REFERENCE CMADC REFERENCE 29 CMADC OUTPUTS ENABLE 19 001aai267 CE_N Fig 1. Block diagram ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 2 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 6. Pinning information 6.1 Pinning 43 VCCO4(1V8) 46 OGND4 OGND1 D3 i.c. VCCO1(1V8) D4 i.c. OGND2 D5 i.c. 1 2 3 4 5 6 7 8 9 DGND 37 CLK+ 36 CLKSEL 35 i.c. 34 VCCA1(3V3) 33 IN 32 INN 31 AGND2 30 FSIN/REFSEL 29 CMADC 28 AGND1 27 NC1V8 26 CCSSEL 25 n.c. n.c. 24 001aai268 40 DEL1 OTC 21 39 DEL0 DGND1 22 ADC0808S VCCO2(1V8) 10 D6 11 i.c. 12 VCCO3(1V8) 13 D7 14 i.c. 15 OGND3 16 CCS 17 i.c. 18 CE_N 19 IR 20 Fig 2. Pin configuration 6.2 Pin description Table 2. Symbol OGND1 D3 i.c. VCCO1(1V8) D4 i.c. OGND2 D5 i.c. VCCO2(1V8) D6 i.c. VCCO3(1V8) D7 ADC0808S125_ADC0808S250_3 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Type[1] G O P O G O P O P O Description data output ground 1 data output bit 3 internally connected; leave open data output supply voltage 1 (1.8 V) data output bit 4 internally connected; leave open data output ground 2 data output bit 5 internally connected; leave open data output supply voltage 2 (1.8 V) data output bit 6 internally connected; leave open data output supply voltage 3 (1.8 V) data output bit 7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 VCCD1(1V8) 23 38 CLK− 41 D0 42 i.c. 48 i.c. 45 i.c. 47 D2 44 D1 3 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz Pin description …continued Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Type[1] G O I(CMOS) O(CMOS) I(CMOS) G P I(CMOS) I G O I G I I P I(CMOS) I I I(CMOS) I(CMOS) O P O G O G Description internally connected; leave open data output ground 3 complete conversion signal output internally connected; leave open chip enable input (active LOW) in-range output control input for 2’s complement output digital ground 1 digital supply voltage 1 (1.8 V) not connected not connected control input for CCS frequency selection not connected or connected to VCCD1(1V8) analog ground 1 regulator common-mode ADC output full-scale reference voltage input/internal or external reference selection analog ground 2 complementary analog input analog input analog supply voltage 1 (3.3 V) internally connected; leave open control input for clock input selection clock input complementary clock input complete conversion signal delay input 0 complete conversion signal delay input 1 data output bit 0 internally connected; leave open data output supply voltage 4 (1.8 V) data output bit 1 internally connected; leave open data output ground 4 data output bit 2 internally connected; leave open digital ground; exposed die pad Table 2. Symbol i.c. OGND3 CCS i.c. CE_N IR OTC DGND1 VCCD1(1V8) n.c. n.c. CCSSEL NC1V8 AGND1 CMADC FSIN/REFSEL AGND2 INN IN VCCA1(3V3) i.c. CLKSEL CLK+ CLK− DEL0 DEL1 D0 i.c. VCCO4(1V8) D1 i.c. OGND4 D2 i.c. DGND [1] See Table 3. ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 4 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz Pin type description Description input output 1.8 V CMOS level input 1.8 V CMOS level output power supply ground Table 3. Type I O I(CMOS) O(CMOS) P G 7. Functional description 7.1 CMOS/LVDS clock input The circuit has two clock inputs CLK+ and CLK−, with two modes of operation: • LVDS mode: CLK+ and CLK− inputs are at differential LVDS levels. An external resistor of between 80 Ω and 120 Ω is required; see Figure 3. maximum Vidth VO(dif) undefined state minimum Vidth LVDS DRIVER RECEIVER CLK+ CLK− Vgpd 001aah720 Fig 3. LVDS clock input • 1.8 V CMOS mode: CLK+ input is at 1.8 V CMOS level and sampling is done on the rising edge of the clock input signal. In this case pin CLK− must be grounded; see Figure 4. CMOS DRIVER CLK+ CLK− 001aai272 Fig 4. CMOS clock input ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 5 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz Clock input format selection Clock input signal Pins CLK+ and CLK− LVDS 1.8 V CMOS Table 4. Pin CLKSEL HIGH or not connected LOW 7.2 Digital output coding The digital outputs are 1.8 V CMOS compatible. The data output format can be either binary or 2’s complement. Table 5. Output coding with differential inputs Vi(p-p) = 2.0 V; Vref(fs) = 1.25 V; typical values to AGND. Code Underflow 0 1 : 127 : 254 255 Overflow Inputs (V) Vi(IN) < 0.45 0.45 : 0.95 : 1.45 > 1.45 Vi(INN) > 1.45 1.45 : 0.95 : 0.45 < 0.45 Output Pin IR LOW HIGH HIGH : HIGH : HIGH HIGH LOW Outputs D7 to D0 Binary 0000 0000 0000 0000 0000 0001 : 0111 1111 : 1111 1110 1111 1111 1111 1111 2’s complement 1000 0000 1000 0000 1000 0001 : 1111 1111 : 0111 1110 0111 1111 0111 1111 The in-range CMOS output pin IR will be HIGH during normal operation. When the ADC input reaches either positive or negative full-scale, the IR output will be LOW. Selection between output coding is controlled by pins OTC and CE_N. Table 6. Pin OTC LOW HIGH X [1] [1] X = don’t care. Output format selection Chip enable Pin CE_N LOW LOW HIGH Output data Pins D0 to D7, CCS and IR active; binary active; 2’s complement high-impedance 2’s complement outputs ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 6 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 7.3 Timing output sample n sample n+1 sample n+2 sample n+3 sample n+4 IN, INN td(s) CLK+, CLK− n 50 % td(o) D0 to D7 data n−2 data n−1 th(o) data n data n+1 001aab892 Fig 5. Output timing diagram (CCS not selected) 7.4 Timing complete conversion signal The ADC0808S generates an adjustable clock output signal on pin CCS called Complete Conversion Signal, which can be used to control the acquisition of converted output data to the digital circuit connected to the ADC0808S output data bus. Two logic input pins DEL0 and DEL1 control the delay of the edge of the CCS signal to achieve an optimal position in the stable, usable zone of the data as shown in Figure 6. Table 7. Pin DEL0 LOW HIGH LOW HIGH Complete conversion signal selection Pin DEL1 LOW LOW HIGH HIGH Pin CCS high-impedance active; see Table 13 Pin CCSSEL selects the CCS frequency; see Table 8. Table 8. Complete conversion signal frequency selection CCS frequency (fCCS) fclk fclk / 2 Pin CCSSEL HIGH or not connected LOW ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 7 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz D0 to D7 data n−2 data n−1 td(CCS) data n data n+1 CCS (fclk) 50 % CCS (fclk / 2) 50 % 001aab893 Fig 6. Complete conversion signal timing diagram using CCS 7.5 Full-scale input selection The ADC0808S has an internal reference circuit which can be overruled by an external reference voltage. This can be done with the full-scale reference voltage (Vref(fs)) according to Table 9. The ADC provides the required common-mode voltage on pin CMADC. In case of internal regulation, the regulator output voltage on pin CMADC is 0.95 V. Table 9. Full-scale input selection Common-mode output voltage VO(cm) 0.8 V 0.86 V 0.94 V 1.01 V 1.09 V Maximum peak-to-peak input voltage Vi(p-p)(max) 1.825 V 1.91 V 1.99 V 2.08 V 2.16 V Full-scale reference voltage Vref(fs) 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V The internal reference circuit is enabled by connecting pin FSIN to ground. The common-mode output voltage VO(cm) on pin CMADC will then be 0.95 V, and the maximum peak-to-peak input voltage Vi(p-p)(max) will be 2.0 V; see Figure 7 and Figure 8. The ADC full-scale input selection principle is shown in Figure 9. ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 8 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 1.1 VO(cm) (V) 1.0 001aai270 0.9 0.8 0.7 0 1.1 1.2 1.3 VFSIN (V) 1.4 Fig 7. ADC common-mode output voltage VO(cm) as a function of VFSIN 2.2 Vi(p-p)(max) (V) 2.1 001aai269 2.0 1.9 1.8 1.0 1.1 1.2 1.3 VFSIN (V) 1.4 Fig 8. ADC maximum peak-to-peak input voltage Vi(p-p)(max) as a function of VFSIN IN INN FSIN/REFSEL CMADC 1.15 V to 1.35 V 0.8 V to 1.1 V analog input IN INN FSIN/REFSEL CMADC 0.95 V analog input 001aai273 a. External reference voltage applied Fig 9. ADC full-scale input selection b. Internal reference circuit enabled ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 9 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 8. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO Vi(IN) Vi(INN) Vi(CLK) Tstg Tamb Tj Parameter analog supply voltage digital supply voltage output supply voltage input voltage on pin IN input voltage on pin INN input voltage on pin CLK storage temperature ambient temperature junction temperature referenced to AGND referenced to AGND referenced to DGND Conditions Min −0.5 −0.5 −0.5 −0.5 −0.5 −0.5 −55 −40 Max +4.6 +2.5 +2.5 VCCA + 1 VCCA + 1 +150 +85 150 Unit V V V V V °C °C °C VCCD + 0.55 V 9. Thermal characteristics Table 11. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions [1] [1] Typ 36.2 14.3 Unit K/W K/W In compliance with JEDEC test board, in free air. 10. Static characteristics Table 12. Static characteristics VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together; Tamb = −40 °C to +85 °C; Vi(IN) − Vi(INN) = 2.0 V − 0.5 dB; VI(cm) = 0.95 V; VFSIN = 0 V; typical values are measured at VCCA = 3.3 V, VCCD = VCCO = 1.8 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Supplies VCCA VCCD VCCO ICCA ICCD ICCO Ptot Ri Ci ∆VI analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current total power dissipation input resistance input capacitance input voltage range VI on pin CLK+ or CLK−; |Vgpd| < 50 mV fclk = 125 MHz; fi = 1.25 MHz fclk = 125 MHz; fi = 1.25 MHz fclk = 125 MHz; fi = 1.25 MHz fclk = 125 MHz; fi = 1.25 MHz [1] [1] Parameter Conditions Min 3.0 1.65 1.65 825 Typ 3.3 1.80 1.80 60 12 11 240 10 1 - Max 3.6 1.95 1.95 1575 Unit V V V mA mA mA mW kΩ pF mV Clock inputs: pins CLK+ and CLK− LVDS clock input; see Figure 3 [2] ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 10 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz Table 12. Static characteristics …continued VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together; Tamb = −40 °C to +85 °C; Vi(IN) − Vi(INN) = 2.0 V − 0.5 dB; VI(cm) = 0.95 V; VFSIN = 0 V; typical values are measured at VCCA = 3.3 V, VCCD = VCCO = 1.8 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Vidth II VIL VIH IIL IIH Ri Ci VI(cm) Parameter input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input resistance input capacitance common-mode input voltage Vi(IN) = Vi(INN); output code = 127 VIL = 0.2VCCD VIH = 0.8VCCD [1] [1] Conditions [2] Min −100 DGND 0.8VCCD 0.7 Typ 1.0 1.0 0.95 Max +100 50 0.2VCCD VCCD 50 50 1.0 Unit mV µA V V µA µA MΩ pF V input differential threshold voltage |Vgpd| < 50 mV 825 mV < VI < 1575 mV 1.8 V CMOS clock input; see Figure 4 Analog inputs: pins IN and INN Digital input pins: OTC, CE_N, DEL0, DEL1, CLKSEL and CCSSEL VIL VIH IIL IIH VO(cm) VFSIN Ii(FSIN) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current common-mode output voltage FSIN[3] internal reference external reference input current on pin FSIN internal reference external reference VFSIN = 1.15 V VFSIN = 1.25 V VFSIN = 1.35 V Digital outputs: pins D0 to D7, CCS and IR VOL VOH [1] [2] [3] DGND 0.8VCCD VIL = 0.3VCCD VIH = 0.7VCCD 0.85 1.15 1.92 1.80 1.98 2.11 OGND 0.95 0 1.25 12 2 1.825 1.99 2.16 - 0.2VCCD VCCD 50 50 1.1 0.6 1.35 2.03 1.85 2.03 2.18 0.2 VCCO V V µA µA V V V µA V V V V V V Voltage controlled regulator output: pin CMADC Reference voltage input: pin voltage on pin FSIN Vi(p-p)(max) maximum peak-to-peak input voltage LOW-level output voltage HIGH-level output voltage VCCO − 0.2 - Guaranteed by design. |Vgpd| is the voltage of ground potential difference across or between boards. The ADC input range can be adjusted with an external reference voltage applied to pin FSIN. This voltage must be referenced to AGND. ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 11 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 11. Dynamic characteristics Table 13. Dynamic characteristics VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together; Tamb = −40 °C to +85 °C; Vi(IN) − Vi(INN) = 2.0 V − 0.5 dB; VI(cm) = 0.95 V; VFSIN = 0 V; typical values are measured at VCCA = 3.3 V, VCCD = VCCO = 1.8 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol fclk(min) fclk(max) tw(clk) td(s) th(o) td(o) Parameter minimum clock frequency maximum clock frequency clock pulse width sampling delay time output hold time output delay time fclk = 125 MHz 1.8 V CMOS clock LVDS clock 1.8 V CMOS clock LVDS clock 1.8 V CMOS clock LVDS clock Timing complete conversion signal: pin CCS; see Figure 6 fCCS(max) td(CCS) maximum CCS frequency CCS delay time DEL0 = HIGH; DEL1 = LOW DEL0 = LOW; DEL1 = HIGH DEL0 = HIGH; DEL1 = HIGH 3-state output delay time: pins CCS, IR and D7 to D0 tdZH tdZL tdHZ tdLZ INL DNL EO EG float to active HIGH delay time float to active LOW delay time active HIGH to float delay time active LOW to float delay time integral non-linearity differential non-linearity offset error gain error fclk = 20 MHz; fi = 21.4 MHz fclk = 20 MHz; fi = 21.4 MHz; no missing code guaranteed VCCA = 3.3 V; VCCD = 1.8 V; Tamb = 25 °C; output code = 127 spread from device to device; VCCA = 3.3 V; VCCD = 1.8 V; Tamb = 25 °C fclk = 125 MHz; −3 dB; full-scale input fclk = 125 MHz; fi = 78 MHz fclk = 250 MHz; fi = 125 MHz Nth(RMS) S/N RMS thermal noise signal-to-noise ratio shorted input; fclk = 125 MHz fclk = 125 MHz; fi = 78 MHz fclk = 250 MHz; fi = 125 MHz [4] [2] Conditions Min 250 1.8 3.3 4.2 125 - Typ 1.3 1.65 4.4 4.8 5.4 5.8 0.3 0.8 1.9 2.1 2.2 3.3 2.9 ±0.82 ±0.4 2.5 1.85 Max 1 6.9 7.3 - Unit MHz MHz ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns LSB LSB mV % Clock timing input: pins CLK+ and CLK− Timing output: pins D0 to D7 and IR[1]; see Figure 5 Analog signal processing (50 % clock duty factor); see Section 12 B THD bandwidth total harmonic distortion - 560 −53 −53 0.5 48 47 - MHz dB dB LSB dBc dBc [3] ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 12 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz Table 13. Dynamic characteristics …continued VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together; Tamb = −40 °C to +85 °C; Vi(IN) − Vi(INN) = 2.0 V − 0.5 dB; VI(cm) = 0.95 V; VFSIN = 0 V; typical values are measured at VCCA = 3.3 V, VCCD = VCCO = 1.8 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol SFDR IMD2 IMD3 Parameter spurious free dynamic range second-order intermodulation distortion third-order intermodulation distortion Conditions fclk = 125 MHz; fi = 78 MHz fclk = 250 MHz; fi = 125 MHz f1 = 124 MHz; f2 = 126 MHz; fclk = 250 MHz f1 = 124 MHz; f2 = 126 MHz; fclk = 250 MHz [5] Min - Typ 55 55 −55 −60 Max - Unit dBc dBc dB dB [5] [1] [2] [3] [4] [5] Output data acquisition: the output data is available after the maximum delay of td(o). The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. The total harmonic distortion is obtained with the addition of the first five harmonics. The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency. Intermodulation measured relative to either tone with analog input frequencies f1 and f2. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full-scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third-order intermodulation product. 12. Definitions 12.1 Static parameters 12.1.1 Integral non-linearity Integral non-linearity (INL) is defined as the deviation of the transfer function from a best-fit straight line (linear regression computation). The INL of the code is obtained from the equation: V in ( i ) – V in ( ideal ) INL ( i ) = ----------------------------------------------S (1) where: S corresponds to the slope of the ideal straight line (code width), i corresponds to the code value, Vin is the input voltage. 12.1.2 Differential non-linearity Differential non-linearity (DNL) is the deviation in code width from the value of 1 LSB. V in ( i + 1 ) – V in ( i ) DNL ( i ) = -------------------------------------------S where: Vin is the input voltage; i is a code value from 0 to (2n − 2). (2) 12.2 Dynamic parameters Figure 10 shows the spectrum of a single tone full-scale input sine wave of frequency ft, conforming to coherent sampling and which is digitized by the ADC under test. Coherent sampling: (ft / fs = M / N, where M = number of cycles and N = number of samples, M and N values being relatively prime). ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 13 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz a1 magnitude SFDR s a2 a3 ak frequency 001aag627 a = harmonic. s = single tone. Fig 10. Single tone spectrum of full-scale input sine wave of frequency ft Remark: Pnoise in the equations in the following sections, is the sum of noise sources which include random noise, non-linearities, sampling time errors, and quantization noise. 12.2.1 Signal-to-Noise And Distortion (SINAD) SINAD is the ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ dB ] = 10log 10  ---------------------------------------   P noise + distortion (3) 12.2.2 Effective Number Of Bits (ENOB) ENOB is derived from SINAD and gives the theoretical resolution required by an ideal ADC to obtain the same SINAD measured on the real ADC. A good approximation gives: SINAD – 1.76 ENOB = ---------------------------------6.02 (4) 12.2.3 Total Harmonic Distortion (THD) THD is the ratio of the power of the harmonics to the power of the fundamental. For k − 1 harmonics the THD is: P harmonics THD [ dB ] = 10log 10  ------------------------   P signal - where: (5) ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 14 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 2 2 2 P harmonics = a 2 + a 3 + … + a k P signal = a 1 2 (6) (7) The value of k is usually 6 (THD is calculated based on the first 5 harmonics). 12.2.4 Signal-to-Noise ratio (S/N) S/N is the ratio of the output signal power to the noise power, excluding the harmonics and the DC component: P signal S ⁄ N = 10log 10  ---------------   P noise- (8) 12.2.5 Spurious Free Dynamic Range (SFDR) The SFDR value specifies the available signal range as the spectral distance between the amplitude of the fundamental (a1) and the amplitude of the largest spurious harmonic and non-harmonic (max (s)), excluding the DC component: a1 SFDR [ dB ] = 20log 10  -----------------   max ( s ) (9) 12.2.6 InterModulation Distortion (IMD) magnitude f2 f1 2f2 − f1 f1 − f2 2f1 − f2 f1 + f2 2f2 2f1 f1 + 2f2 2f1 + f2 3f2 3f1 frequency 001aag628 Fig 11. Spectrum of dual tone input sine wave of frequencies f1 and f2 The second-order and third-order intermodulation distortion products IMD2 and IMD3 are defined using a dual tone input sinusoid, where f1 and f2 are chosen according to the coherence criterion. IMD is the ratio of the RMS value of either tone to the RMS value of the worst, second or third-order intermodulation products. ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 15 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz The total intermodulation distortion is given by: P intermod IMD [ dB ] = 10log 10  ---------------------   P signal - where: P intermod = a im ( f 2 – f 2) (10) 1 – a im ( f 2 2 1 + f 2) + a im ( f 2 2 1 – 2 f 2) + a im ( f 2 1 + 2 f 2) +… (11) … + a im ( 2 f where a im ( f 2 2 n) 1 – f 2) + a im ( 2 f 1 + f 2) is the power in the intermodulation component at fn. 2 2 P signal = a f + a f 1 (12) ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 16 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 13. Package outline HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad SOT545-2 c y exposed die pad side X Dh 36 37 25 24 ZE A e Eh wM θ bp pin 1 index 48 1 wM 12 ZD vM A 13 detail X Lp L E HE A A2 A1 (A 3) bp e D HD B vM B 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 7.1 6.9 Dh 4.6 4.4 E(1) 7.1 6.9 Eh 4.6 4.4 e 0.5 HD 9.1 8.9 HE 9.1 8.9 L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 0.9 0.6 0.9 0.6 θ 7° 0° Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT545-2 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 04-01-29 Fig 12. Package outline SOT545-2 (HTQFP48) ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 17 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 18 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Table 14. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 15. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 19 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 20 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 15. Revision history Table 16. Revision history Release date 20090224 Data sheet status Product data sheet Change notice Supersedes ADC0808S125_ ADC0808S250_2 TDA9917_1 Document ID ADC0808S125_ADC0808S250_3 Modifications: ADC0808S125_ADC0808S250_2 TDA9917_1 • Table 13 updated. Product data sheet Objective data sheet - 20081007 20060609 ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 21 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC0808S125_ADC0808S250_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 24 February 2009 22 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 8 9 10 11 12 12.1 12.1.1 12.1.2 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 13 14 14.1 14.2 14.3 14.4 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 5 CMOS/LVDS clock input . . . . . . . . . . . . . . . . . . 5 Digital output coding . . . . . . . . . . . . . . . . . . . . . 6 Timing output . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Timing complete conversion signal. . . . . . . . . . 7 Full-scale input selection . . . . . . . . . . . . . . . . . 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal characteristics. . . . . . . . . . . . . . . . . . 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Static parameters . . . . . . . . . . . . . . . . . . . . . . 13 Integral non-linearity . . . . . . . . . . . . . . . . . . . . 13 Differential non-linearity . . . . . . . . . . . . . . . . . 13 Dynamic parameters. . . . . . . . . . . . . . . . . . . . 13 Signal-to-Noise And Distortion (SINAD) . . . . . 14 Effective Number Of Bits (ENOB) . . . . . . . . . . 14 Total Harmonic Distortion (THD). . . . . . . . . . . 14 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 15 Spurious Free Dynamic Range (SFDR) . . . . . 15 InterModulation Distortion (IMD). . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering of SMD packages . . . . . . . . . . . . . . 18 Introduction to soldering . . . . . . . . . . . . . . . . . 18 Wave and reflow soldering . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 February 2009 Document identifier: ADC0808S125_ADC0808S250_3