ADC1002S020HL

ADC1002S020 Single 10 bits ADC, up to 20 MHz Rev. 02 — 13 August 2008 Product data sheet 1. General description The ADC1002S020 is a 10-bit high-speed Analog-to-Digital Converter (ADC) for professional video and other applications. It converts with 3.0 V to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows a reduction of the device power consumption to 4 mW. 2. Features I I I I I I I I I I I I 10-bit resolution 3.0 V to 5.25 V operation Sampling rate up to 20 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 MHz; full-scale input at fclk = 20 MHz) In-Range (IR) CMOS output CMOS/Transistor-Transistor Logic (TTL) compatible digital inputs and outputs External reference voltage regulator Power dissipation only 53 mW (typical value) Low analog input capacitance, no buffer amplifier required Standby mode No sample-and-hold circuit required 3. Applications I I I I I Video data digitizing Camera Camcorder Radio communication Barcode scanner NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 4. Quick reference data Table 1. Quick reference data VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol VDDA VDDD1 VDDD2 VDDO IDDA IDDD IDDO Parameter analog supply voltage digital supply voltage 1 digital supply voltage 2 output supply voltage analog supply current digital supply current output supply current fclk = 20 MHz; ramp input; CL = 20 pF ramp input; see Figure 6 ramp input; see Figure 7 operating; VDDD = 3.3 V standby mode Conditions Min 3.0 3.0 3.0 3.0 Typ 3.3 3.3 3.3 3.3 7.5 7.5 1 Max 5.25 5.25 5.25 5.25 10 10 2 Unit V V V V mA mA mA INL DNL fclk(max) Ptot integral non-linearity differential non-linearity maximum clock frequency total power dissipation 20 - ±1 ±0.25 53 4 ±2 ±0.7 73 - LSB LSB MHz mW mW 5. Ordering information Table 2. Ordering information Package Name ADC1002S020HL LQFP32 Description plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm Version SOT401-1 Type number ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 2 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 6. Block diagram VDDA 7 CLK 5 VDDD2 18 OE 16 CLOCK DRIVER RT 15 6 STDBY ADC1002S020 1 D9 MSB 31 D8 30 D7 Rlad analog voltage input VI 14 ANALOG - TO - DIGITAL CONVERTER LATCHES CMOS OUTPUTS 29 D6 28 D5 27 D4 26 D3 RM 11 25 D2 23 D1 22 D0 20 LSB data outputs RB 10 VDDO IN - RANGE LATCH CMOS OUTPUT 2 IR output 4 VDDD1 9 VSSA analog ground 19 VSSD2 digital ground 2 21 VSSO output ground 3 VSSD1 digital ground 1 014aaa482 Fig 1. Block diagram ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 3 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 7. Pinning information 7.1 Pinning 32 n.c. 31 D8 30 D7 29 D6 28 D5 27 D4 26 D3 25 D2 24 n.c. 23 D1 22 D0 21 VSSO 20 VDDO 19 VSSD2 18 VDDD2 17 n.c. RB 10 RM 11 n.c. 12 n.c. 13 VI 14 RT 15 OE 16 9 014aaa483 D9 IR VSSD1 VDDD1 CLK STDBY VDDA n.c. 1 2 3 4 ADC1002S020HL 5 6 7 8 Fig 2. Pin configuration 7.2 Pin description Table 3. Symbol D9 IR VSSD1 VDDD1 CLK STDBY VDDA n.c. VSSA RB RM n.c. n.c. VI RT OE n.c. VDDD2 ADC1002S020_2 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description data output; bit 9 (Most Significant Bit (MSB)) in-range data output digital ground 1 digital supply voltage 1 (3.0 V to 5.25 V) clock input standby mode input analog supply voltage (3.0 V to 5.25 V) not connected analog ground reference voltage BOTTOM input reference voltage MIDDLE input not connected not connected analog voltage input reference voltage TOP input output enable input (active LOW) not connected digital supply voltage 2 (3.0 V to 5.25 V) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 VSSA 4 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz Pin description …continued Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description digital ground 2 positive supply voltage for output stage (3.0 V to 5.25 V) output stage ground data output; bit 0 (Least Significant Bit (LSB)) data output; bit 1 not connected data output; bit 2 data output; bit 3 data output; bit 4 data output; bit 5 data output; bit 6 data output; bit 7 data output; bit 8 not connected Table 3. Symbol VSSD2 VDDO VSSO D0 D1 n.c. D2 D3 D4 D5 D6 D7 D8 n.c. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDA VDDD VDDO ∆VDD Parameter analog supply voltage digital supply voltage output supply voltage supply voltage difference VDDA − VDDD VDDD − VDDO VDDA − VDDO referenced to VSSA referenced to VSSD Conditions [1] [1] [1] Min −0.3 −0.3 −0.3 −0.1 Max +7.0 +7.0 +7.0 +4.0 Unit V V V V VI Vi(a)(p-p) IO Tstg Tamb Tj [1] input voltage peak-to-peak analog input voltage output current storage temperature ambient temperature junction temperature −0.3 −55 −20 - +7.0 VDDD 10 +150 +75 150 V V mA °C °C °C The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply voltage ∆VDD remains as indicated. 9. Thermal characteristics Table 5. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Condition in free air Value 90 Unit K/W ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 5 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 10. Characteristics Table 6. Characteristics VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol Supplies VDDA VDDD1 VDDD2 VDDO ∆VDD IDDA IDDD IDDO Ptot Inputs Clock input CLK (Referenced to VSSD);[1] VIL VIH IIL IIH Zi Ci VIL VIH IIL IIH IIL IIH Zi Ci VRB VRT LOW-level input voltage HIGH-level input voltage VDDD ≤ 3.6 V VDDD > 3.6 V LOW-level input current input impedance input capacitance LOW-level input voltage HIGH-level input voltage VDDD ≤ 3.6 V VDDD > 3.6 V LOW-level input current VIL = 0.3 VDDD HIGH-level input current VIH = 0.7 VDDD LOW-level input current input impedance input capacitance voltage on pin RB voltage on pin RT VI = VRB fi = 1 MHz fi = 1 MHz VCLK = 0.3 VDDD fclk = 20 MHz fclk = 20 MHz HIGH-level input current VCLK = 0.7 VDDD 0 0.6 VDDD 0.7 VDDD −1 0 0.6 VDDD 0.7 VDDD −1 1.1 3.0 0 4 3 0 35 5 8 1.2 3.3 0.3 VDDD VDDD VDDD +1 5 0.3 VDDD VDDD VDDD 1 VDDA V V V µA µA kΩ pF V V V µA µA µA µA kΩ pF V V analog supply voltage digital supply voltage 1 digital supply voltage 2 output supply voltage supply voltage difference VDDA − VDDD; VDDD − VDDO; VDDA − VDDO analog supply current digital supply current output supply current total power dissipation fclk = 20 MHz; ramp input; CL = 20 pF operating; VDDD = 3.3 V standby mode 3.0 3.0 3.0 3.0 −0.2 3.3 3.3 3.3 3.3 7.5 7.5 1 53 4 5.25 5.25 5.25 5.25 +0.2 10 10 2 73 V V V V V mA mA mA mW mW Parameter Conditions Min Typ Max Unit Inputs OE and STDBY (Referenced to VSSD); see Table 7 and 8 Analog input VI (Referenced to VSSA); HIGH-level input current VI = VRT Reference voltages for the resistor ladder; see Table 8 ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 6 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz Table 6. Characteristics …continued VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol Vref(dif) Iref Rlad TCRlad Voffset Vi(p-p) Parameter differential reference voltage reference current ladder resistance ladder resistor temperature coefficient offset voltage peak-to-peak input voltage LOW-level output voltage HIGH-level output voltage IO = 1 mA IO = −1 mA BOTTOM TOP [2] [2] [3] Conditions VRT − VRB Min 1.9 1.66 Typ 2.1 7.2 290 539 1860 135 135 1.83 Max 3.0 2.35 Unit V mA Ω mΩ/K ppm mV mV V Digital outputs D9 to D0 and IR (Referenced to VSSD) VOL VOH IOZ fclk(max) tw(clk)H tw(clk)L Linearity INL DNL ts(LH) ts(HL) integral non-linearity differential non-linearity LOW to HIGH settling time HIGH to LOW settling time ramp input; see Figure 6 ramp input; see Figure 7 full-scale square wave full-scale square wave ±1 ±0.25 4 4 ±2 ±0.7 6 6 LSB LSB ns ns 0 VDDO − 0.5 −20 4;[1] 20 15 15 MHz ns ns 0.5 VCCO +20 V V µA OFF-state output current 0.5 V < VO < VDDO maximum clock frequency HIGH clock pulse width LOW clock pulse width Switching characteristics; Clock input CLK; see Figure Analog signal processing (fclk = 20 MHz) Input set response; see Figure 8[4] Harmonics; see Figure 9[5] THD S/N total harmonic distortion fi = 1 MHz 9[5] without harmonics; fi = 1 MHz fi = 300 KHz fi = 1 MHz fi = 3.58 MHz 60 dB signal-to-noise ratio −63 dB Signal-to-Noise ratio; see Figure Effective bits; see Figure 9[5] ENOB effective number of bits 9.5 9.3 8.0 bits bits bits ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 7 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz Table 6. Characteristics …continued VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 °C to 70 °C; typical values measured at Tamb = 25 °C unless otherwise specified. Symbol td(s) th(o) td(o) Parameter sampling delay time output hold time output delay time VDDO = 4.75 V VDDO = 3.15 V 3-state output delay times; see Figure 5 tdZH tdZL tdHZ tdLZ float to active HIGH delay time float to active LOW delay time active HIGH to float delay time active LOW to float delay time LOW to HIGH transition time HIGH to LOW transition time stand-by start-up 14 16 16 14 18 20 20 18 ns ns ns ns Conditions 4[6] 5 8 8 12 17 5 15 20 ns ns ns ns Min Typ Max Unit Timing (fclk = 20 MHz; CL = 20 pF); see Figure Standby mode output delay times tTLH tTHL 200 500 ns ns [1] [2] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. Analog input voltages producing code 0 up to and including code 1023: a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 °C. b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 °C. To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. a) The current flowing into the resistor ladder is I = --------------------------------------- and the full-scale input range at the converter, to cover code 0 - [3] V RT – V RB R OB + R L + R OT to 1023 is V I = R L × I L = --------------------------------------- × ( V RT + V RB ) = 0.871 × ( V RT – V RB ) - RL R OB + R L + R OT b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio --------------------------------------will be kept reasonably constant from device to device. Consequently variation of the output codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] [5] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to SIgnal-to-Noise And Distortion (SINAD) ratio: SINAD = ENOB × 6.02 + 1.76 dB. Output data acquisition: the output data is available after the maximum delay time of td(o). RL R OB + R L + R OT [6] ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 8 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 11. Additional information relating to Table 6 RT ROT code 1023 RL RL RM RL IL Rlad RL code 0 ROB RB 014aaa480 Fig 3. Converter reference resistor ladder Table 7. OE 1 0 Table 8. STBY 1 0 Table 9. Code Underflow 0 1 ↓ 1022 1023 Overflow Mode selection D9 to D0 high impedance active; binary Standby selection D9 to D0 last logic state active ICCA + ICCD 1.2 mA (typical value) 15 mA (typical value) IR high impedance active Output coding and input voltage (typical values; referenced to VSSA) Vi(a)(p-p) (V) < 1.335 1.335 3.165 > 3.165 IR 0 1 1 ↓ 1 1 0 Binary outputs D9 to D0 00 0000 0000 00 0000 0000 00 0000 0001 ↓ 11 1111 1110 11 1111 1111 11 1111 1111 ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 9 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz sample N sample N + 1 tw(clk)L sample N + 2 tw(clk)H CLK 50% sample N sample N + 1 sample N + 2 VI td(s) th(o) VDDO DATA D0 to D9 DATA N−2 DATA N−1 td(o) DATA N DATA N+1 50% 0V 014aaa481 Fig 4. Timing diagram ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 10 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz VDDD OE 50 % tdHZ HIGH 90 % output data tdLZ HIGH output data LOW 10 % tdZL tdZH 50 % LOW 50 % TEST VDDO 3.3 kΩ S1 VDDO VDDO VSSO VSSO tdLZ tdZL tdHZ tdZH ADC1002S020 20 pF S1 OE 014aaa484 frequency on pin OE= 100 kHz. Fig 5. Timing diagram and test conditions of 3-state output delay time 0.6 A (LSB) 0.2 014aaa491 −0.2 −0.6 0 200 400 600 800 1023 1000 f (MHZ) 1200 Fig 6. Typical Integral Non-Linearity (INL) performance ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 11 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 0.25 A (LSB) 0.15 014aaa492 0.05 −0.05 −0.15 1023 −0.25 0 200 400 600 800 1000 f (MHZ) 1200 Fig 7. Typical Differential Non-Linearity (DNL) performance ts(LH) code 1023 VI code 0 5 ns 50 % ts(HL) 50 % 5 ns CLK 50 % 50 % 2 ns 2 ns 014aaa479 Fig 8. Analog input settling time diagram ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 12 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 0 A (dB) −40 014aaa493 −80 −120 0 2.5 5.01 7.51 f (MHz) 10 Effective bits: 9.59; THD = −76.60 dB. Harmonic levels (dB): 2nd = −81.85; 3rd = −87.56; 4th = −88.81; 5th = −88.96; 6th = −79.58. Fig 9. Typical fast Fourier transform (fclk = 20 MHz; fi = 1 MHz) ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 13 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz VDDO VDDA D9 to D0 IR VI VSSO 014aaa485 VSSA 014aaa486 Fig 10. D9 to D0 and IR outputs Fig 11. VI analog input VDDA VDDO RT Rlad Rlad OE STDBY RM Rlad Rlad RB VSSO VSSA 014aaa487 014aaa488 Fig 12. OE and STDBY inputs Fig 13. RB, RM and RT inputs VDDD CLK 1/ V 2 DDD VSSD 014aaa489 Fig 14. CLK input ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 14 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 12. Application information 12.1 Application diagram n.c.(2) D9 32 1 D8 31 D7 30 D6 29 D5 28 D4 27 D3 26 D2 25 24 n.c.(2) IR 2 23 D1 VSSD1 3 22 D0 VDDD1 4 21 VSSO ADC1002S020 CLK 5 20 VDDO STDBY 6 19 VSSD2 VDDA 7 18 VDDD2 n.c.(2) 8 9 VSSA 10 RB(1) 11 RM(1) (3) 12 n.c.(2) 13 n.c.(2) 14 VI(4) 15 RT(1) 17 16 OE n.c.(2) 100 nF 100 nF 100 nF 014aaa490 VSSA VSSA VSSA The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built in such a way that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupling capacitor. (1) RB, RM and RT are decoupled to VSSA (2) Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence (3) When RM is not used, pin 11 can be left open circuit, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded. (4) When the analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14). Fig 15. Application diagram ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 15 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 13. Package outline LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm SOT401-1 c y X 24 25 17 16 ZE A e E HE wM bp 32 1 8 9 detail X Lp L A A2 A1 pin 1 index θ (A 3) e bp D HD ZD wM B vM A vM B 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.5 1.3 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 5.1 4.9 E (1) 5.1 4.9 e 0.5 HD 7.15 6.85 HE 7.15 6.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 θ 7 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT401-1 REFERENCES IEC 136E01 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-20 Fig 16. Package outline SOT401-1 (LQFP32) ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 16 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 14. Revision history Table 10. Revision history Release date 20080813 Data sheet status Product data sheet Product data sheet Change notice Supersedes ADC1002S020_1 Document ID ADC1002S020_2 Modifications: ADC1002S020_1 • Corrections made to cross references and note 3 a) in Table 6. 20080612 ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 17 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1002S020_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 13 August 2008 18 of 19 NXP Semiconductors ADC1002S020 Single 10 bits ADC, up to 20 MHz 17. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 12.1 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . . 9 Application information. . . . . . . . . . . . . . . . . . 15 Application diagram . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 August 2008 Document identifier: ADC1002S020_2