ADC1006S055

ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Rev. 02 — 12 August 2008 Product data sheet 1. General description The ADC1006S055/070 are a family of Bipolar CMOS (BiCMOS) 10-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used. 2. Features I I I I I I I I I I I I I I I I 10-bit resolution Sampling rate up to 70 MHz −3 dB bandwidth of 245 MHz 5 V power supplies and 3.3 V output power supply Binary or two’s complement CMOS outputs In-range CMOS compatible output TTL and CMOS compatible static digital inputs TTL and CMOS compatible digital outputs Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible Power dissipation 550 mW (typical) Low analog input capacitance (typical 2 pF), no buffer amplifier required Integrated sample-and-hold amplifier Differential analog input External amplitude range control Voltage controlled regulator included −40 °C to +85 °C ambient temperature 3. Applications High-speed analog-to-digital conversion for: I Cellular infrastructure I Professional telecommunication I Digital radio I Radar I Medical imaging I Fixed network I Cable modem NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz I Barcode scanner I Cable Modem Termination System (CMTS)/Data Over Cable Service Interface Specification (DOCSIS) 4. Quick reference data Table 1. Quick reference data VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol VCCA VCCD VCCO ICCA ICCD ICCO INL DNL Parameter analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current integral non-linearity differential non-linearity fclk = 20 MHz; fi = 400 kHz fclk = 20 MHz; fi = 400 kHz fclk = 20 MHz; fi = 400 kHz (no missing code guaranteed) ADC1006S055H ADC1006S070H fclk = 55 MHz; fi = 20 MHz Conditions Min 4.75 4.75 3.0 Typ 5.0 5.0 3.3 78 27 3 ±0.65 ±0.12 Max 5.25 5.25 3.6 87 30 4 ±1.12 ±0.27 Unit V V V mA mA mA LSB LSB fclk(max) Ptot maximum clock frequency total power dissipation 55 70 - 550 660 MHz MHz mW 5. Ordering information Table 2. Ordering information Package Name ADC1006S055H ADC1006S070H QFP44 QFP44 Description plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm Version Sampling frequency (MHz) Type number SOT307-2 55 SOT307-2 70 ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 2 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 6. Block diagram VCCA1 2 n.c. 12 VCCA3 VCCA4 3 41 CLKN 35 CLK 36 VCCD1 37 VCCD2 15 OTC 18 CE 19 21 D9 CLOCK DRIVER FSREF VREF REFERENCE 22 D8 23 D7 24 D6 25 D5 CMOS OUTPUTS ANALOG-TO-DIGITAL CONVERTER LATCHES 26 D4 27 D3 28 D2 29 D1 30 D0 33 1 5 CMADC REFERENCE LSB VCCO data outputs 6 to 10, 13, 14, 16, 31, 32 MSB VREF 11 AMP sample and - hold 43 INN IN SH CMADC DEC 42 s 39 ADC1006S055/070 44 AGND1 4 40 OVERFLOW/ UNDERFLOW LATCH CMOS OUTPUT 20 IR 38 17 34 OGND AGND3 AGND4 DGND1 DGND2 014aaa464 Fig 1. Block diagram ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 3 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 7. Pinning information 7.1 Pinning 38 DGND1 44 AGND1 40 AGND4 34 OGND 33 VCCO 32 n.c. 31 n.c. 30 D0 29 D1 28 D2 27 D3 26 D4 25 D5 24 D6 23 D7 FSREF 12 n.c. 13 n.c. 14 VCCD2 15 n.c. 16 DGND2 17 OTC 18 CE 19 IR 20 D9 21 D8 22 014aaa442 37 VCCD1 41 VCCA4 CMADC VCCA1 VCCA3 AGND3 DEC n.c. n.c. n.c. n.c. 1 2 3 4 5 6 7 8 9 ADC1006S055/070 n.c. 10 VREF 11 Fig 2. Pin configuration 7.2 Pin description Table 3. Symbol CMADC VCCA1 VCCA3 AGND3 DEC n.c. n.c. n.c. n.c. n.c. VREF FSREF n.c. n.c. VCCD2 n.c. DGND2 ADC1006S055_070_2 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description regulator output common mode ADC input analog supply voltage 1 (5 V) analog supply voltage 3 (5 V) analog ground 3 decoupling node not connected not connected not connected not connected not connected reference voltage input full-scale reference output not connected not connected digital supply voltage 2 (5 V) not connected digital ground 2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 35 CLKN 36 CLK 43 INN 39 SH 42 IN 4 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Pin description …continued Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Description control input two’s complement output; active HIGH chip enable input (CMOS level; active LOW) in-range output data output; bit 9 (Most Significant Bit (MSB)) data output; bit 8 data output; bit 7 data output; bit 6 data output; bit 5 data output; bit 4 data output; bit 3 data output; bit 2 data output; bit 1 data output; bit 0 (Least Significant Bit (LSB)) not connected not connected output supply voltage (3.3 V) output ground complementary clock input clock input digital supply voltage 1 (5 V) digital ground 1 sample-and-hold enable input (CMOS level; active HIGH) analog ground 4 analog supply voltage 4 (5 V) analog input voltage complementary analog input voltage analog ground 1 Table 3. Symbol OTC CE IR D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 n.c. n.c. VCCO OGND CLKN CLK VCCD1 DGND1 SH AGND4 VCCA4 IN INN AGND1 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO ∆VCC Parameter analog supply voltage digital supply voltage output supply voltage supply voltage difference VCCA − VCCD VCCD − VCCO VCCA − VCCO Vi(IN) Vi(INN) ADC1006S055_070_2 Conditions [1] [1] [1] Min −0.3 −0.3 −0.3 −1.0 −1.0 −1.0 0.3 0.3 Max +7.0 +7.0 +7.0 +1.0 +4.0 +4.0 VCCA VCCA Unit V V V V V V V V input voltage on pin IN input voltage on pin INN referenced to AGND © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 5 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Vi(clk)(p-p) Parameter peak-to-peak clock input voltage output current storage temperature ambient temperature junction temperature Conditions differential clock drive at pins 35 and 36 Min Max VCCD Unit V IO Tstg Tamb Tj [1] −55 −40 - 10 +150 +85 150 mA °C °C °C The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. 9. Thermal characteristics Table 5. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Condition in free air Value 75 Unit K/W 10. Characteristics Table 6. Characteristics VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Supplies VCCA VCCD VCCO ICCA ICCD ICCO Ptot Inputs CLK and CLKN (referenced to DGND)[2] VIL LOW-level input voltage PECL mode; VCCD = 5 V TTL mode I C 3.19 0 3.52 0.8 V V analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current total power dissipation fclk = 20 MHz; fi = 400 kHz fclk = 55 MHz; fi = 20 MHz fclk = 55 MHz; fi = 20 MHz I I I I 4.75 4.75 3.0 5.0 5.0 3.3 78 27 3 9.5 550 5.25 5.25 3.6 87 30 4 12 660 V V V mA mA mA mA mW Parameter Conditions Test[1] Min Typ Max Unit ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 6 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol VIH IIL IIH Vi(dif)(p-p) Parameter HIGH-level input voltage LOW-level input current HIGH-level input current peak-to-peak differential input voltage input resistance input capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input current HIGH-level input current input resistance input capacitance common-mode input voltage common-mode output voltage load current Vref[3] full-scale fixed voltage; fi = 20 MHz; fclk = 55 MHz VI(IN)(p-p) − VI(INN)(p-p); Vref = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V C C C VCCA3 − 1.75 0.3 1.9 10 V µA V reference voltage reference current peak-to-peak differential input voltage VIL = 0.8 V VIH = 2.0 V Conditions PECL mode; VCCD = 5 V TTL mode VCLK or VCLKN = 3.19 V VCLK or VCLKN = 3.83 V AC driving mode; DC voltage level = 2.5 V fclk = 55 MHz fclk = 55 MHz Test[1] Min I C C C C 3.83 2.0 −10 1 Typ 1.5 Max 4.12 VCCD 10 2.0 Unit V V µA µA V Ri Ci VIL VIH IIL IIH D D I I I I 2 0 2.0 −20 - - 2 0.8 VCCD 20 kΩ pF V V µA µA OTC, SH and CE (referenced to DGND); see Table 7 and 8 IN and INN (referenced to AGND); see Table 7, VVREF = VCCA3 − 1.75 V IIL IIH Ri Ci VI(cm) SH = HIGH SH = HIGH fi = 20 MHz fi = 20 MHz VI(IN) = VI(INN) output code 512 C C D D C 10 10 14 450 µA µA MΩ fF VCCA3 − 1.7 VCCA3 − 1.6 VCCA3 − 1.2 V Voltage controlled regulator output CMADC VO(cm) Iload Vref Iref Vi(dif)(p-p) I I VCCA3 − 1.6 1 2 V mA Voltage input ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 7 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol VO(ref) Parameter reference output voltage LOW-level output voltage HIGH-level output voltage output current Conditions Test[1] Min Typ Max Unit V Voltage controlled regulator output FSREF VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V I VCCA3 − 1.75 - Digital outputs D9 to D0 and IR (referenced to OGND) VOL VOH Io IOL = 2 mA IOH = −0.4 mA I I 0 VCCO − 0.5 −20 0.5 VCCO +20 V V µA 3-state output level between I 0.5 V and VCCO SH = HIGH ADC1006S055H ADC1006S070H fi = 20 MHz fi = 20 MHz C I C C C Switching characteristics; Clock frequency fclk; see Figure 3 fclk(min) fclk(max) tw(clk)H tw(clk)L minimum clock frequency maximum clock frequency HIGH clock pulse width LOW clock pulse width 55 70 6.8 6.8 7 MHz MHz MHz ns ns Analog signal processing; 50 % clock duty factor; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; see Table 7 Linearity INL DNL integral non-linearity differential non-linearity offset error fclk = 20 MHz; fi = 400 kHz fclk = 20 MHz; fi = 400 kHz (no missing code guaranteed) VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 °C; output code = 512 spread from device to device; VCCA = VCCD = 5 V; VCCO = 3.3 V; Tamb = 25 °C −3 dB; full-scale input I I ±0.65 ±0.12 ±1.12 ±0.27 LSB LSB Eoffset C −25 +5 +25 mV EG gain error C −7 - +7 %FS Bandwidth (fclk = 55 MHz)[4] B bandwidth C 220 245 MHz ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 8 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol Harmonics α2H second harmonic level ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz α3H fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Total harmonic THD distortion[5] ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Thermal noise Nth(RMS) RMS thermal noise shorted input; SH = HIGH; fclk = 55 MHz C 0.12 LSB C C C I C C C −68 −68 −68 −68 −67 −67 −66 dBFS dBFS dBFS dBFS dBFS dBFS dBFS total harmonic distortion C C C I C C C C C C I C C C −77 −76 −75 −73 −75 −74 −70 −73 −73 −73 −72 −73 −73 −72 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Parameter Conditions Test[1] Min Typ Max Unit ADC1006S070H (fclk = 70 MHz) third harmonic level ADC1006S055H (fclk = 55 MHz) ADC1006S070H (fclk = 70 MHz) ADC1006S070H (fclk = 70 MHz) ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 9 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol S/N Parameter Conditions Test[1] Min Typ Max Unit Signal-to-noise ratio[6] signal-to-noise ratio ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Spurious free dynamic range; see Figure 7, 13 and 14 SFDR spurious free dynamic range ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Effective number of bits[7] ENOB effective number of bits ADC1006S055H (fclk = 55 MHz) fi = 4.43 MHz fi = 10 MHz fi = 15 MHz fi = 20 MHz fi = 4.43 MHz fi = 10 MHz fi = 15 MHz Intermodulation; (fclk = 55 MHz; fi = 20 αIM IMD3 intermodulation suppression third-order intermodulation distortion bit error rate MHz)[8] C C −69 −79 dBFS dBFS C C C I C C C 9.5 9.5 9.5 9.5 9.5 9.5 9.4 bit bit bit bit bit bit bit C C C I C C C 71 70 70 70 70 69 68 dBFS dBFS dBFS dBFS dBFS dBFS dBFS C C C I C C C 60 60 60 59.5 60 60 59 dBFS dBFS dBFS dBFS dBFS dBFS dBFS ADC1006S070H (fclk = 70 MHz) ADC1006S070H (fclk = 70 MHz) ADC1006S070H (fclk = 70 MHz) Bit error rate (fclk = 55 MHz) BER fi = 20 MHz; VI = ±16 LSB at C code 512 10−14 times/ sample © NXP B.V. 2008. All rights reserved. ADC1006S055_070_2 Product data sheet Rev. 02 — 12 August 2008 10 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Table 6. Characteristics …continued VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted together; Tamb = −40 °C to +85 °C; VI(IN)(p-p) − VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 − 1.75 V; VI(cm) = VCCA3 − 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V, Tamb = 25 °C and CL = 10 pF; unless otherwise specified. Symbol td(s) th(o) td(o) tdZH tdZL tdHZ tdLZ Parameter sampling delay time output hold time output delay time float to active HIGH delay time float to active LOW delay time active HIGH to float delay time active LOW to float delay time Conditions Test[1] Min C C C C C C C 4 Typ 0.25 6.4 9.0 5.1 7.0 9.7 9.5 Max 1 13 9.0 11 14 13 Unit ns ns ns ns ns ns ns Timing (CL = 10 pF)[9] 3-state output delay times; see Figure 4 [1] [2] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode 1: (DC level vary 1 : 1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC level vary 1 : 1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1 : 1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 1: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. The ADC input range can be adjusted with an external reference connected to VREF pin. This voltage has to be referenced to VCCA; see Figure 12. The −3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. Total Harmonic Distortion (THD) is obtained with the addition of the first five harmonics: [3] [4] [5] THD = 20 log --------------------------------------------------------------------------------------------------------------------------------------2 ( a 1H ) where α1H is the fundamental harmonic referenced at 0 dB for a full-scale sine wave input; see Figure 6. [6] [7] Signal-to-noise ratio (S/N) takes into account all harmonics above five and noise up to Nyquist frequency; see Figure 8. Effective number of bits are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to SIgnal-to_Noise_Distortion ratio (SINAD) is given by SINAD = ENOB × 6.02 + 1.76 dB; see Figure 5. Intermodulation measured relative to either tone with analog input frequencies of 20 MHz and 20.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter (−6 dB below full scale for each input signal). IMD3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product. Output data acquisition: the output data is available after the maximum delay of td(o); see Figure 3. ( α 2H ) + ( α 3H ) + ( α 4H ) + ( α ) + ( α 6H ) 2 2 2 2 2 [8] [9] ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 11 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 11. Additional information relating to Table 6 Table 7. Code Underflow 0 1 ↓ 511 ↓ 1022 1023 Overflow [1] Output coding with differential inputs (typical values to AGND); Vi(IN)(p-p) − Vi(INN)(p-p) = 1.9 V, VVREF = VCCA3 − 1.75 V Vi(a)(p-p) (V) < 3.125 3.125 3.6 4.075 > 4.075 Vi(a)(p-p) (V) > 4.075 4.075 3.6 3.125 < 3.125 IR 0 1 1 ↓ 1 ↓ 1 1 0 Binary outputs D9 to D0 00 0000 0000 00 0000 0000 00 0000 0001 ↓ 01 1111 1111 ↓ 11 1111 1110 11 1111 1111 11 1111 1111 Two’s complement outputs[1] D9 to D0 10 0000 0000 10 0000 0000 10 0000 0001 ↓ 11 1111 1111 ↓ 01 1111 1110 01 1111 1111 01 1111 1111 Two’s complement reference is inverted MSB. Table 8. OTC 0 1 X[1] [1] Mode selection CE 0 0 1 D0 to D9 and IR binary; active two’s complement; active high-impedance X = don’t care. Table 9. SH 1 0 Sample-and-hold selection Sample-and-hold active inactive; tracking mode ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 12 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz sample N sample N + 1 tw(clk)H sample N + 2 tw(clk)L HIGH 50 % LOW CLK sample N sample N + 1 sample N + 2 IN td(s) th(o) DATA D0 TO D9 DATA N−2 DATA N−1 DATA N DATA N+1 HIGH 50 % LOW td(o) 014aaa465 Fig 3. Timing diagram VCCD CE 0V tdHZ HIGH 90 % output data tdLZ HIGH output data 50 % LOW 10 % TEST VCCO tdLZ tdZL tdHZ tdZH CE 3.3 kΩ S1 15 pF 50 % tdZH 50 % tdZL LOW S1 VCCO VCCO OGND OGND 014aaa443 ADC1006S 070 (1) frequency on pin CE = 100 kHz. Fig 4. Timing diagram and test conditions of 3-state output delay time ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 13 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 9.70 ENOB (bit) 9.60 (1) 014aaa444 −63 THD (dB) −65 014aaa445 9.50 (2) −67 (1) 9.40 −69 (2) 9.30 0 5 10 15 20 25 fi (MHz) −71 0 5 10 15 20 25 fi (MHz) (1) 55 MHz. (2) 70 MHz. (1) 55 MHz. (2) 70 MHz. Fig 5. Effective Number Of Bits (ENOB) as a function of input frequency (sample device) Fig 6. Total Harmonic Distortion (THD) as a function of input frequency (sample device) 73 SFDR (dB) 72 (1) 014aaa446 60.0 S/N (dB) 59.8 014aaa447 (1) 71 59.6 70 59.4 (2) 69 (2) 59.2 68 0 5 10 15 20 25 fi (MHz) 59.0 0 5 10 15 20 25 fi (MHz) (1) 55 MHz. (2) 70 MHz. (1) 55 MHz. (2) 70 MHz. Fig 7. Spurious Free Dynamic Range (SFDR) as a function of input frequency (sample device) Fig 8. Signal-to-Noise Ratio (S/N) as a function of input frequency (sample device) ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 14 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 0 power spectrum (dB) −40 014aaa448 −80 −120 −160 0 5 10 15 20 25 fi (MHz) 30 Fig 9. Single-tone; fi = 20 MHz; fclk = 55 MHz 0 power spectrum (dB) −40 014aaa449 −80 −120 −160 0 5 10 15 20 25 fi (MHz) 30 Fig 10. Two-tone; fi 1 = 20 MHz; fi 2 = 20.1 MHz; fclk = 55 MHz ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 15 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 1.00 output range (INL) 0.60 014aaa450 0.20 −0.20 −0.60 0 256 512 768 output code 1024 Fig 11. Integral Non-Linearity (INL) 0.30 DNL (LSB) 0.20 014aaa451 0.10 0 −0.10 −0.20 0 256 512 768 output code 1024 Fig 12. Differential Non-Linearity (DNL) ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 16 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 80 SFDR (dBFS) 60 014aaa452 (1) 40 (3) (2) 20 −60 −50 −40 −30 −20 −10 0 Input amplitude (dBFS) (1) fi = 4.43 MHz. (2) fi = 20 MHz. (3) SFDR = 80 dB. Fig 13. SFDR as a function of input amplitude; Vi(IN)(p-p) − Vi(INN)(p-p) = 1.9 V; fclk = 40 MHz 80 SFDR (dBFS) 60 014aaa453 (1) 40 (2) (3) 20 −60 −50 −40 −30 −20 −10 0 Input amplitude (dBFS) (1) fi = 4.43 MHz. (2) fi = 20 MHz. (3) SFDR = 80 dB. Fig 14. SFDR as a function of input amplitude; Vi(IN)(p-p) − Vi(INN)(p-p) = 1.9 V; fclk = 55 MHz ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 17 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 75 (dB) 70 65 60 55 50 45 40 35 1.3 (1) (2) 10.0 (bit) 9.5 9.0 2.6 VI(IN)(p-p) − VI(INN)(p-p) (V) 2.2 (3) 8.5 8.0 7.5 7.0 6.5 6.0 2.2 014aaa455 1.8 1.4 1.4 1.5 1.6 1.7 1.8 1.9 2.0 VCCA − VVREF (V) 2.1 1.0 1.3 1.4 1.5 1.6 1.7 1.8 1.9 VCCA − VVREF (V) 2.0 2.1 2.2 014aaa456 (1) SFDR. (2) ENOB. (3) S/N. Fig 15. SFDR, ENOB and S/N as a function of VCCA − VVREF; fclk = 55 MHz; fi = 20 MHz Fig 16. ADC full-scale; VI(IN)(p-p) − VI(INN)(p-p) as a function of VCCA − VVREF ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 18 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 12. Application information 12.1 Application diagrams SH mode 100 nF 220 nF 100 Ω 5V 5V 100 nF 1:1 100 Ω IN CLK INN 44 1 5V 10 nF 100 nF 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 5V 100 nF 2 3 4 100 nF n.c. n.c. D0 (LSB) D1 D2 D3 D4 D5 D6 D7 5 n.c. n.c. n.c. n.c. n.c. VREF 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ADC1006S055/070 28 27 26 25 24 23 n.c. n.c. 5V n.c. IR D9 (MSB) D8 100 nF chip select input output format select 014aaa457 The analog, digital and output supplies should be separated and decoupled. Fig 17. Application diagram MC100 ELT20 TTL input D PECL CLKN CLK 270 Ω 270 Ω ADC1006S 055/070 014aaa458 Fig 18. Application diagram for differential clock input PECL compatible using a TTL to PECL translator ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 19 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz CLKN TTL input CLK ADC1006S 055/070 014aaa459 Fig 19. Application diagram for TTL single-ended clock ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 20 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 12.2 Demonstration board B11 1 VCC C6 330 nF 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 B8 J2 CLK2 R4 50 Ω 2 C15 10 nF n.c n.c D0 D1 D2 D3 D4 D5 D6 D7 VCCO FL3 VCCO B5 33 R3 100 Ω C13 100 nF 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 IC2 D8 D9 IR CE OTC DGND2 n.c. VCCD2 n.c. n.c. FSREF FL1 C12 100 nF C18 10 nF C5 330 nF FL2 S3 S4 OGND CLKN CLK VCCD1 34 35 36 37 38 39 40 41 42 43 44 1 CMADC 2 VCCA1 3 VCCA3 4 AGDN3 5 DEC 6 n.c. 7 n.c. 8 n.c. 9 n.c. 10 11 n.c. J3 CLK1 CLK1 C19 10 nF VCCD S5 C17 10 nF DGND1 SH AGND4 VCCA4 IN VCCA ADC1006S055/070 17 16 15 14 13 12 VREF VCC C9 J1 220 nF IN R1 100 Ω TR1 CMADC INN AGND1 R9 100 Ω MCLT1_6T_KK81 C8 330 nF S1 S2 C16 10 nF C10 100 nF C11 100 nF B7 P2 C7 330 nF R7 1.2 kΩ VCCA P1 5 kΩ C14 100 nF FL4 VCC VCCA 1 kΩ R6 2.4 KΩ VCCA 12 V GND J4 1 J4 2 BYD17G D3 ICI 1 IN C1 22 µF (20 V) VCC TM3 VCC OUT 3 C2 4.7 µF (16 V) R2 62 Ω MC78MO5CDT GND PMBT 2222A T1 VCCO R8 750 Ω D1 LGT679 C3 1 µF D2 BZV55C3V6 R5 4.7 kΩ C4 1 µF TP2 VCCO 014aaa460 C8 is close to TR1 pin. Fig 20. Demonstration board schematic ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 21 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz R1 J1 C9 TR1 B4 1 TM2 J3 1 S5 S1 P1 1 C14 112 C12 IC2 23 1 B5 S2 R7 TM1 S3 S4 FL2 J2 C5 R3 34 R9 C7 FL4 C10 B7 C11 R6 P2 IC1 TM3 R8 R2 T1 R5 C1 C2 D3 J4 1 2 D1 C3 D2 B8 TP2 C4 R4 B11 1 014aaa466 Fig 21. Component placement (top side) C6 FL3 C8 C19 C15 C13 C16 C17 FL1 C18 014aaa467 Fig 22. Component placement (underside) ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 22 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 1 014aaa461 Fig 23. Printed-circuit board layout (top layer) 2 014aaa462 Fig 24. Printed-circuit board layout (ground layer) ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 23 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 3 014aaa463 Fig 25. Printed-circuit board layout (power plane) 12.3 Alternative parts The following alternative parts are also available: Table 10. Alternative parts Description Single 12 bits ADC Single 12 bits ADC Single 12 bits ADC [1] [1] [1] Type number ADC1206S040 ADC1206S055 ADC1206S070 [1] Pin to pin compatible Sampling frequency 40 MHz 55 MHz 70 MHz 12.4 Recommended companion chip The recommended companion chip is the TDA9901 wideband differential digital controlled variable gain amplifier. ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 24 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 13. Support information 13.1 Definitions 13.1.1 Non-linearities 13.1.1.1 Integral Non-Linearity (INL) It is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of the code i is obtained from the equation: V I ( i ) – V I ( ideal ) INL ( i ) = -----------------------------------------S where i = 0 ⋅ ( 2 – 1 ) and S = slope of the ideal straight line = code width; i = code value. 13.1.1.2 Differential Non-Linearity (DNL) It is the deviation in code width from the value of 1 LSB. V I (i + 1) – V I (i) DNL ( i ) = ---------------------------------------- – 1 S where i = 0 ⋅ ( 2 – 2 ) n n (1) (2) 13.1.2 Dynamic parameters (single tone) Figure 26 shows the spectrum of a full-scale input sine wave with frequency ft, conforming to coherent sampling (ft / fs = M / N, where M is the number of cycles and N is number of samples, M and N being relatively prime), and digitized by the ADC under test. magnitude a1 SFDR a3 a2 ak measured output range (MHz) fs/2 014aaa440 Fig 26. Spectrum of full-scale input sine wave with frequency ft ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 25 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Remark: In the following equations, Pnoise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and ‘quantization noise’. 13.1.2.1 Signal-to-Noise And Distortion (SINAD) The ratio of the output signal power to the noise and distortion power for a given sample rate and input frequency, excluding the DC component: P signal SINAD [ dB ] = 10 log ----------------------------------------P noise + distortion 13.1.2.2 Effective Number Of Bits (ENOB) It is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the real ADC. A good approximation gives: ENOB = ( SINAD [ dB ] – ( 1.76 ) ) ⁄ ( 6.02 ) 13.1.2.3 Total Harmonic Distortion (THD) The ratio of the power of the harmonics to the power of the fundamental. For k-1 harmonics the THD is: P harmonics THD [ dB ] = 10 log -------------------------P signal where P harmonics = α 2 + α 3 + α 2 2 2 k (3) (4) 2 1 and P signal = α The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics). 13.1.2.4 Signal-to-Noise ratio (S/N) The ratio of the output signal power to the noise power, excluding the harmonics and the DC component. P signal S/N [ dB ] = 10 log ---------------P noise 13.1.2.5 Spurious Free Dynamic Range (SFDR) The number SFDR specifies available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious (harmonic and non-harmonic), excluding DC component. α1 SFDR [ dB ] = 20 log ----------------max ( s ) (6) (5) ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 26 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 13.1.3 Intermodulation distortion 13.1.3.1 Spectral analysis (dual-tone) magnitude IMD3 measured output range (MHz) fs/2 014aaa441 Fig 27. Spectral analysis (dual-tone) From a dual-tone input sinusoid (ft1 and ft2, these frequencies being chosen according to the coherence criterion), the intermodulation distortion products IMD2 and IMD3 (respectively, 2nd and 3rd-order components) are defined, as follows. 13.1.3.2 IMD2 (IMD3) The ratio of the RMS value of either tone to the RMS value of the worst second (third) order intermodulation product. The total IMD is given by: P intermod IMD [ dB ] = 10 log ----------------------P signal where, P intermod = a +a 2 ( 2 f t1 im 2 2 (f im t1 – f t2 ) – a 2 ( 2 f t1 im 2 (f im t1 + f t2 ) + a 2 (f im t1 – 2 f t2 ) + a 2 (f im t1 + 2 f t2 ) – f t2 ) + a 2 + f t2 ) P signal = a ( f t1 ) + a ( f t2 ) and a 2 (f ) im t is the power in the intermodulation component at frequency ft. 13.1.4 Noise Power Ratio (NPR) When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the NPR is defined as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample set. ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 27 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 14. Package outline QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 34 23 22 ZE e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vM A 12 detail X A A2 (A 3) θ Lp L A1 e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.1 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.4 0.2 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ 10 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 97-08-01 03-02-25 Fig 28. Package outline SOT307-2 (QFP44) ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 28 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 15. Revision history Table 11. Revision history Release date 20080812 Data sheet status Product data sheet Change notice Supersedes ADC1006S055_070_1 Document ID ADC1006S055_070_2 Modifications: ADC1006S055_070_1 • • Corrections made to titles in Figure 13 and 14. Corrections made to note in Figure 4. Product data sheet - 20080611 ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 29 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1006S055_070_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 12 August 2008 30 of 31 NXP Semiconductors ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 Additional information relating to Table 6 . . . 12 12 Application information. . . . . . . . . . . . . . . . . . 19 12.1 Application diagrams . . . . . . . . . . . . . . . . . . . 19 12.2 Demonstration board . . . . . . . . . . . . . . . . . . . 21 12.3 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 24 12.4 Recommended companion chip . . . . . . . . . . . 24 13 Support information . . . . . . . . . . . . . . . . . . . . 25 13.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.1.1 Non-linearities. . . . . . . . . . . . . . . . . . . . . . . . . 25 13.1.1.1 Integral Non-Linearity (INL) . . . . . . . . . . . . . . 25 13.1.1.2 Differential Non-Linearity (DNL) . . . . . . . . . . . 25 13.1.2 Dynamic parameters (single tone) . . . . . . . . . 25 13.1.2.1 Signal-to-Noise And Distortion (SINAD) . . . . . 26 13.1.2.2 Effective Number Of Bits (ENOB) . . . . . . . . . . 26 13.1.2.3 Total Harmonic Distortion (THD). . . . . . . . . . . 26 13.1.2.4 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 26 13.1.2.5 Spurious Free Dynamic Range (SFDR) . . . . . 26 13.1.3 Intermodulation distortion . . . . . . . . . . . . . . . . 27 13.1.3.1 Spectral analysis (dual-tone) . . . . . . . . . . . . . 27 13.1.3.2 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.1.4 Noise Power Ratio (NPR) . . . . . . . . . . . . . . . . 27 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 28 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17 Contact information. . . . . . . . . . . . . . . . . . . . . 30 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 August 2008 Document identifier: ADC1006S055_070_2