ASL2500SHNY

ASL2500SHN Two phase boost converter Rev. 3 — 26 October 2017 Product data sheet 1. Introduction The ASL2500SHN is a highly integrated and flexible two-phase DC-to-DC boost converter IC. It has an SPI interface allowing control and diagnostic communication with an external microcontroller. It is designed primarily for use in automotive LED lighting applications and provides an optimized supply voltage for ASLx415SHN Multi-channel LED Buck Driver. 2. General description The ASL2500SHN has a fixed frequency peak current mode control with parabolic/non-linear slope compensation. It can operate with input voltages from 5.5 V to 40 V. It can be configured via SPI for output voltages of up to 80 V, to power the LED buck driver IC. The ASL2500SHN is a two-phase converter which can have two independent outputs. The flexible driver can be configured, via the SPI interface, as a single output converter, or with multiple combinations of number of outputs and phases. The ASL2500SHN boost converter can drive up to two external low-side N channel MOSFETs from an internally regulated adjustable supply. It can drive either logic or standard level MOSFETs. The integrated SPI interface also allows for programming the supply under/over voltage range, output voltage range and DC-to-DC switching frequency. It enables the optimization of external components and flexibility for EMC design. This interface can also be used to provide diagnostic information such as the driver temperature. Additional features include input under-voltage lockout and thermal shutdown when the junction temperature of the ASL2500SHN exceeds +175 C. The device is housed in a very small HVQFN32 pin package with an exposed thermal pad. It is designed to meet the stringent requirements of automotive applications. It is fully AEC Q100 grade 1 qualified. It operates over the 40 C to +125 C ambient automotive temperature range. ASL2500SHN NXP Semiconductors Two phase boost converter 3. Features and benefits                        The ASL2500SHN is an automotive grade product that is AEC-Q100 grade 1 qualified. Operating ambient temperature range of 40 C to +125 C Wide operating input voltage range from +5.5 V to +40 V Output voltage programmable via SPI interface Multi-phase operation for higher power Up to two phases per output Up to two flexible output voltages with 3 % accuracy programmable via SPI Both output voltages can be controlled independently Fixed Frequency Operation via built-in oscillator Slope compensation to track the frequency and output voltage Programmable control loop compensation Fast high efficiency FET switching Programmable internal gate driver voltage regulator Gate switching is halted when overvoltage on output is detected Support both Logic Level and Standard Level FETs Low Electro Magnetic Emission (EME) and high Electro Magnetic Immunity (EMI) Output voltage monitoring Supply voltage measurement Control signal to enable the device Read-back programmed voltage and frequency range via SPI Junction temperature monitoring via SPI Small package outline HVQFN32 Low quiescent current Vth(det)pon and EN = high VBAT < Vth(det)pon or EN = low Off Cfg_dn = 1 Configuration VBAT < Vth(det)pon or EN = low Operation Cfg_dn = 0 VBAT > V_VIN_OV or VBAT < V_VIN_UV or Tj > Tsd(otp) or VGG_err = 1 or VGG_ok 1->0 VBAT < Vth(det)pon or EN = low Fail silent VBAT > V_VIN_OV or VBAT < V_VIN_UV or Tj > Tsd(otp) or VGG_err = 1 or VGG_ok 1->0 aaa-015303 Fig 3. State diagram Table 3. Operating modes Mode Control registers Configuration Diagnostic VGG registers IC registers Vout1 Remark Off n.a. n.a. n.a. Off Off device is off, no communication possible Configuration Read/write Read/write Read Off Off VGG is off if the output was not previously enabled According to register Off VGG stays on as soon as the output has been enabled Operation Read/write Read Read Locked According to register configuration register is locked Fail silent Read/write Read[1] Read Off Off communication possible, but the output is off; restart via EN possible. [1] Setting the bit cfg_dn to 0 also grants write access to the configuration registers. 8.1.1 Off mode The ASL2500SHN switches to off mode, if the input voltage drops below the power-on detection threshold (Vth(det)pon) or the EN pin is low. The SPI interface and output are turned off when the ASL2500SHN is in the Off mode. 8.1.2 Configuration mode The ASL2500SHN switches from off mode to configuration mode, as soon the input voltage is above the power-on detection threshold (Vth(det)pon) and pin EN is high. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 6 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter The configuration registers can be set when the ASL2500SHN is in the Configuration mode. 8.1.3 Operation mode The ASL2500SHN switches from configuration mode to operation mode, as soon as the configuration done bit is set. Once the bit is set, the configuration registers are locked and cannot be changed. In operation mode, the output is available as configured via the SPI interface. Setting the bits Vout1en or Vout2en, starts up VGG. Once VGG is in regulation (signaled by bit VGG_ok), the output voltages Vout1 and Vout2 are turned on accordingly. When the converters are on, the battery monitoring functionality is available. 8.1.4 Fail silent mode The ASL2500SHN switches from Operation mode to Fail silent mode, when the junction temperature exceeds the over temperature shutdown threshold or a VGG error is detected. It will also switch modes when the input voltage is below the under voltage detection threshold or above the over voltage detection threshold. In Fail silent mode, all outputs are turned off and only the SPI interface remains operational. 8.2 Boost converter configuration The ASL2500SHN is an automatic boost converter IC delivering constant DC-to-DC voltage to a load. It has a fixed frequency current-mode control for an enhanced stable operation. The ASL2500SHN offers two phases. Each phase consists of a coil, a resistor, a MOSFET and a diode as shown in Figure 4. Lx Dx Voutx Mx Gx FBx SNHx Rx SNLx aaa-018173 Fig 4. Phase of the boost converter with IC and application connections To allow a flexible use of the ASL2500SHN, the configuration is based on virtual phases. These phases are then mapped to a real, physical phase according to the physical connections and conditions of the circuitry around the ASL2500SHN as shown in Figure 5. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 7 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter V1_1 V1_2 CONTROL LOOP 1 V1_3 V1_4 FLEXIBLE MAPPING VIA REGISTER SETTINGS V2_1 G1 G2 V2_2 CONTROL LOOP 2 V2_3 V2_4 aaa-018174 Fig 5. Mapping of virtual phases (V1_1 to V2_4) to physical phases (G1 and G2) 8.2.1 Configuration of the virtual phases The ASL2500SHN can generate up to four internal phases for up to two virtual outputs. With the internal phase control enable registers, it can be selected, how many virtual phases are generated for the individual virtual outputs. Table 4. Bit Internal phase control enable for output 1, address 0x0Bh Symbol 7:4 3 EN_P4_1 Description Value Function reserved 0000 reserved; should remain cleared for future use phase 4 enabled 0 1 2 EN_P3_1 phase 3 enabled 0 1 1 EN_P2_1 phase 2 enabled 0 1 0 EN_P1_1 phase 1 enabled 0 1 ASL2500SHN Product data sheet phase 4 is off phase 4 is enabled phase 3 is off phase 3 is enabled phase 2 is off phase 2 is enabled phase 1 is off phase 1 is enabled All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 8 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 5. Bit Internal phase control enable for output 2, address 0x0Ch Symbol 7:4 3 EN_P4_2 Description Value Function reserved 0000 reserved; should remain cleared for future use phase 4 enabled 0 1 2 EN_P3_2 phase 3 enabled 0 1 1 EN_P2_2 phase 2 enabled 0 1 0 EN_P1_2 phase 1 enabled 0 1 phase 4 is off phase 4 is enabled phase 3 is off phase 3 is enabled phase 2 is off phase 2 is enabled phase 1 is off phase 1 is enabled 8.2.2 Association of physical phases to the output voltages Each phase that the ASL2500SHN offers, must be associated to one of the outputs. Multiple combinations are possible here, e.g. all phases to one of the outputs, or 1 phase to one output and 1 phase to another one. Table 6. Bit Gate driver output, address 0x02h Symbol Description Value reserved 0000000 O_G2 association phase 2 0 phase 2 is connected to Vout1 1 phase 2 is connected to Vout2 association phase 1 0 phase 1 is connected to Vout1 1 phase 1 is connected to Vout2 7:2 1 0 O_G1 Function reserved; should remain clear for future use 8.2.3 Association of connected phases to the internal phase generation The physical phase that the ASL2500SHN offers, must be associated to one of the virtual phases of one of the outputs. It is established with the gate driver phase and phase select configuration registers. Table 7. Bit Gate driver phase, address 0x0Fh Symbol 7:2 ASL2500SHN Product data sheet Description Value Function reserved 000000 reserved; should remain clear for future use 1 O_GP2 association phase 2 0 phase 2 is connected to Vout1 1 phase 2 is connected to Vout2 0 O_GP1 association phase 1 0 phase 1 is connected to Vout1 1 phase 1 is connected to Vout2 All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 9 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 8. Bit Phase select configuration, address 0x10h Symbol 7:4 3:2 1:0 Description Value Function reserved 0000 reserved; should remain clear for future use 0x0h routing from phase 1 0x1h routing from phase 2 0x2h routing from phase 3 0x3h routing from phase 4 0x0h routing from phase 1 0x1h routing from phase 2 0x2h routing from phase 3 0x3h routing from phase 4 Phsel2[1:0] phase select gate driver 2 Phsel1[1:0] phase select gate driver 1 8.2.4 Enabling of connected phases The gate driver enable register is used to configure which of the phases is active. Table 9. Bit Gate driver enable, address 0x01h Symbol 7:2 Description Value Function reserved 0000000 reserved; should remain clear for future use 1 EN_G2 phase 2 enabled 0 0 EN_G1 phase 1 enabled 0 1 1 phase 2 is off phase 2 is enabled phase 1 is off phase 1 is enabled 8.2.5 Configuration of the boost converter frequencies The operation frequency of the boost converters can be set with via several SPI registers. To ensure a stable phase delay between the different phases, all timings are derived from the same oscillator. An integer number downscales the internal oscillator frequency for each regulation loop. The slower clock controls the off-time of a phase and the delay from one phase of the regulation loop to the next internal phase. The number of phases determinates finally when the phase is turned on again and so defines the operation frequency of the boost converter. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 10 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter switching frequency phase delay and phase off parameters phase active Ph0 clk COUNTER (DIV N) PHASE GATING COUNTER Ph1 Ph2 Ph3 combined reset rst_n phase_gen_rst config change slope comp clk PHASE CONTROL GENERATOR aaa-017533 Fig 6. Table 10. Phase control generator Clock divider for Vout1, address 0x09h Bit Symbol Description Value Function 7:0 Clkdiv1 [7:0] clock divider for output voltage 1 0x00h clock is not divided ... clock is divided by clkdiv1[7:0]+1 0xFFh clock is divided by 256 Table 11. Clock divider for Vout2, address 0x0Ah Bit Symbol Description Value 7:0 Clkdiv1 [7:0] clock divider for output voltage 2 0x00h clock is not divided ... clock is divided by clkdiv2[7:0]+1 0xFFh clock is divided by 256 Table 12. Phase-off time and phase delay of output 1, address 0x0Dh Bit Symbol Description 7:3 Phdel1 [4:0] delay to next 0x0h phase of output1 ... Phoff1 [2:0] phase-off time of 0x0h output1 ... Value 0x1Fh 2:0 0x7h ASL2500SHN Product data sheet Function Function phase delay is 1 clock period of the divided clock phase delay is Phdel1[4:0]+1 clock period of the divided clock phase delay is 32 clock periods of the divided clock phase-off time is 1 clock period of the divided clock phase-off time is Phoff1[2:0] clock period of the divided clock phase-off time is 7 clock periods of the divided clock All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 11 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 13. Phase-off time and phase delay of output 2, address 0x0Eh Bit Symbol Description Value 7:3 Phdel2 [4:0] delay to next 0x0h phase of output2 ... 0x1Fh 2:0 Phoff2 [2:0] phase-off time of 0x0h output2 ... 0x7h Function phase delay is 1 clock period of the divided clock phase delay is Phdel2[4:0]+1 clock period of the divided clock phase delay is 32 clock periods of the divided clock phase-off time is 1 clock period of the divided clock phase-off time is Phoff2[2:0] clock period of the divided clock phase-off time is 7 clock periods of the divided clock Note: To obtain the best performance of the internal slope compensation, keep the settings of the delay between the phases as close to 32 as possible. 8.2.6 Control loop parameter setting The ASL2500SHN is able to operate with a wide range of external components and offers wide range of operating frequencies. To achieve the maximum performance for each set of operation conditions, set the control loop parameters according to the external components and the operating frequency. Table 14. Loop filter proportional configuration, address 0x11h Bit Symbol 7:4 Prop2[3:0] proportional 0x0h factor output 2 ... Description Value 0xFh 3:0 Prop1[3:0] proportional 0x0h factor output 1 ... 0xFh Table 15. Product data sheet proportional factor output 2 is Prop2[3:0]*0.05+0.05 proportional factor output 2 is 0.8 proportional factor output 1 is 0.05 proportional factor output 1 is Prop1[3:0]*0.05+0.05 proportional factor output 1 is 0.8 Loop filter integral configuration, address 0x12h Bit Symbol Description Value Function 7:4 Integ2[3:0] integral factor output 2 0x0h integral factor output 2 is 0.005 ... integral factor output 2 is Integ2[3:0]*0.005+0.005 0xFh integral factor output 2 is 0.08 0x0h integral factor output 1 is 0.005 ... integral factor output 1 is Integ1[3:0]*0.005+0.005 0xFh integral factor output 1 is 0.08 3:0 ASL2500SHN Function proportional factor output 2 is 0.05 Integ1[3:0] integral factor output 1 All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 12 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 16. Slope compensation configuration, address 0x13h Bit Symbol Description Value Function 7:4 Slpcmp2[3:0] slope compensation factor output 2 0x0h slope compensation factor output 2 = 112 k 0x1h slope compensation factor output 2 = 84 k 0x2h slope compensation factor output 2 = 70 k 0x4h slope compensation factor output 2 = 56 k 0x8h slope compensation factor output 2 = 28 k 3:0 Slpcmp1[3:0] Table 17. Bit slope compensation factor output 1 0x0h slope compensation factor output 1 = 112 k 0x1h slope compensation factor output 1 = 84 k 0x2h slope compensation factor output 1 = 70 k 0x4h slope compensation factor output 1 = 56 k 0x8h slope compensation factor output 1 = 28 k Current sense slope resistor configuration, address 0x14h Symbol Description Value Function Slpr2[1:0] slope resistor 0x0h configuration 0x1h for gate driver 2 0x2h 2'b10 - 1000  0x3h 2'b11 - 1500  7:4 3:2 1:0 Slpr1[1:0] 2'b00 - 250  2'b01 - 500  2'b00 - 250  slope resistor 0x0h configuration 0x1h for gate driver 1 0x2h 2'b10 - 1000  0x3h 2'b11 - 1500  2'b01 - 500  8.3 Output voltage programmability The ASL2500SHN provides the possibility to program the output voltage and output overvoltage protection of the output via the SPI interface. 8.3.1 Output voltage target programming The target output voltage can be programmed via the Output voltage registers. As the ASL2500SHN is a boost converter, the output voltage cannot be lower than the supply voltage minus the drop of the converter diode (Dx in Figure 4). Table 18. ASL2500SHN Product data sheet Output voltage 1 register, address 0x03h Bit Symbol Description Value Function 7:0 V_Vout_1[7:0] target voltage output 1 0x00h output 1 is turned off ... target voltage output 1 = 0.3606 * V_Vout_1[7:0] 0xFFh maximum target output voltage = 90 V All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 13 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 19. Output voltage 2 register, address 0x04h Bit Symbol Description Value Function 7:0 V_Vout_2[7:0] target voltage output 2 0x00h output 2 is turned off ... target voltage output 2 = 0.3606 * V_Vout_2[7:0] 0xFFh maximum target output voltage = 90 V 8.3.2 Output overvoltage protection programming Due to fast changes in the supply or the output, it is possible that the output voltage is disturbed. To avoid high voltages that may result into damage of attached components, the ASL2500SHN offers a programmable overvoltage protection threshold. Once the output voltage is above this threshold, the gate pin of the output stops toggling. It results in a halt of the energy delivery to the output. Once the output voltage recovers and is below the threshold again, the gate pin starts toggling again. The regulation loop regulates the output back to the target value. For stable operation of the device, the limit voltage output register should be programmed around 5 V higher than the output voltage registers. Table 20. Limit voltage output 1 register, address 0x05h Bit Symbol Description Value Function 7:0 Vmax_Vout_1 [7:0] limit voltage output 1 0x00h output 1 is turned off ... target voltage output 1 = 0.3606 * Vmax_Vout_1[7:0] 0xFFh maximum output over voltage protection output 1 = 90 V Table 21. Limit voltage output 2 register, address 0x06h Bit Symbol Description Value Function 7:0 Vmax_Vout_2 [7:0] limit voltage output 2 0x00h output 2 is turned off ... target voltage output 2 = 0.3606 * Vmax_Vout_2[7:0] 0xFFh maximum output over voltage protection output 2 = 90 V 8.4 Coil peak current limitation The ASL2500SHN offers a function to limit peak current inside the coil and therefore to limit the input current for the system. Furthermore this functionality can be used to avoid magnetic saturation of the coils. It also allows some soft start feature to be realized with this function. With the Max phase current Vout1 register, the maximum peak current for the phase can be configured. Once the voltage between pins SNSLx and SNSHx reaches this level, the gate will be turned off until the next switching cycle. To avoid sub harmonic oscillations when the coil peak current limitation is becoming active, the slope compensation remains active. It reduces the coil peak current towards the end of the switching cycle to ensure stable operation of the system. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 14 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter In order to avoid that this function interferes with the normal regulation, the limit should be placed well above the maximum expected current. Table 22. Maximum phase current Vout1 register, address 0x07h Bit Symbol Description Value Function 7:0 I_max[7:0] coil current 0x00h limitation for ... phases assigned to 0x80 Vout1 ... no current allowed maximum peak current = (I_max_per_phase_Vout1 [7:0] * 1.8 V / 256 - 0.24 V) / Rsense max allowed setting = (128/255*1.8V-0.24) V / Rsense not allowed 0xFFh not allowed Table 23. Maximum phase current Vout2 register, address 0x08h Bit Symbol Description Value Function 7:0 I_max[7:0] coil current 0x00h limitation for ... phases assigned to 0x80 Vout2 ... no current allowed maximum peak current = (I_max_per_phase_Vout2 [7:0] * 1.8 V / 256 - 0.24 V) / Rsense max allowed setting = (128/255*1.8V-0.24) V / Rsense not allowed 0xFFh not allowed 8.5 Enabling the output voltage The ASL2500SHN provides two independent output voltages. In operation mode, the output voltages are turned on with the bit Vout1en and Vout2en. As soon as one of the outputs is turned on, the VGG voltage regulator is turned on. After tVGG_startup the gate drivers start switching, provided the bit VGG_ok is set. Table 24. Bit Symbol Description Value Function 7:4 reserved 3 2 1 0 ASL2500SHN Product data sheet Function control register, address 0x00h 0000 reserved; should remain cleared for future use Cnt_CSB count chip select time 0 chip select low count feature is disabled 1 chip select low count feature is enabled Vout2en enable output 2 0 output 2 is turned off 1 output 2 is turned on when the device is in operation mode enable output 1 0 output 1 is turned off 1 output 1 is turned on when the device is in operation mode Vout1en Cfg_dn configuration 0 done bit 1 device is in configuration mode - no configuration lock device is in operation mode - configuration lock is active All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 15 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 8.6 Frequency trimming To ensure the ASL2500SHN operates inside the specified oscillator frequency range, it is mandatory to adjust the internal oscillator frequency of the device. To measure the actual internal frequency, the device is measuring the time that the CSB pin is low during an SPI transfer. This time information can be used to adjust the oscillator frequency of the device. The recommended procedure for the time adjustment is shown in Figure 7. Frequency trimming start Enable CSB low count feature (CNT_CSB = 1) Disable CSB low count feature (CNT_CSB = 0) With defined, CSB LOW TIME Adjust frequency trimming register Read CSB count registers no COUNT as expected? remark: count = CSB LOW TIME 1 yes fosc_trimmed End frequency trimming Fig 7. (± 1 %) aaa-017534 Frequency trimming flow At the start of the sequence, the CSB low count feature is activated. It is done by setting the Cnt_CSB Bit high in the Frequency trimming control register (Bit 3; register 0x00h). The device now measures the time with its internal time domain each time the CSB pin is low. It makes this information available in the CSB count registers. To allow an exact stable reading, set the Cnt_CSB Bit low again with an accurately known CSB low time. Setting the bit low freezes the count registers. They store the last value, which in this case is the command that set the Cnt_CSB bit low. The CSB count registers contain the count of the CSB low time of the last SPI command the CSB low count feature was enabled. CSB count register 1 contains the bits 7 to 0 of the counter, while the CSB count register 2 contains the bits 15:8. Table 25. ASL2500SHN Product data sheet CSB count register 1, address 0x41h Bit Symbol Description Value Function 7:0 CSB_cnt[7:0] CSB count low ... count value (bits 7:0) All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 16 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 26. CSB count register 2, address 0x42h Bit Symbol Description Value 7:0 CSB_cnt[15:8] CSB count high ... Function count value (bits 15:8) The count, the CSB count register returns, should correspond to the real time of the CSB low time. 1 count should correspond with 1/ fosc_trimmed (see Table 44). When the count that the CSB count registers return, deviates from the applied CSB low time, the device internal timing must be adjusted by modifying the frequency trimming register. Table 27. Bit 7:6 5:0 Frequency trimming register, address 0x1Ch Symbol Description Value reserved Function not allowed Freq_trim[5:0] frequency trim bits 010001 default frequency 33.33 % 010011 default frequency 30.56 % 010101 default frequency 27.78 % 010111 default frequency 25.00 % 011001 default frequency 22.22 % 011011 default frequency 19.44 % 011101 default frequency 16.67 % 011111 default frequency 13.89 % 000001 default frequency 11.11 % 000011 default frequency 8.33 % 000101 default frequency 5.56 % 000111 default frequency 2.78 % 001001 default frequency 001011 default frequency + 2.78 % 001101 default frequency + 5.56 % 001111 default frequency + 8.33 % 110001 default frequency + 11.11 % 110011 default frequency + 13.89 % 110101 default frequency + 16.67 % 110111 default frequency + 19.44 % 111001 default frequency + 22.22 % 111011 default frequency + 25.00 % 111101 default frequency + 27.78 % 111111 default frequency + 30.56 % 100001 default frequency + 33.33 % 100011 default frequency + 36.11 % others not allowed To ensure that the adjustment had the desired effect, restart the procedure and check the count with the new settings in the frequency trimming register. When the device internal time matches the applied CSB low time, no further adjustment is needed and the trimming procedure is finished. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 17 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 8.7 Gate voltage supply The ASL2500SHN has an integrated linear regulator to generate the supply voltage of the gate drivers, which is internally connected to the pin VGG. The voltage generated by the linear regulator can be set via the VGG control register. Table 28. VGG control register, address 0x15h Bit Symbol Description Value Function 7:0 VGG[7:0] supply voltage for gate driver 0x00h not allowed ... not allowed 0x5Dh maximum output voltage = 10.04 V ... (255- VGG[7:0]) * 62 mV 0xB7h minimum output voltage = 4.46 V ... not allowed 0xFFh not allowed The actual value of VGG can deviate from the target setting due to the tolerances of the VGG regulation loop (see Vo(reg)acc in Table 43). When a setting between 0x00h and 0x5Dh is used, the resulting gate driver target voltage exceeds the limiting values of the IC. The limiting values of the VGG pin can also be violated with target settings of 0xA6h to 0x5Dh due to these tolerances. A violation of the limiting values with the actual VGG voltage must be avoided. To ensure that only allowed settings are used for the gate driver target voltage, an immediate read back of the programmed value is required after setting the registers. If a setting between 0xFFh and 0xB7h is used, the device may not start up VGG. If the device operates, parameters of VGG are not guaranteed. 8.7.1 Gate voltage supply diagnostics The diagnostic options for the gate voltage supply are: • VGG available. Details can be found in Section 8.10 • VGG protection active. Details can be found in Section 8.10 8.8 Supply voltage monitoring The ASL2500SHN is continuously measuring the voltage at pin Vbat, when at least one of the outputs is enabled and bit VGG_ok is set. It allows the system to monitor the supply voltage without additional external components. It also offers the option to put an automatic under- and/or overvoltage protection in place. Note: The VIN_UV and VIN_OV bits in the status register use the battery voltage measurement. Consequently the VIN_UV and VIN_OV bits are only reliable when at least one output is enabled. 8.8.1 Battery voltage measurement The ASL2500SHN continuously measures the voltage at pin Vbat. The measurement result is available in the battery voltage register when the output is enabled. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 18 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 29. Battery voltage register, address 0x45h Bit Symbol Description Value Function 7:0 V_VBAT[7:0] Battery voltage 0x00h battery voltage = 0 V ... battery voltage = 0.3606 * V_VBAT[7:0] 0xFFh maximum measurable battery voltage = 90 V 8.8.2 Undervoltage detection The ASL2500SHN offers a variable undervoltage detection threshold. When the supply voltage drops below this threshold, the undervoltage detect bit is set, and fail silent mode is entered. The gate pin stops toggling and no more power is delivered to the output. Table 30. Undervoltage threshold register, address 0x1Bh Bit Symbol Description Value Function 7:0 V_VIN_UV[7:0] undervoltage detection threshold 0x00h undervoltage detection threshold = 0 V ... under voltage detection threshold = 0.3606 * V_VIN_UV[7:0 0xFFh maximum undervoltage detection threshold = 90 V 8.8.3 Overvoltage detection The ASL2500SHN offers a variable overvoltage detection threshold. When the supply voltage rises above this threshold, the overvoltage detect bit is set, and fail silent mode is entered. The gate pin stops toggling and no more power is delivered to the output. Table 31. Overvoltage threshold register, address 0x1Ah Bit Symbol Description 7:0 V_VIN_OV[7:0] overvoltage detection threshold Value Function 0x00h overvoltage detection threshold = 0 V ... overvoltage detection threshold = 0.3606 * V_VIN_OV[7:0 0xFFh maximum overvoltage detection threshold = 90 V 8.9 Junction temperature information The ASL2500SHN provides a measurement of the IC junction temperature. The measurement information is available in the junction temperature register. Table 32. ASL2500SHN Product data sheet Junction temperature register, address 0x46h Bit Symbol Description Value Function 7:0 T_junction[7:0] junction temperature ... device junction temperature below 40 C 0x18h device junction temperature = 40 C ... device junction temperature = T_junction[7:0] * (215/106) C  88 C 0x82h device junction temperature  175 C All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 19 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 8.10 Diagnostic information The diagnostic register contains useful information for diagnostic purposes. Details for each bit can be found in the following subchapters. Table 33. Diagnostic register, address 0x5Fh Bit Symbol 7 6 5 Description Vout1_ok Vout1 regulated Vout2_ok Vout2 regulated VGG_ok Value Function 0 Vout1 is deviating from the target value 1 Vout1 is regulated to the target value 0 Vout2 is deviating from the target value 1 Vout2 is regulated to the target value VGG regulation OK 0 1 4 3 2 1 0 Tj_err VIN_UV VIN_OV SPI_err VGG_err VGG is not available VGG is available device temperature 0 is too high 1 device temperature above Tsd(otp) VIN under voltage 0 no under voltage at VIN detected 1 under voltage at VIN detected 0 no over voltage at VIN detected 1 over voltage at VIN detected 0 last SPI command was executed correctly 1 last SPI command was erroneous and has been discarded 0 VGG overload protection not active 1 VGG overload protection has turned on and VGG is deactivated VIN over voltage SPI error VGG error device temperature below Tsd(otp) 8.10.1 Bit VIN_OV The bit VIN_OV depends on the battery monitoring functionality as described in Section 8.8. It indicates that the device has detected an overvoltage condition and entered fail silent mode. A write access to the diagnostic register or when the Off mode has been entered, clears the bit. Independent of the clearing of the bit, the device stays in fail silent mode. 8.10.2 Bit VIN_UV The bit VIN_UV depends on the battery monitoring functionality as described in Section 8.8. It indicates that the device has detected an undervoltage condition and entered fail silent mode. A write access to the diagnostic register or when the Off mode has been entered, clears the bit. Independent of the clearing of the bit, the device stays in fail silent mode. 8.10.3 Bit SPI_err The device is evaluating all SPI accesses to the device for the correctness of the commands. When the command is not allowed, the SPI_err bit is set. A write access to the diagnostic register or when the Off mode is entered, clears the bit. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 20 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 8.10.4 Bit Tj_err The bit Tj_err indicates that the junction temperature has exceeded the maximum allowable temperature, and the device has entered Fail silent mode. A write access to the diagnostic register, or once Off mode has been entered, clears the bit. The device stays in Fail silent mode irrespective of the clearing of the bit. After leaving the OFF mode (at IC start-up), it is possible that bit Tj_err is set. To avoid wrong diagnostics, clear the diagnostic register before it is evaluated. 8.10.5 Bit VGG_err Bit VGG_err is set when the gate driver does not reach the VGG_ok _window (when VVGG is within range) within the regulator voltage start-up error time. Once bit VGG_err is set, it indicates that an error on the gate driver has been detected and the device has entered Fail silent mode. A write access to the diagnostic register, or once Off mode has been entered, clears the bit. The device stays in Fail silent mode irrespective of the clearing of the bit. 8.10.6 Bit VGG_ok The bit VGG_ok indicates that the gate driver is regulated to the target voltage and allows the gate drivers to drive the gate driver pins. If the gate driver is outside the VGG_ok window after tstartup, and VVGG is within range, the device clears VGG_ok bit and enters Fail silent mode. 8.10.7 Bit Vout1_ok and Vout2_ok The bits Vout1_ok and Vout2_ok indicate whether the output voltage is regulated to the target value or deviating from the target value. The bits are set as soon as the corresponding output is within the Vout_ok window (when VO is within the range) for more than tfltr(ov). The bits are cleared when the corresponding output is outside the Vout_ok window for more than tfltr(ov). 8.11 SPI The ASL2500SHN uses an SPI interface to communicate with an external microcontroller. The SPI interface can be used for setting the LEDs current, reading and writing the control register. 8.11.1 Introduction The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave operations. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing the application to read back the registers without changing the register content. The SPI uses four interface signals for synchronization and data transfer: • • • • ASL2500SHN Product data sheet CSB - SPI chip select; active LOW SCLK - SPI clock - default level is LOW due to low-power concept SDI - SPI data input SDO - SPI data output - floating when pin CSB is HIGH All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 21 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Bit sampling is performed on the falling clock edge and data is shifted on the rising clock edge as illustrated in Figure 8. SCLK CSB SDI b15 MSB b14 b13 b12 b11 b10 b9 b3 b2 b1 b0 SDO b15 MSB b14 b13 b12 b11 b10 b9 b3 b2 b1 b0 Sampling Edge Driving Edge aaa-016623 Format: * Steady state SCLK = 0 * Data driving edge = positive edge * Data sampling edge = negative edge Fig 8. SPI timing protocol The data bits of the ASL2500SHN are arranged in registers of one-byte length. Each register is assigned to a 7-bit address. For writing into a register, 2 bytes must be sent to the LED driver. The first byte is an identifier byte that consists of the 7-bit address and one read-only bit. For writing, the read-only bit must be set to 0. The second byte is the data that is written into the register. So an SPI access consists of at least 16 bit. Figure 9 together with Table 34 and Table 35 demonstrate the SPI frame format. R/W Address b15 b14 b13 b12 b11 b10 b9 Table 34. b8 b7 b6 b5 b15 = MSB = first transmitted bit R/W Fig 9. Data b4 b3 b2 b1 b0 aaa-016624 SPI frame format SPI frame format for a transition to the device Bit Symbol Description Value Function 15 b15 R/W bits 0 write access 1 read access 14:8 b14:8 address bits ... selected address 7:0 data bits ... transmitted data b7:0 ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 22 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 35. Bit SPI frame format for a transition from the device Symbol Description Value Function[1] 8:15 b8:15 diagnostic register ... content of diagnostic register 7:0 data bits ... when previous command was a valid read command, content of the register that is supposed to be read ... when previous command was a valid write command, new content of the register that was supposed to be written [1] b7:0 The first SPI command after leaving the Off mode, will return 0x00h. The master initiates the command sequence. The sequence begins with CSB pin pulled low and lasts until it is asserted high. The ASL2500SHN also tolerates SPI accesses with a multiple of 16 bits. It allows a daisy chain configuration of the SPI. MOSI SDI CSB CSB SCLK SCLK ASL2500SHN SDO SOMI µC SDI CSB SCLK ASLxxxxSHN SDO SDI CSB SCLK ASLxxxxSHN SDO aaa-018175 Fig 10. Daisy chain configuration ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 23 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter MOSI SDI CSB1 CSB SCLK SCLK ASL2500SHN SDO SOMI CSB2 µC CSB3 SDI CSB SCLK ASLxxxxSHN SDO SDI CSB SCLK ASLxxxxSHN SDO aaa-018176 Fig 11. Physical parallel slave connection During the SPI data transfer, the identifier byte and the actual content of the addressed registers is returned via the SDO pin. The same happens for pure read accesses. Here the read-only bit must be set to 1. The content of the data bytes that are transmitted to the ASL2500SHN is ignored. The ASL2500SHN monitors the number of data bits that are transmitted. If the number is not 16, or a multiple of 16, then a write access is ignored and the SPI error indication bit is set. 8.11.2 Typical use case illustration (Write/Read) Consider a daisy chain scheme with one master connected to 4 slaves in Daisy chain fashion. The following commands are performed during one sequence (first sequence). • • • • ASL2500SHN Product data sheet Write data 0xFF to register 0x1A Slave 1 Read from register 0x02 of Slave 2 Write data 0xAF to register 0x2F of Slave 3 Read from register 0x44 of Slave 4 All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 24 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 1st Sequence 2nd Sequence CSB SCLK 1 x 16 SCLK’s 2 x 16 SCLK’s 3 x 16 SCLK’s 4 x 16 SCLK’s 1 x 16 SCLK’s 2 x 16 SCLK’s 3 x 16 SCLK’s Next command for Slave4 Next command for Slave3 Next command for Slave2 Next command for Slave1 4 x 16 SCLK’s Master SDO/ Slave1 SDI b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF b15 = 1 b14-b8 = 0x2 b7-b0 = xx Slave 1 b15 = 0 b14-b8 = 0x1A b7-b0 = 0xFF Slave1 SDO/ Slave2 SDI XXX b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF Slave 2 b15 = 1 b14-b8 = 0x2 b7-b0 = xx b15-b8 = Default read reg of slave1 b7-b0 = xx Next command for Slave4 Next command for Slave3 Next command for Slave2 Slave2 SDO/ Slave3 SDI XXX XXX b15 = 1 b14-b8 = 0x44 b7-b0 = xx Slave 3 b15 = 0 b14-b8 = 0x2F b7-b0 = 0xAF b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave2 b15-b8 = Default read reg of slave1 b7-b0 = xx Next command for Slave4 Next command for Slave3 Slave3 SDO/ Slave4 SDI XXX XXX XXX Slave 4 b15 = 1 b14-b8 = 0x44 b7-b0 = xx b15-b8 = Default read reg of slave3 b7-b0 = xx b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave2 b15-b8 = Default read reg of slave1 b7-b0 = xx Next command for Slave4 Slave4 SDO/ Master SDI XXX XXX XXX XXX b15-b8 = Default read reg of slave4 b7-b0 = Data from 0x44 of Slave4 b15-b8 = Default read reg of slave3 b7-b0 = xx b15-b8 = Default read reg of slave2 b7-b0 = Data from 0x2 of Slave4 b15-b8 = Default read reg of slave1 b7-b0 = xx Current sequence Command decoded by Slave Response from previous sequence aaa-016627 Fig 12. SPI frame format 8.11.3 Diagnostics for the SPI interface The device is evaluating all SPI access to the device for the correctness of the commands. When the command is not allowed, the SPI_err bit is set. The conditions that are considered as erratic accesses are: • • • • SPI write is attempted to a read-only location or reserved location SPI write is attempted during operation to a configuration register SPI read is attempted from a reserved location SPI command does not consist of a multiple of 16 clock counts If an SPI access is considered to be erratic, no modifications to a SPI register are made. The access after the erratic SPI command returns the diagnostic register and zero in the data field. For details about the SPI_err bit, see Section 8.10.3. 8.11.4 Register map The addressable register space amounts to 128 registers from 0x00 to 0x7F. They are separated in two groups as shown in Table 36. The register mapping is shown in Table 37, Table 38, Table 39 and Table 40. The functional description of each bit can be found in the dedicated chapter. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 25 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 36. 8.11.4.1 Register space grouping Address range Description Content 0x00 to 0x1F control registers control register information 0x20 to 0x7F diagnostic registers diagnostic information Control registers Table 37 provides an overview of the control registers and their reset value. Table 37. Control register group overview Address Name Reset value 7 0x00h function control 0x00h - 6 - - - 0x01h gate driver enable 0x00h - - - - 0x03h target voltage output 1 0x00h V_Vout_1[7:0] 0x04h target voltage output 2 0x00h V_Vout_2[7:0] 0x05h limit voltage output 1 0x00h Vmax_Vout_1[7:0] 0x06h limit voltage output 2 0x00h Vmax_Vout_2[7:0] 0x07h maximum phase current Vout1 0x46h I_max_per_phase_Vout1[7:0] 0x08h maximum phase current Vout2 0x46h I_max_per_phase_Vout2[7:0] 0x1Ch frequency trimming register 0x09h - 5 4 3 2 1 Cnt_CSB Vout2en[1] - - - 0 Vout1en[1] Cfg_dn EN_G2[2] EN_G1[2] Freq_trim[5:0] [1] Bit is locked with bit Cfg_dn is high. When bit Cfg_dn is low, bits can be changed. Read is always possible. [2] Individual gate drivers that are enabled when Cfg_dn and VGG_ok are set high, can be turned on and off during operation of the system. Gate drivers, disabled when bits Cfg_dn and VGG_ok are set high, remain off, even when the gate enable bits are set high later. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 26 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 8.11.4.2 Configuration registers Table 38 provides an overview of the configuration registers. The configuration registers inside the control block can only be written in configuration mode. In the other modes, this register can only be read. Table 38. Configuration register group overview Address Name Reset value 0x02h 0x00h gate driver output 7 6 - 5 - 4 - 3 2 - - 1 - 0 O_G2 O_G1 0x09h clock divider for output 1 0x0Fh Clkdiv1[7:0] 0x0Ah clock divider for output 2 0x0Fh Clkdiv2[7:0] 0x0Bh internal phases output 1 0x0Fh - - - - EN_P4_1 EN_P3_1 EN_P2_1 EN_P1_1 0x0Ch internal phases output 2 0x0Fh - - - - EN_P4_2 EN_P3_2 EN_P2_2 EN_P1_2 0x0Dh phase off and delay output 1 0x39h Phdel1 Phoff1 0x0Eh phase off and delay output 2 0x39h Phdel2 Phoff2 0x0Fh gate driver phase 0x00h 0x10h phase selection configuration 0xE4h 0x11h loop filter proportional configuration 0x00h Prop2[3:0] Prop1[3:0] 0x12h loop filter integral configuration 0x00h Integ2[3:0] Integ1[3:0] 0x13h slope compensation configuration 0x88h Slpcmp2[3:0] Slpcmp1[3:0] 0x14h current sense slope resistor configuration 0x00h 0x15h VGG control 0xFFh VGG[7:0] 0x1Ah over voltage detection threshold 0xFFh V_VIN_OV[7:0] 0x1Bh under voltage detection threshold 0x00h V_VIN_UV[7:0] ASL2500SHN Product data sheet - - - - - - - - O_GP2 Phsel2 - Slpr2[1:0] All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 - O_GP1 Phsel1 Slpr1[1:0] © NXP Semiconductors N.V. 2017. All rights reserved. 27 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 8.11.4.3 Internal registers The ASL2500SHN uses the SPI registers to control some internal functions. In order to avoid any unintended behavior of the device, do not modify these registers but leave them all at their default value. Table 39. Internal register overview Address Name Reset value 0x19h Internal 1 0x25h 0x26h 7 6 5 4 3 2 1 0 0x82h - - - - - - - - Internal 2 0x27h - - - - - - - - Internal 3 0x3Bh - - - - - - - - 0x2Fh Internal 4 0xE8h - - - - - - - - 0x30h Internal 5 0x09h - - - - - - - - 8.11.4.4 Diagnostic registers The ASL2500SHN provides diagnostic data via some SPI registers. These registers are read only, but error bits can be cleared via a write access to the register. Table 40. Diagnostic register group overview Address Name 7 6 5 4 3 0x41h CSB count low CSB_cnt[7:0] 0x42h CSB count high CSB_cnt[15:8] 0x45h battery voltage V_VBAT[7:0] 0x46h junction temperature 0x5Fh diagnostic Register ASL2500SHN Product data sheet 2 1 0 T_junction[7:0] Vout1_ok Vout2_ok VGG_ok Tj_err VIN_UV All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 VIN_OV SPI_err VGG_err © NXP Semiconductors N.V. 2017. All rights reserved. 28 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 9. Limiting values Table 41. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VBAT battery supply voltage EN = low 0.3 +60 V VVCC voltage on pin VCC VGND ground supply voltage VFBx 0.3 +40 V 0.3 +5.5 V voltage between ground pins 0.6 +0.6 V voltage on feedback pins FB1 and FB2 0.3 +90 V VO output voltage programmed target voltage according to registers 0x03h and 0x04h 10 +80 V VI(dig) digital input voltage voltage on digital pins SDO, SDI, CSB, SCLK and EN 0.3 +5.5 V VVGG voltage on pin VGG 0.3 +10 V Vsense sense voltage voltage on sense pins SNH1, SNL1, SNH2 and SNL2 0.3 +0.3 V VGx voltage on gate pins G1 and G2 0.3 +10 V Vic voltage on internally connected pins i.c. 0.3 +1.8 V Tj junction temperature 40 +175 °C Tstg storage temperature 55 +175 °C VESD electrostatic discharge voltage at any pin 2 +2 kV at pin VBAT with 100 nF at pin 6 +6 kV 500 +500 V EN = high HBM[1] CDM[2] at any pin [1] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k) [2] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF). 10. Thermal characteristics Table 42. Symbol Parameter thermal resistance Rth [1] Thermal characteristics Conditions HVQFN32 package JEDEC[1] Typ Unit 37 K/W According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 29 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 11. Static characteristics Table 43. Static characteristics Min and Max values are specified for the following conditions: VBAT = 5.5 V to 40 V, VEN = 4.5 V to 5.5 V, VVCC = 4.5 V to 5.5 V and Tj = 40 °C to +175 °C[1]. All voltages are defined with respect to ground, positive currents flow into the IC. Typical values are given at VVIN = 40 V. VEN = 5 V, VVCC = 5 V and Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit operating; no load on VGG; Gate pins low; one phase; one output 5 13 - mA operating; no load on VGG; Gate pins low - 20 - mA EN = low - - 5 A - - 4.5 V Supply pin Vbat IDD supply current Ioff off-state current Vth(det)pon power-on detection threshold voltage Supply pin VCC IVCC supply current on pin VCC operating - - 250 A current on pin EN operating - - 2 mA Vout1: operating accuracy 1 0.03  Vout1  0.721 - +0.03  Vout1 + 0.721 V Vout2: operating accuracy 2 0.03  Vout2  0.721 - +0.03  Vout2 + 0.721 V bit Vout1_ok/Vout2_ok is set when VO is within the range regarding the target value 5.4 - +2.4 V VBAT  VVGG + Vdo(reg)VGG 4.46 - 10.04 V bit VGG_ok is set when VVGG is within the range regarding the target value 2.4 - +2.4 V Ireg  50 mA; regulator in saturation - 0.5 1.0 V Ireg  160 mA; regulator in saturation - 1.6 3.2 V 25 C to Tj(max) 5 - +5 % 40 C to +25 C 7 - +5 % Pin EN IEN Output voltage VO(acc) VO output voltage accuracy output voltage Regulated voltage output VVGG Vdo(reg)VGG Vreg(acc)VGG voltage on pin VGG regulator dropout voltage on pin VGG regulator voltage accuracy on pin VGG Serial peripheral interface inputs; pins SDI, SCLK and CSB Vth(sw) switching threshold voltage 0.3  VVCC - 0.7  VVCC V Rpd(int)SCLK internal pull-down resistance on pin SCLK 40 - 80 k Rpd(int)CSB internal pull-down resistance on pin CSB 40 - 80 k Rpd(int)SDI internal pull-down resistance on pin SDI 40 - 80 k ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 30 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 43. Static characteristics …continued Min and Max values are specified for the following conditions: VBAT = 5.5 V to 40 V, VEN = 4.5 V to 5.5 V, VVCC = 4.5 V to 5.5 V and Tj = 40 °C to +175 °C[1]. All voltages are defined with respect to ground, positive currents flow into the IC. Typical values are given at VVIN = 40 V. VEN = 5 V, VVCC = 5 V and Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Serial peripheral interface data output; pin SDO VOH HIGH-level output voltage IOH = 4 mA; VVCC = 4.5 V to 5.5 V VVCC  0.4 - - V VOL LOW-level output voltage IOL = 4 mA; VVCC = 4.5 V to 5.5 V - - 0.4 V ILOZ OFF-state output leakage VCSB = VVCC; VO = 0 V to VVCC current 5 - +5 A 20 - +20 C 150 175 200 C 0.035  VBAT  0.3606 - Temperature protection Tj junction temperature variation Tsd(otp) overtemperature protection shutdown temperature Tj = 130 C Vbat monitoring VBAT [1] battery voltage accuracy accuracy of VBAT measurement 0.035  VBAT  0.3606 V All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. 12. Dynamic characteristics Table 44. Dynamic characteristics Min and Max values are specified for the following conditions: VBAT = 5.5 V to 40 V, VEN = 4.5 V to 5.5 V, VVCC = 4.5 V to 5.5 V and Tj = 40 °C to +175 °C[1]. All voltages are defined with respect to ground, positive currents flow into the IC. Typical values are given at VVIN = 40 V. VEN = 5 V, VVCC = 5 V and Tj = 25 °C unless otherwise specified. Symbol Parameter fDCDC DC-to-DC converter frequency f(DCDC)acc DC-to-DC converter  frequency accuracy fosc oscillator frequency tstartup start-up time Conditions Min Typ Max Unit 125 - 700 kHz operating, trimmed 5 - +5 % internal oscillator, untrimmed 130 - 250 MHz target frequency for trimmed operation - 180 - MHz EN high until SPI is operational - - 150 s - 20:1 - 1 - - ns Serial peripheral interface timing; pins CSB, SCLK, SDI and SDO fclk(int)/fSPI Internal clock frequency to SPI ratio between internal clock and SPI clock clock frequency ratio tcy(clk) clock cycle time 250 tSPILEAD SPI enable lead time 50 tSPILAG SPI enable lag time 50 tclk(H) clock HIGH time 125 tclk(L) clock LOW time 125 tsu(D) data input set-up time 50 th(D) data input hold time 50 tv(Q) data output valid time ASL2500SHN Product data sheet pin SDO; CL = 20 pF All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 - ns - - ns ns - - ns ns - - ns 130 ns © NXP Semiconductors N.V. 2017. All rights reserved. 31 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter Table 44. Dynamic characteristics …continued Min and Max values are specified for the following conditions: VBAT = 5.5 V to 40 V, VEN = 4.5 V to 5.5 V, VVCC = 4.5 V to 5.5 V and Tj = 40 °C to +175 °C[1]. All voltages are defined with respect to ground, positive currents flow into the IC. Typical values are given at VVIN = 40 V. VEN = 5 V, VVCC = 5 V and Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions tWH(S) chip select pulse width HIGH Min Typ 250 - Max Unit ns Gate driver characteristics for pin G1 and pin G2 tch(G) gate charge time 20 % to 80 %; VVGG= 7.5 V; Cgate = 2000 pF - - 30 ns tdch(G) gate discharge time 80 % to 20 %; VVGG= 7.5 V; Cgate = 2000 pF - - 14 ns Regulated voltage terr(startup) start-up error time of VGG; fosc = 180 MHz - 2.5 - ms terr error detection time for VGG during operation; fosc = 180 MHz - 31.5 - s tfltr(ov) output voltage filter time for bit Vout1_ok and Vout2_ok; fosc = 180 MHz - 31.5 - s [1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. CSB tSPILEAD tWH(S) tclk tSPILAG SCLK tclk(H) tclk(L) tSU(D) th(D) b15 MSB SDI b0 LSB tv(Q) SDO FLOATING b15 MSB b0 LSB FLOATING aaa-017537 Fig 13. SPI timing diagram ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 32 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 13. Application information Figure 14 provides an example for the ASL2500SHN in a typical 2-phase boost converter IC with 1 output voltage. D8 battery C1 C2 L1 D1 VIN VGG G1 C16 M1 VGG C8 G1 SNH1 C15 BS1 R1 M5 L5 R5 C5 LED1 C12 SNL1 LX1 D9 PWM1 C18 G2 D10 PWM2 D2 C9 M2 RL1 PWM3 D11 D5 SNH2 VCC EN RH1 L2 VBAT ASL2500SHN R2 SNL2 CSB G2 SDI SDO FB1 SCLK FB2 BS2 ASLxxxxSHN M6 L6 R6 C6 LED2 C13 LX2 D12 GND VCC EN RH2 D13 RL2 D14 CSB D6 SDI SDO SCLK G3 BS3 M7 L7 C7 R7 LED3 C14 LX3 C20 VCC VBAT RSTN C19 GND TJA1028 LIN LIN EN TXD RXD D15 VCC EN_1 RSTN EN_2 EN CSB1 TXD CSB2 D16 GND RL3 D17 D7 SDI RXD GND RH3 µC SDO SCLK PWM1 PWM2 PWM3 aaa-018177 Fig 14. ASL2500SHN, configured as two-phase, single-output boost converter 14. Test information 14.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 Rev-H - Failure mechanism-based stress test qualification for integrated circuits, and is suitable for use in automotive applications. ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 33 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 15. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-12 terminal 1 index area E A A1 c detail X e1 1/2 e e 9 16 C C A B C v w b y1 C y L 8 17 e e2 Eh 1/2 e 1 24 terminal 1 index area 32 k 25 X Dh 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 e2 0.2 5.1 5.0 4.9 3.1 3.0 2.9 5.1 5.0 4.9 3.1 3.0 2.9 0.5 3.5 3.5 k L v 0.1 0.5 0.50 0.44 0.30 w y y1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC SOT617-12 JEDEC JEITA sot617-12_po European projection Issue date 13-10-14 13-11-05 MO-220 Fig 15. Package outline HVQFN32 ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 34 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 16. Revision history Table 45. Revision history Document ID Release date Data sheet status Change notice Supersedes ASL2500SHN v.3 20171026 Product data sheet - ASL2500SHN v.2 Modifications: ASL2500SHN v.2 Modifications: ASL2500SHN v.1 ASL2500SHN Product data sheet • • • • • Section 8.7: clarified exceeding of limiting values Formula for voltage conversion updated Table 43: values of output voltage accuracy updated Table 43: values of regulator voltage accuracy on pin VGG updated Table 44: data output valid time updated 20160413 • • Product data sheet - ASL2500SHN v.1 Minor corrections made to Figure 3 “State diagram” on page 6. Text has been corrected and aligned with the ASLxxxxSHN series of data sheets. 20150925 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 - © NXP Semiconductors N.V. 2017. All rights reserved. 35 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. ASL2500SHN Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 36 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 37 of 39 ASL2500SHN NXP Semiconductors Two phase boost converter 19. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description[1] . . . . . . . . . . . . . . . . . . . . . . . .4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . .6 Internal phase control enable for output 1, address 0x0Bh . . . . . . . . . . . . . . . . . . . . . . . . . .8 Internal phase control enable for output 2, address 0x0Ch . . . . . . . . . . . . . . . . . . . . . . . . .9 Gate driver output, address 0x02h . . . . . . . . . . .9 Gate driver phase, address 0x0Fh . . . . . . . . . . .9 Phase select configuration, address 0x10h . . .10 Gate driver enable, address 0x01h . . . . . . . . .10 Clock divider for Vout1, address 0x09h . . . . . . 11 Clock divider for Vout2, address 0x0Ah . . . . . . 11 Phase-off time and phase delay of output 1, address 0x0Dh . . . . . . . . . . . . . . . . . . . . . . . . . 11 Phase-off time and phase delay of output 2, address 0x0Eh . . . . . . . . . . . . . . . . . . . . . . . . .12 Loop filter proportional configuration, address 0x11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Loop filter integral configuration, address 0x12h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Slope compensation configuration, address 0x13h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Current sense slope resistor configuration, address 0x14h . . . . . . . . . . . . . . . . . . . . . . . . .13 Output voltage 1 register, address 0x03h . . . . .13 Output voltage 2 register, address 0x04h . . . . .14 Limit voltage output 1 register, address 0x05h .14 Limit voltage output 2 register, address 0x06h .14 Maximum phase current Vout1 register, address 0x07h . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 23. Maximum phase current Vout2 register, address 0x08h . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 24. Function control register, address 0x00h . . . . . 15 Table 25. CSB count register 1, address 0x41h . . . . . . . 16 Table 26. CSB count register 2, address 0x42h . . . . . . . 17 Table 27. Frequency trimming register, address 0x1Ch . 17 Table 28. VGG control register, address 0x15h. . . . . . . . 18 Table 29. Battery voltage register, address 0x45h. . . . . . 18 Table 30. Undervoltage threshold register, address 0x1Bh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 31. Overvoltage threshold register, address 0x1Ah. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 32. Junction temperature register, address 0x46h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 33. Diagnostic register, address 0x5Fh . . . . . . . . . 20 Table 34. SPI frame format for a transition to the device. 22 Table 35. SPI frame format for a transition from the device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 36. Register space grouping . . . . . . . . . . . . . . . . . 26 Table 37. Control register group overview . . . . . . . . . . . . 26 Table 38. Configuration register group overview . . . . . . 27 Table 39. Internal register overview . . . . . . . . . . . . . . . . 28 Table 40. Diagnostic register group overview . . . . . . . . . 28 Table 41. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 42. Thermal characteristics . . . . . . . . . . . . . . . . . . 29 Table 43. Static characteristics . . . . . . . . . . . . . . . . . . . . 30 Table 44. Dynamic characteristics . . . . . . . . . . . . . . . . . 31 Table 45. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 35 20. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4 State diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Phase of the boost converter with IC and application connections . . . . . . . . . . . . . . . . . . . . .7 Mapping of virtual phases (V1_1 to V2_4) to physical phases (G1 and G2) . . . . . . . . . . . . . . . .8 Phase control generator . . . . . . . . . . . . . . . . . . . 11 Frequency trimming flow . . . . . . . . . . . . . . . . . . .16 SPI timing protocol. . . . . . . . . . . . . . . . . . . . . . . .22 SPI frame format . . . . . . . . . . . . . . . . . . . . . . . . .22 Daisy chain configuration. . . . . . . . . . . . . . . . . . .23 Physical parallel slave connection . . . . . . . . . . . .24 SPI frame format . . . . . . . . . . . . . . . . . . . . . . . . .25 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . .32 ASL2500SHN, configured as two-phase, single-output boost converter . . . . . . . . . . . . . . .33 Package outline HVQFN32 . . . . . . . . . . . . . . . . .34 ASL2500SHN Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 26 October 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 38 of 39 NXP Semiconductors ASL2500SHN Two phase boost converter 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.3.1 8.3.2 8.4 8.5 8.6 8.7 8.7.1 8.8 8.8.1 8.8.2 8.8.3 8.9 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.10.5 8.10.6 8.10.7 8.11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6 Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration mode . . . . . . . . . . . . . . . . . . . . . 6 Operation mode . . . . . . . . . . . . . . . . . . . . . . . . 7 Fail silent mode . . . . . . . . . . . . . . . . . . . . . . . . 7 Boost converter configuration . . . . . . . . . . . . . . 7 Configuration of the virtual phases . . . . . . . . . . 8 Association of physical phases to the output voltages . . . . . . . . . . . . . . . . . . . . . . . . . 9 Association of connected phases to the internal phase generation . . . . . . . . . . . . . . . . . 9 Enabling of connected phases . . . . . . . . . . . . 10 Configuration of the boost converter frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control loop parameter setting . . . . . . . . . . . . 12 Output voltage programmability . . . . . . . . . . . 13 Output voltage target programming . . . . . . . . 13 Output overvoltage protection programming . 14 Coil peak current limitation . . . . . . . . . . . . . . . 14 Enabling the output voltage . . . . . . . . . . . . . . 15 Frequency trimming . . . . . . . . . . . . . . . . . . . . 16 Gate voltage supply . . . . . . . . . . . . . . . . . . . . 18 Gate voltage supply diagnostics . . . . . . . . . . . 18 Supply voltage monitoring . . . . . . . . . . . . . . . 18 Battery voltage measurement. . . . . . . . . . . . . 18 Undervoltage detection. . . . . . . . . . . . . . . . . . 19 Overvoltage detection. . . . . . . . . . . . . . . . . . . 19 Junction temperature information . . . . . . . . . . 19 Diagnostic information . . . . . . . . . . . . . . . . . . 20 Bit VIN_OV . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bit VIN_UV . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bit SPI_err . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bit Tj_err . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bit VGG_err . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bit VGG_ok. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bit Vout1_ok and Vout2_ok . . . . . . . . . . . . . . 21 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11.2 Typical use case illustration (Write/Read) . . . 8.11.3 Diagnostics for the SPI interface . . . . . . . . . . 8.11.4 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 8.11.4.1 Control registers. . . . . . . . . . . . . . . . . . . . . . . 8.11.4.2 Configuration registers. . . . . . . . . . . . . . . . . . 8.11.4.3 Internal registers . . . . . . . . . . . . . . . . . . . . . . 8.11.4.4 Diagnostic registers . . . . . . . . . . . . . . . . . . . . 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal characteristics . . . . . . . . . . . . . . . . . 11 Static characteristics . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics. . . . . . . . . . . . . . . . . 13 Application information . . . . . . . . . . . . . . . . . 14 Test information . . . . . . . . . . . . . . . . . . . . . . . 14.1 Quality information . . . . . . . . . . . . . . . . . . . . . 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information . . . . . . . . . . . . . . . . . . . . . . 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information . . . . . . . . . . . . . . . . . . . . 19 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 24 25 25 26 27 28 28 29 29 30 31 33 33 33 34 35 36 36 36 36 37 37 38 38 39 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 October 2017 Document identifier: ASL2500SHN