B4860NXN7QUMD

NXP Semiconductors Data Sheet: Technical Data Document Number: B4860 Rev. 3, 09/2016 B4860 B4860 QorIQ Qonverge Data Sheet This B4860 QorIQ Qonverge chip is a NXP high-end heterogeneous multicore SoC based on StarCore, Power Architecture®, CoreNet, MAPLE, and DPAA technologies. The chip targets the emerging broadband wireless infrastructure and builds upon the proven success of NXP’s existing multicore DSPs and CPUs. It is designed to bolster the rapidly changing and expanding wireless base station markets, such as 3G-LTE (FDD and TDD), LTE-Advanced, TD-SCDMA, GSM and WCDMA. This chip can be used for combined control, data path, and application layer processing in base stations and in general-purpose embedded computing systems. Its high level of integration offers performance benefits compared to multiple discrete devices, while also simplifying board design.This chip includes these functions and features: • Six fully-programmable StarCore SC3900 FVP core subsystems, divided into three clusters—each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications • Four dual-thread e6500 Power Architecture processors organized in one cluster—each core runs up to 1.6 GHz • Two 64-bits DDR3/3L controllers for high-speed, industry-standard memory interfaces running up to 1866 MT/s • MAPLE-B3 hardware acceleration—for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration • CoreNet fabric supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at up to 667 MHz and supports coherent and non-coherent out NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2015–2016 NXP B.V. FC-PBGA–1020 33 mm x 33 mm • • • • • • of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes: – Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution – Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores – Security engine (SEC 5.3)—crypto-acceleration for protocols such as IPsec, SSL and 802.16 Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856 KB internal memory space includes the following: – 32 KB L1 ICache per e6500/SC3900 core – 32 KB L1 DCache per e6500/SC3900 core – 2048 KB unified L2 cache for each SC3900 FVP cluster – 2048 KB unified L2 cache for e6500 cluster – Two 512 KB shared L3 CoreNet platform caches (CPC) Sixteen 10 Gbps SerDes lanes serving: – Two Serial RapidIO controllers each with four lanes running at up to 5 GT/s – Eight lanes common public radio interface (CPRI V4.2) controller for glueless antenna connection running at up to 9.8 GT/s – Two 10 GT/s Ethernet controllers (10GbE) for network communications – Six 1 GT/s/2.5 GT/s Ethernet controllers for network communications – Four lanes PCI Express controller running at up to 5 GT/s – Eight2.5 GT/s/3.125 GT/s/5 GT/s Debug (Aurora) Two OCeaN DMAs Various system peripherals 118 32-bit timers Table of Contents 1 2 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 1020 FC-PBGA ball layout diagrams . . . . . . . . . . . . . . .3 1.2 Pinout list by bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3 Pinout list by package pin number . . . . . . . . . . . . . . . .47 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .62 2.2 Power sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 2.3 Power-down requirements . . . . . . . . . . . . . . . . . . . . . .69 2.4 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .70 2.5 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .70 2.6 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 2.7 RESET initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .73 2.8 DDR3 and DDR3L SDRAM controller. . . . . . . . . . . . . .74 2.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . .80 2.10 eSPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 2.11 DUART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 2.12 Ethernet interface, Ethernet management interface 1 and 2, IEEE Std 1588™. . . . . . . . . . . . . . . . . . . . . . .83 2.13 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 2.14 Integrated flash controller . . . . . . . . . . . . . . . . . . . . . . .90 2.15 Enhanced secure digital host controller (eSDHC) . . . .92 2.16 Multicore programmable interrupt controller (MPIC) specifications . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.17 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 3 4 5 6 7 2.18 I2C interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 2.19 GPIO interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.20 Timers interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 2.21 Asynchronous signal timing. . . . . . . . . . . . . . . . . . . . 100 2.22 CPRI interface signals . . . . . . . . . . . . . . . . . . . . . . . . 100 2.23 High-speed serial interfaces (HSSI) . . . . . . . . . . . . . 101 Hardware design considerations . . . . . . . . . . . . . . . . . . . . . 141 3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 3.2 Power supply design . . . . . . . . . . . . . . . . . . . . . . . . . 145 3.3 Decoupling recommendations . . . . . . . . . . . . . . . . . . 150 3.4 SerDes block power supply decoupling recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 3.5 Connection recommendations for unused pins . . . . . 150 3.6 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 3.7 Thermal management information. . . . . . . . . . . . . . . 159 3.8 Temperature diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.1 Package parameters for the FC-PBGA . . . . . . . . . . . 161 4.2 Mechanical dimensions of the B4860 FC-PBGA. . . . 162 Security fuse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6.1 Part numbering nomenclature . . . . . . . . . . . . . . . . . . 163 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 B4860 QorIQ Qonverge Data Sheet, Rev. 3 2 NXP Semiconductors Pin assignments This figure shows the major functional units of the chip. StarCore Sc3900 FCP core Power Architecture e6500 dual-thread core Power Architecture e6500 dual-thread core 32 KB I-Cache 32 KB L1 D-cache L1 I-cache 32 KB I-Cache 32 KB L1 D-cache L1 I-cache 32 KB StarCore Sc3900 FVP core Starcore 32 KB Sc3900 KB FVP32 core Starcore I-Cache I-Cache 32 KB 32 Sc3900 32core KB 32 KB 32 KB KB 32 KB FVP 32I-Cache KB 32L1 32I-Cache KB 32L1 L1 D-cache D-cache KBI-cache32L1KB KBI-cache I-Cache I-Cache L1KB I-Cache L1 D-Cache L1KB I-Cache 32 32 KB 32 2048 KB L1 I-CacheL1 D-Cache L1 I-Cache L2 cache Power Architecture e6500 dual-thread core 32 KB 2048 KB L2 Cache Power Architecture e6500 dual-thread core 32 KB 32 KB 32 KB I-Cache 32 KB L1 D-cache L1 I-cache 32 KB I-Cache 32 KB L1 D-cache L1 I-cache 64-bit DDR3/3L memory controller 64-bit DDR3/3L memory controller 512-KB L3/M3 cache 512-KB L3/M3 cache CoreNet Coherency fabric Frame Manager (FMan) Parse, classify, distribute 2x EQPE2 2x DEPE 2.5G/ 1Gbs 2.5/ 1Gbps 2.5/ 1Gbps 2.5/ 1Gbps 2.5/ 1Gbps 2.5/ 1Gbps 2x eTVPE2 8x eFTPE 10Gbps 2x PUPE2 2x PDPE2 10Gbps 1x CRPE DMA DMA OCeaN PCIE sRIO Debug (Aurora) 1588™ support QMan RapidIO Message Manager (RMan) MAPLE-B3 baseband accelerator sRIO USB Test port/ SAP eSDHC BMan IFC Pre boot loader Security monitor Power mgmt OpenPIC eSPI 44 GPIO 4x I2C SEC 5.3 2x DUART Clocks/Reset 1x TCPE x8 x4 x4 x4 x1 x1 x1 x1 x1 x1 x4/x1 x4/x1 Timers B4860 CPRI x8 16-lane 10-Gbps SerDes Figure 1. Block diagram 1 Pin assignments 1.1 1020 FC-PBGA ball layout diagrams These figures show the B4860 FC-PBGA ball map. B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 3 Pin assignments 1 A 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GND [A2] 2 AVDD_ CGA1 3 SGND [A4] 4 SD2_ RX7 SD2_ RX6 SGND [A7] 7 SD2_ RX5 SD2_ RX4 SGND [A10] SD2_ RX3 SD2_ RX2 SGND [A13] SD2_ REF1_ CLK_B SGND [A15] SD2_ RX1 SD2_ RX0 SGND [A18] SD1_ RX0 SD1_ RX1 SGND [A21] SD1_ REF1_ CLK_B SGND [A23] SD1_ RX2 SGND [A23] SD1_ RX3 SD1_ RX4 SGND [A28] SD1_ RX5 SD1_ RX6 SGND [A31] 32 SD1_ REF1_ CLK SGND [B23] SD1_ RX2_B SGND [B23] SD1_ RX3_B SD1_ RX4_B SGND [B28] SD1_ RX5_B SD1_ RX6_B SGND [B31] NC_ DET B A B GND [B1] AVDD_ CGB1 AVDD_ PLAT SGND [B4] SD2_ RX7_B SD2_ RX6_B SGND [B7] SD2_ RX5_B SD2_ RX4_B SGND [B10] SD2_ RX3_B SD2_ RX2_B SGND [B13] SD2_ REF1_ CLK SGND SD2_ [B15] RX1_B SD2_ RX0_B SGND [B18] SD1_ RX0_B SD1_ RX1_B SGND [B21] C AVDD_ CGA2 GND [C2] AVDD_ CGB2 SGND [C4] SGND [C5] SGND [C6] SGND [C7] SGND C8] SGND [C9] SGND [C10] SGND [C11] SGND [C12] SGND [C13] SGND [C14 SGND [C15] SGND [C16] SGND [C17] SGND [C18] SGND [C19] SGND [C20] SGND [C21] SGND [C22] SGND [C23] SGND [C24] SGND [C25] SGND [C26] SGND [C27] SGND [C28] SGND [C29] SGND [C30] SD1_ RX7_B SD1_ RX7 C GND [D1] NC_ D2 GND [D3] SGND [D4] SD2_ REF2_ CLK_B XGND [D6] SD2_ TX7 SD2_ TX6 XGND [D9] SD1_ SD2_ TX5 TX5 SD2_ TX4 XGND [D12] SD2_ TX3 SD2_ TX2 XGND [D15] SD2_ TX1 SD2_ TX0 XGND [D18] SD1_ TX0 SD1_ TX1 XGND [D21] SD1_ TX2 SD1_ TX3 XGND [D24] SD1_ TX4 SD1_ TX5 XGND [D27] SD1_ TX6 SD1_ TX7 XGND [D30] SGND [D31] SGND [D32] D E PO QVDD RESET_ [E2] B NC_ E3 SGND [E5] SD2_ REF2_ CLK XGND [E6] SD2_ TX7_B SD2_ TX6_B XGND [E9] SD1_ SD2_ TX5 TX5_B SD2_ TX4_B XGND [E12] SD2_ TX3_B SD2_ TX2_B XGND [E15] SD2_ TX1_B SD2_ TX0_B XGND [E18] SD1_ TX0_B SD1_ TX1_B XGND [E18] SD1_ TX2_B SD1_ TX3_B XGND [E24] SD1_ TX4_B SD1_ TX5_B XGND [E27] SD1_ TX6_B SD1_ TX7_B XGND [E30] SD1_ REF2_ CLK SD1_ REF2_ CLK_B E F QVDD SYSCLK [F2] GND [F3] NC [F4] SGND [F5] SGND [F6] SGND [F7] SGND [F8] XVDD [F9] SGND [F10] SGND [F11] XVDD [F12] SGND [F13] SGND [F14] XVDD [F15] SGND [F16] XVDD DD [F17] XGND [F18] XVDD [F19] SGND [F20] XVDD [F21] SGND [F22] SGND [F23] XVDD [F24] SGND [F25] SGND [F26] XVDD [F27] SGND [F28] SGND [F29] XVDD [F30] SGND [F31] SGND [F32] F NC_ G5 GND [G6] GND [G7] GND [G8] SD1_ SGND SGND SD2_IMP_ TX5 [G11] [G9] CAL_TX SGND [G12] NC_ G13 AGND_ SRDS2_ PLL2 SGND [G15] NC_ G16 SGND SD1_ SGND SGND SD2_ [G19] IMP_CAL [G21] [G17] IMP_CAL _RX _RX NC_ G22 SGND AGND_ [G21] SRDS1_ PLL2 GND [G32] G D D1_ D1_ D1_ MDQ59 MDQ56 MDQ58 G GND [G1] H D1_ D1_ D1_ MDQ51 MDQ52 MDQ55 J D1_ D1_ D1_ D1_ MDQS6 MDQS6 MDM6 MDQS7 _B K D1_ MDQ50 L D1_ D1_ D1_ MDQ48 MDQ49 MDQ43 GND [K2] D1_ MDQ53 GND [H4] SEE DETAIL A D1_ D1_ MDQ60 MDQ63 D1_ MDQS7 _B D1_ D1_ MDQ54 MDM7 GND [L4] M N D1_ MDQ33 P D1_ MDQS4 GND [N2] D1_ MDQS4 _B R D1_ MDQ32 T D1_ G1VDD MA05 [T1] U D1_ MCK2 V D1_ MCK0 GND [R2] D1_ MDQ39 W G1VDD [W1] D1_ MDIC0 D1_ MA08 Y D1_ MECC3 GND [Y2] AA D1_ D1_ MDQS8_ MDQS8 B G1VDD [U3] D1_ MECC7 D1_ SENSESD1_ MODT1 VDD1 TX5 G1VDD [L8] D1_ D1_ MODT0 MODT3 D1_ MCS3 _B SGND [H12] NC_ H15 NC_ H16 GND [J11] VDD [J12] GND [J13] SGND [J14] SGND [J15] SGND [J16] SGND [J17] SGND [J18] SGND [J19] SGND [J20] SGND [J21] SGND [J22] SGND [J23] SGND [J24] GND [J25] GND [K10] VDD [K11] GND [K12] VDD [K13] GND [K14] SVDD [K15] SVDD [K16] SVDD [K17] SVDD [K18] SVDD [K18] SVDD [K20] SVDD [K21] SVDD [K22] SVDD [K23] GND [K24] D2_ D2_ D2_ D2_ MODT1 MDQ61 MDQ57 MDM7 VDD [L10] GND [L11] VDD [L12] GND [L13] VDD [L14] GND [L15] VDD [L16] GND [L17] VDD [L18] GND [L19] VDD [L20] GND [L21] VDD [L22] GND [L23] D2_ MCS3 _B G2VDD D2_ D2_ MODT3 MODT0 J D2_ D2_ MDQ54 MDQ53 D2_ D2_ D2_ MDQ62 MDQ45 MDQ47 D2_ MDQ43 GND [L29] GND [M12] VDD [M13] GND [M14] VDD [M15] GND [M16] VDD [M17] GND [M18] VDD [M19] GND [M20] VDD [M21] GND [M22] VDD [M23] GND [M24] GND [N11] GND [N13] VDD [N14] GND [N15] VDD [N16] GND [N17] VDD [N18] GND [N19] VDD [N20] GND [N21] VDD [N22] GND [N23] D2_ MA13 D1_ D1_ MDQ40 MDQ46 G1VDD [P7] D1_ MRAS _B D1_ MCS1_ B GND G1V DD [P10] [P10] VDD [P11] GND [P12] VDD [P13] GND [P14] VDD [P15] GND [P16] VDD [P17] GND [P18] VDD [P19] GND [P20] VDD [P21] GND [P22] VDD [P23] D1_ MCS2 _B D1_ MCAS _B G1VDD [R9] VDD [R10] GND [R11] VDD [R12] GND [R13] VDD [R14] GND [R15] VDD [R16] GND [R17] VDD [R18] GND [R19] VDD [R20] GND [R21] VDD [R22] GND [R23] G2VDD [R24] D2_ D2_ MCAS_ MCS2_ B B D1_ D1_ MAPAR MBA0 _OUT D1_ D1_ MA10 MA00 D1_ MCS0 _B G1VDD [T10] VDD [T11] GND [T12] VDD [T13] GND [T14] VDD [T15] GND [T16] VDD [T17] GND [T18] VDD [T19] GND [T20] VDD [T21] GND [T22] G2VDD [T23] D2_ MCS0 _B D2_ MBA0 D2_ D2_ MAPAR MA01 _OUT D2_ MBA1 D2_ MA10 D2_ MA00 G2VDD [U27] D2_ D2_ MCK3_ MCK3 B G2VDD [U30] GND [P4] D1_ MCK3 D1_ MCK1 D1_ MA06 GND [Y4] D1_ MBA1 GND [R6] D1_ MA01 D2_ D2_ MODT2 MWE_ B D2_ D2_ G2VDD MCS1_ MRAS [P26] _B B GND [M27] D2_ MDM5 D2_ D2_ MDQS5 MDQS5 _B D2_ D2_ MDQ46 MDQ40 GND [R27] D2_ MDQ50 K D2_ D2_ MDQ49 MDQ48 L GND [G32] D2_ D2_ D2_ D2_ MDQ42 MDQ41 MDQ37 MDQ34 VDD [N12] D2_ MDM4 M D2_ MDQ33 N D2_ D2_ D2_ MDQ39 MDQS4 MDQS4 _B GND [P29] D2_ D2_ D2_ MDQ44 MDQ38 MDQ36 D2_ MA02 GND [N31] D2_ MDQ35 P GND [R31] D2_ MDQ32 R D2_ D2_ MAPAR ERR_B MA05 G2VDD [T32] T D2_ MCK2_ B D2_ MCK2 U D1_ MCK3 _B D1_ MCK1 _B G1VDD [U6] G1VDD [U9] GND [U10] GND [U11] VDD [U12] GND [U13] VDD [U14] GND [U15] VDD [U16] GND [U17] VDD [U18] GND [U19] VDD [U20] GND [U21] VDD [U22] GND [U23] G2VDD [U24] G1VDD [V6] D1_ MDIC1 D1_ MA04 D1_ MA03 G1VDD [V10] VDD [V11] GND [V12] VDD [V13] GND [V14] VDD [V15] GND [V16] VDD [V17] GND [V18] VDD [V19] GND [V20] VDD [V21] GND [V22] G2VDD [V23] D2_ MA03 D2_ MA04 D2_ MDIC1 G2VDD [V27] D2_ MCK1 _B D2_ MCK1 G2VDD [V30] D2_ MCK0 _B D2_ MCK0 V D1_ MA07 D1_ MA09 D1_ MA12 D1_ MA11 G1VDD [W9] GND [W10] GND [W11] VDD [W12] GND [W13] VDD [W14] GND [W15] VDD [W16] GND [W17] VDD [W18] GND [W19] VDD [W20] GND [W21] VDD [W22] GND [W23] G2VDD [W24] D2_ MA11 D2_ MA12 D2_ MA09 D2_ MA07 D2_ MA06 D2_ MA08 D2_ MDIC0 G2VDD [W32] W G1VDD [Y10] VDD [Y11] GND [Y12] VDD [Y13] GND [Y14] VDD [Y15] GND [Y16] VDD [Y17] GND [Y18] VDD [Y19] GND [Y20] VDD [Y21] GND [Y22] G2VDD [Y23] D2_ MA15 D2_ G2VDD MCKE2 [Y26] GND [Y31] D2_ MECC3 Y GND [AA21] VDD [AA22] D2_ G2VDD [AA23] MA14 D2_ D2_ D2_ MCKE1 MCKE0 MBA2 GND [AB23] GND [AB25] GND M2VREF AVDD_ GND [AC23] DDR2 [AC26] D1_ D1_ G1VDD MECC0 MCKE3 [Y7] D1_ D1_ MCKE2 MA15 D1_ D1_ D1_ MECC6 MDQ30 MDM3 D1_ MBA2 D1_ D1_ D1_ MCKE0 MCKE1 MA14 G1VDD [AA10] GND [AA11] VDD [AA12] GND [AA13] D1_ D1_ GND MECC2 MDQ29 [AB5] D1_ MDQ27 D1_ GND MDQ26 [AB8] GND [AB10] [AB10] VDD [AB11] GND [AB12] VDD [AB13] GND AVDD_ M1VREF [AC10] DDR1 GND [AC11] VDD [AC12] GND [AC13] GND [AD8] D1_ GND MDQ21 [AE2] D1_ D1_ D1_ MDQ23 MDQS0 MDQS0 _B TSEC_ TSEC_ D1_ D1_ EVT0 1588_ MDQ04 MDQ01 CLK_OUT1588_TRIG _B _IN1 AF D1_ D1_ MDQS2 MDQS2 _B D1_ D1_ GND MDQ16 MDQ03 [AF5] D1_ D1_ MDQ06 MDQ00 AG D1_ D1_ D1_ D1_ MDQ20 MDQ18 MDQ17 MDM0 AH D1_ MDM1 GND [AH2] D1_ D1_ D1_ MDQ14 MDQ12 MDQ09 1 D2_ D2_ MDQS6 MDQS6 _B VDD [M11] AE AM H D2_ MDM6 GND [M10] AD AL GND [H29] D2_ D2_ MDQS7 MDQS7 _B GND [J27] VDD [N10] D1_ D1_ GND MDQ19 MDQ22 [AD4] GND [AL1] TH_ VDD D2_ D2_ MDQ52 MDQ51 GND [M9] D1_ MDM2 D1_ D1_ MDQS1 MDQS1 _B SGND [H26] SEE DETAIL B D2_ MDQ55 D1_ D1_ MODT2 MA13 GND [M6] AC AJ NC_ H23 D2_ D2_ MDQ63 MDQ60 POVDD D1_ D1_ D1_ D1_ D1_ D1_ MDQS3 MDQS3 MECC5 MECC4 MECC1 MDQ31 _B AK NC_ H22 AVDD_ SGND SRDS1_ [H25] PLL2 SGND [H10] AB D1_ MDQ11 AGND_ AVDD_ SGND SRDS1_ SRDS1_ [H19] PLL1 PLL1 VDD [J10] D1_ MDM8 GND [AB2] AVDD_ AGND_ SRDS2_ SRDS2_ PLL1 PLL1 D2_ D2_ MDQ56 MDQ59 D1_ MWE_ B D1_ MAPAR_ D1_ ERR_B MA02 G1VDD [V3] D1_ D1_ MDQ57 MDQ61 SGND AVDD_ [H13] SRDS2_ PLL2 SD1_ D2_ SGND NC_G28 NC_ IMP_CAL MDQ58 [G27] G28 _TX D1_ D1_ D1_ MDQS5 MDQS5 MDM5 _B D1_ D1_ D1_ MDQ36 MDQ38 MDQ44 D1_ MCK2 _B D1_ MCK0 _B GND [H8] TD_ SENSETD_ [J7] ANODE GND1 [J8] CATHODE D1_ D1_ D1_ MDQ47 MDQ45 MDQ62 D1_ D1_ D1_ D1_ D1_ MDQ35 MDQ34 MDQ37 MDQ41 MDQ42 D1_ MDM4 GND [J6] NC_ H7 QVDD [H9] NC_ G25 GND [AC7] GND [AB9] GND [AA15] VDD [AA16] GND [AA17] VDD [AA18] GND [AA19] GND [AB14] VDD [AB15] GND [AB16] VDD [AB17] GND [AB18] VDD [AB19] GND [AB20] VDD [AB21] GND [AB22] VDD [AC14] GND [AC15] VDD [AC16] GND [AC17] VDD [AC18] GND [AC19] VDD [AC20] GND [AC21] VDD [AC22] OVDD SENSE- D1_ GND2 DDRCLK [AD13] GND [AD14] OVDD [AD15] GND [AD16] OVDD [AD17] GND [AD18] DVDD [AD19] D2_ GND GND [AD20] DDRCLK [AD22] SENSE- GND VDD2 [AE13] OVDD [AE14] GND [AE15] OVDD [AE16] GND [AE17] OVDD [AE18] GND [AE19] DVDD [AE20] SEE DETAIL C D1_ D1_ D1_ MDQ28 MDQ24 MDQ25 GND [AD9] NC_ AD10 EVT1 _B VDD [AA14] VDD [AA20] GND [AE21] GND [AB24] GND [AE22] NC_ AD23 GND [AD24] IIC2_ UART1_ SCL CTS_B USB_ D0 EVT4 _B IFC_ AD02 IFC_ AD08 IFC_ AD09 IFC_ AD10 IFC_ AD12 IFC_ AD13 IFC_ AD03 USB_ D1 GND [AG8] TSEC_ 1588_ ALARM_ OUT1 CP_ SYNC2 GND [AG11] IFC_ AD00 IFC_ AD01 GND [AG14] IFC_ A16 IFC_ A18 GND [AG17] IFC_ A15 IFC_ A21 GND [AG20] SPI_ CLK USB_ STP USB_ D2 TSEC_ 1588_ ALARM_ OUT2 CP_ SYNC7 CP_ SYNC3 EVT2 _B IFC_ A24 IFC_ PAR0 IFC_ A17 IFC_ AD04 IFC_ AD11 IFC_ A20 IFC_ AD19 IFC_ AD14 SPI_ CS2_B SDHC_ DAT1 IRQ02 GND [AJ5] USB_ D3 GND [AJ7] EMI2_ MDIO CP_ SYNC0 GND [AJ9] EVT3 _B IFC_ PAR1 GND [AJ12] IFC_ A25 IFC_ A26 GND [AJ12] IFC_ A27 IFC_ CS3_B GND [AJ19] IFC_ A22 SPI_ CS0_B GND [AJ22] USB_ D5 TSEC_ 1588_ PULSE_ OUT2 CP_ SYNC5 CKSTP_ IFC_ CP_ OUT_ WE_0 SYNC6 ASLEEP _B B IFC_ CS1_B IFC_ CS2_B IFC_ CS0_B IFC_ OE_B IFC_ A23 IFC_ AD07 SPI_ CS1_B SDHC_ CMD IRQ06 IRQ08 GND [AL15] IFC_ BCTL IFC_ AD06 GND [AL18] IFC_ AVD SPI_ MISO GND [AL21] SDHC_ DAT2 IFC_ RB0_B IFC_ TE IFC_ RB1_ B IFC_ CLK0 IFC_ CLK1 SPI_ CS3_B SPI_ MOSI SDHC_ CLK RTC IRQ09 16 17 18 19 20 21 22 23 24 D1_ D1_ MDQ05 MDQ02 D1_ D1_ D1_ MDQ13 MDQ08 MDQ07 D1_ MDQ10 USB_ D7 USB_ D4 D1_ MDQ15 GND [AL3] USB_ CLK USB_ NXT GND [AM2] TSEC_ 1588_ CLK_IN USB_ D6 USB_ DIR 2 3 4 5 DMA1_ CP_ GND CP_ CP_ IFC_ IFC_ GND DACK0 SYNC4 [AL9] RCLK0 RCLK1 [AL12] AD05 WP0_B _B DMA1_ DMA1_ EMI2_ RESET_ CP_ CP_ HRESET IFC_ CLK_OUT CLE DREQ0 DDONE0 MDC REQ_B RCLK0_B RCLK1_B _B _B _B GND [AL6] 6 7 8 9 10 11 12 13 14 15 D2_ D2_ MDQ26 MDQ27 IRQ01 UART2_ IRQ00 UART1_ RTS_B SOUT SDHC_ DAT0 GND [AG20] D2_ MECC7 D2_ D2_ D2_ D2_ MDQ30 MECC6 MDQS8 MDQS8_ B GND [AB28] D2_ D2_ GND MDQ29 MECC2 [AB31] D2_ MDM8 D2_ D2_ D2_ D2_ D2_ D2_ MDQS3 MDQS3 MDQ31 MECC1 MECC4 MECC5 _B D2_ D2_ D2_ GND [AD25] MDQ25 MDQ24 MDQ28 IIC4_ SDA GND [Y29] D2_ MDM3 SEE DETAIL D TSEC_ TSEC_ 1588_ 1588_TRIG CP_ PULSE_ SYNC1 _IN2 OUT1 TMP_ SDHC_ DETECT DAT3 _B D2_ D2_ MCKE3 MECC0 GND [AD29] D2_ D2_ D2_ MDQ22 MDQ19 MDM2 AA AB AC AD D2_ D2_ D2_ MDQ01 MDQ04 MDQS0 D2_ D2_ GND MDQS0 MDQ23 [AE31] _B D2_ MDQ21 AE D2_ D2_ GND MDQ00 MDQ06 [AF28] D2_ MDQ03 D2_ D2_ MDQ16 MDQS2 D2_ MDQS2 _B AF D2_ D2_ D2_ MDQ17 MDQ18 MDQ20 AG IIC2_ SDA UART2_ RTS_B GND [AG26] IRQ03 IRQ04 IIC1_ SDA UART2_ SIN IIC1_ SCL D2_ MDQ07 D2_ D2_ GND MDQ08 MDQ13 [AH31] IRQ_ OUT_B IRQ10 GND [AJ25] EMI1_ MDC IIC4_ SCL GND [AJ28] D2_ D2_ D2_ D2_ MDQ09 MDQ12 MDQ14 MDQ11 AJ IRQ05 IRQ07 TRST _B EMI1_ _ MDIO D2_ D2_ MDQ10 MDQS1 D2_ MDQS1 _B AK IRQ11 GND [AL24] GND [AL32] AL D2_ D2_ D2_ MDQ02 MDQ05 MDM0 CP_ UART2_ LOS1 CTS_B CP_ LOS3 TCK GND [AL27] TMS TDI CP_ UART1_ SIN LOS2 25 26 TDO 27 28 IIC3_ SDA UART1_ SOUT GND [AL30] D2_ MDQ15 CP_ LOS0 IIC3_ SCL GND [AM31] 29 30 31 D2_ MDM1 AH AM 32 Signal groups OVDD I/O supply voltage SVDD SerDes core power supply XVDD SerDes transmitter pad supply DVDD I/O supply voltage I/O supply voltage AVDD_ SRDSn GnVDD POVDD QVDD SerDes n PLL supply voltage SENSEVDD1 Core group 1 voltage sense GND DDR1/DDR2 I/O supply AVDD_ PLAT Platform PLL supply voltage SENSEVDD2 Core group 2 voltage sense SGND SerDes core ground supply Fuse I/O supply AVDD_ CGxn Core group x, n supply voltage XGND SerDes transceivers ground AVDD_ DDRn DDR n PLL supply voltage Ground Figure 2. 1020 BGA ball map diagram (top view) B4860 QorIQ Qonverge Data Sheet, Rev. 3 4 NXP Semiconductors Pin assignments 1 A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND [A2] AVDD_ CGA1 SGND [A4] SD2_ RX7 SD2_ RX6 SGND [A7] SD2_ RX5 SD2_ RX4 SGND [A10] SD2_ RX3 SD2_ RX2 SGND [A13] SD2_ REF1_ CLK_B SGND [A15] SD2_ RX1 B GND [B1] AVDD_ CGB1 AVDD_ PLAT SGND [B4] SD2_ RX7_B SD2_ RX6_B SGND [B7] SD2_ RX5_B SD2_ RX4_B SGND [B10] SD2_ RX3_B SD2_ RX2_B SGND [B13] SD2_ REF1_ CLK SGND SD2_ [B15] RX1_B C AVDD_ CGA2 GND [C2] AVDD_ CGB2 SGND [C4] SGND [C5] SGND [C6] SGND [C7] SGND C8] SGND [C9] SGND [C10] SGND [C11] SGND [C12] SGND [C13] SGND [C14 SGND [C15] SGND [C16] D GND [D1] NC_ D2 GND [D3] SGND [D4] SD2_ REF2_ CLK_B XGND [D6] SD2_ TX7 SD2_ TX6 XGND [D9] SD1_ SD2_ TX5 TX5 SD2_ TX4 XGND [D12] SD2_ TX3 SD2_ TX2 XGND [D15] SD2_ TX1 E PO QVDD RESET_ [E2] B NC_ E3 SGND [E5] SD2_ REF2_ CLK XGND [E6] SD2_ TX7_B SD2_ TX6_B XGND [E9] SD1_ SD2_ TX5 TX5_B SD2_ TX4_B XGND [E12] SD2_ TX3_B SD2_ TX2_B XGND [E15] SD2_ TX1_B F SYSCLK QVDD [F2] GND [F3] NC_ F4 SGND [F5] SGND [F6] SGND [F7] SGND [F8] XVDD [F9] SGND [F10] SGND [F11] XVDD [F12] SGND [F13] SGND [F14] XVDD [F15] SGND [F16] G GND [G1] NC_ G5 GND [G6] GND [G7] GND [G8] SD1_ SGND SGND SD2_IMP_ [G11] TX5 [G9] CAL_TX SGND [G12] NC_ G13 AGND_ SRDS2_ PLL2 SGND [G15] NC_ G16 H D1_ D1_ D1_ MDQ51 MDQ52 MDQ55 NC_ H7 GND [H8] QVDD [H9] SGND AVDD_ [H13] SRDS2_ PLL2 NC_ H15 NC_ H16 J D1_ D1_ D1_ D1_ MDQS6 MDQS6 MDM6 MDQS7 _B K D1_ MDQ50 L D1_ D1_ D1_ MDQ48 MDQ49 MDQ43 D1_ D1_ D1_ MDQ59 MDQ56 MDQ58 D1_ MDQ53 GND [K2] GND [H4] D1_ D1_ MDQ60 MDQ63 D1_ MDQS7 _B D1_ D1_ MDQ54 MDM7 GND [L4] D1_ D1_ D1_ MDQ47 MDQ45 MDQ62 D1_ D1_ D1_ D1_ D1_ MDQ35 MDQ34 MDQ37 MDQ41 MDQ42 N D1_ MDQ33 P D1_ MDQS4 D1_ MDM4 D1_ MDQS4 _B R D1_ MDQ32 GND [R2] T G1VDD [T1] D1_ MA05 D1_ MDQ39 GND [M6] D1_ D1_ D1_ MDQS5 MDQS5 MDM5 _B GND [P4] D1_ D1_ MDQ40 MDQ46 D1_ D1_ D1_ MDQ36 MDQ38 MDQ44 D1_ MAPAR_ D1_ ERR_B MA02 TD_ GND GND NC_ TD_ NC_ SENSE[J7] CATHODE [J8] ANODE J7 GND1 J8 D1_ D1_ MDQ57 MDQ61 M GND [N2] GND [J6] D1_ MBA1 GND [R6] D1_ MA01 D1_ SENSESD1_ MODT1 VDD1 TX5 SGND [H10] POVDD SGND [H12] VDD [J10] GND [J11] VDD [J12] GND [J13] SGND [J14] SGND [J15] SGND [J16] GND [K10] VDD [K11] GND [K12] VDD [K13] GND [K14] SVDD [K15] SVDD [K16] G1VDD [L8] D1_ MCS3 _B VDD [L10] GND [L11] VDD [L12] GND [L13] VDD [L14] GND [L15] VDD [L16] D1_ D1_ MODT0 MODT3 GND [M9] GND [M10] VDD [M11] GND [M12] VDD [M13] GND [M14] VDD [M15] GND [M16] D1_ MWE _B D1_ D1_ MODT2 MA13 VDD [N10] GND [N11] VDD [N12] GND [N13] VDD [N14] GND [N15] VDD [N16] G1VDD [P7] D1_ MRAS _B D1_ MCS1_ B GND G1V DD [P10] [P10] VDD [P11] GND [P12] VDD [P13] GND [P14] VDD [P15] GND [P16] G1VDD [R9] VDD GND [R10] [R10] GND [R11] VDD [R12] GND [R13] VDD [R14] GND [R15] VDD [R16] D1_ MCS0 _B G1VDD [T10] VDD [T11] GND [T12] VDD [T13] GND [T14] VDD [T15] GND [T16] D1_ D1_ MCS2 MCAS _B _B D1_ D1_ MAPAR_ MBA0 OUT DETAIL A Figure 3. 1020 BGA ball map diagram (detail view A) B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 5 Pin assignments 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SD2_ RX0 SGND [A18] SD1_ RX0 SD1_ RX1 SGND [A21] SD1_ REF1_ CLK_B SGND [A23] SD1_ RX2 SGND [A23] SD1_ RX3 SD1_ RX4 SGND [A28] SD1_ RX5 SD1_ RX6 SGND [A31] SD2_ RX0_B SGND [B18] SD1_ RX0_B SD1_ RX1_B SGND [B21] SD1_ REF1_ CLK_B SGND [B23] SD1_ RX2_B SGND [B23] SD1_ RX3_B SD1_ RX4_B SGND [B28] SD1_ RX5_B SD1_ RX6_B SGND [B31] NC_ DET B SGND [C17] SGND [C18] SGND [C19] SGND [C20] SGND [C21] SGND [C22] SGND [C23] SGND [C24] SGND [C25] SGND [C26] SGND [C27] SGND [C28] SGND [C29] SGND [C30] SD1_ RX7_B SD1_ RX7 C SD2_ TX0 XGND [D18] SD1_ TX0 SD1_ TX1 XGND [D21] SD1_ TX2 SD1_ TX3 XGND [D24] SD1_ TX4 SD1_ TX5 XGND [D27] SD1_ TX6 SD1_ TX7 XGND [D30] SGND [D31] SGND [D32] D SD2_ TX0_B XGND [E18] SD1_ TX0_B SD1_ TX1_B XGND [E18] SD1_ TX2_B SD1_ TX3_B XGND [E24] SD1_ TX4_B SD1_ TX5_B XGND [E27] SD1_ TX6_B SD1_ TX7_B XGND [E30] SD1_ REF2_ CLK SD1_ REF2_ CLK_B E XVDD [F17] XGND [F18] XVDD [F19] SGND [F20] XVDD [F21] SGND [F22] SGND [F23] XVDD [F24] SGND [F25] SGND [F26] XVDD [F27] SGND [F28] SGND [F29] XVDD [F30] SGND [F31] SGND [F32] F NC_ G22 AGND_ SGND SRDS1_ [G21] PLL2 NC_ G28 D2_ MDQ58 D2_ D2_ MDQ56 MDQ59 GND [G32] G AGND_ AVDD_ SGND SRDS1_ SRDS1_ [H19] PLL1 PLL1 NC_ H22 NC_ H23 SGND SD1_ SGND SGND SD2_ [G19] IMP_CAL [G21] [G17] IMP_CAL _RX _RX AVDD_ AGND_ SRDS2_ SRDS2_ PLL1 PLL1 NC_ G25 AVDD_ SGND SRDS1_ [H25] PLL2 SD1_ SGND IMP_CAL [G27] _TX SGND [H26] D2_ D2_ MDQ63 MDQ60 TH_ VDD GND [J27] GND [H29] D2_ D2_ MDQS7 MDQS7 _B 32 A D2_ D2_ D2_ MDQ55 MDQ52 MDQ51 D2_ MDM6 D2_ D2_ MDQS6 MDQS6 _B H SGND [J17] SGND [J18] SGND [J19] SGND [J20] SGND [J21] SGND [J22] SGND [J23] SGND [J24] GND [J25] SVDD [K17] SVDD [K18] SVDD [K18] SVDD [K20] SVDD [K21] SVDD [K22] SVDD [K23] GND [K24] D2_ D2_ D2_ D2_ MODT1 MDQ61 MDQ57 MDM7 GND [L17] VDD [L18] GND [L19] VDD [L20] GND [L21] VDD [L22] GND [L23] D2_ MCS3 _B G2VDD VDD [M17] GND [M18] VDD [M19] GND [M20] VDD [M21] GND [M22] VDD [M23] GND [M24] D2_ D2_ MODT3 MODT0 GND [M27] D2_ D2_ D2_ D2_ MDQ42 MDQ41 MDQ37 MDQ34 D2_ MDQ35 M GND [N17] VDD [N18] GND [N19] VDD [N20] GND [N21] VDD [N22] GND [N23] D2_ MA13 D2_ D2_ MODT2 MWE_ B D2_ MDM5 D2_ D2_ MDQS5 MDQS5 _B D2_ MDQ33 N VDD [P17] GND [P18] VDD [P19] GND [P20] VDD [P21] GND [P22] VDD [P23] D2_ D2_ MCS1_ MRAS _B B GND [R17] VDD [R18] GND [R19] VDD [R20] GND [R21] VDD [R22] GND [R23] G2VDD [R24] VDD [T17] GND [T18] VDD [T19] GND [T20] VDD [T21] GND [T22] G2VDD [T23] D2_ MCS0 _B D2_ D2_ D2_ MDQ62 MDQ45 MDQ47 G2VDD [P26] D2_ D2_ MDQ46 MDQ40 D2_ D2_ GND MCAS_ MCS2_ [R27] B B D2_ D2_ D2_ MAPAR MBA0 MA01 _OUT D2_ D2_ MDQ54 MDQ53 GND [L29] GND [P29] D2_ MDQ43 D2_ MDM4 D2_ MBA1 D2_ MA02 D2_ MDQ50 K D2_ D2_ MDQ49 MDQ48 L GND [G32] GND [N31] D2_ D2_ D2_ MDQS4 MDQS4 MDQ39 _B D2_ D2_ D2_ MDQ44 MDQ38 MDQ36 J P GND [R31] D2_ MDQ32 R D2_ MAPAR_ D2_ ERR_B MA05 G2VDD [T32] T DETAIL B Figure 4. 1020 BGA ball map diagram (detail view B) B4860 QorIQ Qonverge Data Sheet, Rev. 3 6 NXP Semiconductors Pin assignments DETAIL C U D1_ MCK2 D1_ MCK2 _B D1_ G1VDD MCK3 [U3] D1_ MCK3 _B D1_ G1VDD MA00 [U6] D1_ MA10 G1VDD [U9] GND [U10] GND [U11] VDD [U12] GND [U13] VDD [U14] GND [U15] VDD [U16] V D1_ MCK0 D1_ MCK0 _B D1_ G1VDD MCK1 [V3] D1_ MCK1 _B D1_ G1VDD MDIC1 [V6] D1_ MA04 D1_ MA03 G1VDD [V10] VDD [V11] GND [V12] VDD [V13] GND [V14] VDD [V15] GND [V16] W D1_ G1VDD MDIC0 [W1] D1_ MA08 D1_ MA06 D1_ MA07 D1_ MA09 D1_ MA11 G1VDD [W9] GND [W10] GND [W11] VDD [W12] GND [W13] VDD [W14] GND [W15] VDD [W16] D1_ MECC3 D1_ MECC7 GND [Y4] D1_ D1_ D1_ D1_ G1VDD MECC0 MCKE3 [Y7] MCKE2 MA15 G1VDD [Y10] VDD [Y11] GND [Y12] VDD [Y13] GND [Y14] VDD [Y15] GND [Y16] Y GND [Y2] D1_ MA12 D1_ D1_ MDQS8_ MDQS8 B D1_ D1_ D1_ MECC6 MDQ30 MDM3 D1_ MBA2 D1_ D1_ D1_ MCKE0 MCKE1 MA14 G1VDD [AA10] GND [AA11] VDD [AA12] GND [AA13] VDD [AA14] GND [AA15] VDD [AA16] AB D1_ MDM8 D1_ D1_ GND MECC2 MDQ29 [AB5] D1_ MDQ27 D1_ GND MDQ26 [AB8] GND [AB10] VDD [AB11] GND [AB12] VDD [AB13] GND [AB14] VDD [AB15] GND [AB16] AC D1_ D1_ D1_ D1_ D1_ D1_ MDQS3 MDQS3 MECC5 MECC4 MECC1 MDQ31 _B GND AVDD_ M1VREF [AC10] DDR1 GND [AC11] VDD [AC12] GND [AC13] VDD [AC14] GND [AC15] VDD [AC16] AD D1_ MDM2 SENSE- D1_ OVDD GND2 DDRCLK [AD13] GND [AD14] OVDD [AD15] GND [AD16] AE D1_ GND MDQ21 [AE2] D1_ D1_ D1_ MDQ23 MDQS0 MDQS0 _B TSEC_ TSEC_ D1_ D1_ EVT0 1588_ MDQ04 MDQ01 CLK_OUT1588_TRIG _B _IN1 SENSEVDD2 GND [AE13] OVDD [AE14] GND [AE15] OVDD [AE16] AF D1_ D1_ MDQS2 MDQS2 _B D1_ D1_ GND MDQ16 MDQ03 [AF5] D1_ D1_ MDQ06 MDQ00 AG D1_ D1_ D1_ D1_ MDQ20 MDQ18 MDQ17 MDM0 AH D1_ MDM1 GND [AH2] AJ D1_ MDQ11 D1_ D1_ D1_ MDQ14 MDQ12 MDQ09 AK D1_ D1_ MDQS1 MDQS1 _B AL GND 1 [AL1] AA AM 1 GND [AB2] D1_ D1_ MDQ19 MDQ22 GND [AD4] GND [AC7] D1_ D1_ D1_ MDQ28 MDQ24 MDQ25 GND [AD8] GND [AB9] GND [AD9] NC_ AD10 EVT1 _B USB_ D0 TSEC_ TSEC_ 1588_ 1588_TRIG CP_ PULSE_ SYNC1 _IN2 OUT1 EVT4 _B IFC_ AD02 IFC_ AD08 IFC_ AD09 IFC_ AD10 USB_ D1 GND [AG8] TSEC_ 1588_ ALARM_ OUT1 CP_ SYNC2 GND [AG11] IFC_ AD00 IFC_ AD01 GND [AG14] IFC_ A16 IFC_ A18 USB_ STP USB_ D2 TSEC_ 1588_ ALARM_ OUT2 CP_ SYNC7 CP_ SYNC3 EVT2 _B IFC_ A24 IFC_ PAR0 IFC_ A17 IFC_ AD04 IFC_ AD11 GND [AJ5] USB_ D3 GND [AJ7] EMI2_ MDIO CP_ SYNC0 GND [AJ10] EVT3 _B IFC_ PAR1 GND [AJ13] IFC_ A25 IFC_ A26 GND [AJ16] USB_ D5 TSEC_ 1588_ PULSE_ OUT2 CP_ SYNC5 CKSTP_ IFC_ CP_ WE_0 SYNC6 ASLEEP OUT_ _B B IFC_ CS1_B IFC_ CS2_B IFC_ CS0_B IFC_ OE_B CP_9 GND 14IFC_ 15 IFC_ 16 GND CP_ CP_ GND 10 11 12 13 DACK0 SYNC4 [AL9] RCLK0 RCLK1 [AL12] AD05 WP0_B [AL15] _B DMA1_ DMA1_ CP_ EMI2_ RESET_ CP_ HRESET IFC_ IFC_ DREQ0 DDONE0 MDC REQ_B RCLK0_B RCLK1_B _B CLK_OUT CLE RB0_B _B _B IFC_ BCTL D1_ D1_ MDQ05 MDQ02 D1_ D1_ D1_ MDQ13 MDQ08 MDQ07 D1_ MDQ10 USB_ D7 USB_ D4 D1_ 2 MDQ15 GND 3 [AL3] USB_ 4 CLK DMA1_ 5USB_ 6 GND 7 8 GND [AM2] TSEC_ 1588_ CLK_IN USB_ D6 USB_ DIR 2 3 4 5 [AL6] NXT 6 7 8 9 10 11 12 13 14 15 IFC_ TE 16 Figure 5. 1020 BGA ball map diagram (detail view C) B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 7 Pin assignments DETAIL D D2_ MA10 D2_ MA00 D2_ MA03 D2_ MA04 D2_ MDIC1 GND [W23] G2VDD [W24] D2_ MA11 D2_ MA12 GND [Y22] G2VDD [Y23] D2_ MA15 D2_ G2VDD MCKE2 [Y26] GND [AA21] VDD [AA22] G2VDD [AA23] D2_ MA14 D2_ D2_ D2_ MCKE1 MCKE0 MBA2 GND [AB20] VDD [AB21] GND [AB22] GND [AB23] GND [AB24] GND [AB25] GND [AC19] VDD [AC20] GND [AC21] VDD [AC22] GND M2VREF AVDD_ GND [AC23] DDR2 [AC26] GND [AD18] DVDD [AD19] GND D2_ GND [AD20] DDRCLK [AD22] GND [AE17] OVDD [AE18] GND [AE19] DVDD [AE20] IFC_ AD12 IFC_ AD13 IFC_ AD03 GND [AG17] IFC_ A15 IFC_ A21 GND [AG20] IFC_ A20 IFC_ AD19 IFC_ AD14 IFC_ A27 IFC_ CS3_B IFC_ A23 GND [U17] VDD [U18] GND [U19] VDD [U20] GND [U21] VDD [U22] GND [U23] G2VDD [U24] VDD [V17] GND [V18] VDD [V19] GND [V20] VDD [V21] GND [V22] G2VDD [V23] GND [W17] VDD [W18] GND [W19] VDD [W20] GND [W21] VDD [W22] VDD [Y17] GND [Y18] VDD [Y19] GND [Y20] VDD [Y21] GND [AA17] VDD [AA18] GND [AA19] VDD [AA20] VDD [AB17] GND [AB18] VDD [AB19] GND [AC17] VDD [AC18] OVDD [AD17] NC_ AD23 GND [AD24] D2_ MCK3 G2VDD [V27] D2_ MCK3 _B D2_ MCK1 _B D2_ MA09 D2_ MA07 D2_ MA06 G2VDD [U27] D2_ D2_ MCKE3 MECC0 D2_ D2_ MDQ26 MDQ27 D2_ MCK1 GND [Y29] D2_ MCK2 _B D2_ G2VDD MCK0 [V30] _B D2_ MCK2 U D2_ MCK0 V D2_ MA08 D2_ MDIC0 G2VDD [W32] W GND [Y31] D2_ MECC3 Y G2VDD [U30] D2_ MECC7 D2_ MDM3 D2_ D2_ D2_ D2_ MDQ30 MECC6 MDQS8 MDQS8_ B GND [AB28] D2_ D2_ GND MDQ29 MECC2 [AB31] D2_ MDM8 D2_ D2_ D2_ D2_ D2_ D2_ MDQS3 MDQS3 MDQ31 MECC1 MECC4 MECC5 _B D2_ D2_ D2_ GND GND [AD25] MDQ25 MDQ24 MDQ28 [AD29] D2_ D2_ D2_ MDQ22 MDQ19 MDM2 AA AB AC AD GND [AE21] GND [AE22] TMP_ SDHC_ DETECT DAT3 _B IRQ01 UART2_ IRQ00 UART1_ RTS_B SOUT SPI_ CLK SDHC_ DAT0 GND [AG20] IIC2_ SDA UART2_ RTS_B GND [AG26] SPI_ CS2_B SDHC_ DAT1 IRQ02 IRQ03 IRQ04 IIC1_ SDA UART2_ SIN IIC1_ SCL D2_ MDQ07 D2_ D2_ GND MDQ08 MDQ13 [AH31] GND [AJ19] IFC_ A22 SPI_ CS0_B GND [AJ22] IRQ_ OUT_B IRQ10 GND [AJ25] EMI1_ MDC IIC4_ SCL GND [AJ28] D2_ D2_ D2_ D2_ MDQ09 MDQ12 MDQ14 MDQ11 AJ IFC_ AD07 IFC_ CS1_B SDHC_ CMD IRQ06 IRQ08 IRQ05 IRQ07 TRST _B EMI1_ MDIO CP_ UART2_ LOS1 CTS_B D2_ D2_ MDQ10 MDQS1 AK IFC_ AD06 GND [AL18] IFC_ AVD SPI_ MISO GND [AL21] SDHC_ DAT2 IRQ11 GND [AL24] TDO TCK GND [AL27] IFC_ RB1_ B IFC_ CLK0 IFC_ CLK1 SPI_ CS3_B SPI_ MOSI SDHC_ CLK RTC IRQ09 TMS TDI CP_ UART1_ SIN LOS2 17 18 19 20 21 22 23 24 25 26 IIC2_ UART1_ SCL CTS_B IIC4_ SDA D2_ D2_ D2_ MDQ01 MDQ04 MDQS0 D2_ D2_ GND MDQS0 MDQ23 [AE31] _B D2_ MDQ21 AE D2_ D2_ GND MDQ00 MDQ06 [AF28] D2_ MDQ03 D2_ D2_ MDQ16 MDQS2 D2_ MDQS2 _B AF D2_ D2_ D2_ MDQ17 MDQ18 MDQ20 AG D2_ D2_ D2_ MDQ02 MDQ05 MDM0 27 CP_ LOS3 28 IIC3_ SDA D2_ MDM1 D2_ MDQS1 _B AH D2_ GND MDQ15 [AL32] AL IIC3_ SCL GND [AM31] AM 30 31 UART1_ SOUT GND [AL30] CP_ LOS0 29 32 Figure 6. 1020 BGA ball map diagram (detail view D) B4860 QorIQ Qonverge Data Sheet, Rev. 3 8 NXP Semiconductors Pin assignments 1.2 Pinout list by bus This table provides the pinout list for the chip sorted by bus. Table 1. Pinout list by bus Signal Signal Description Package Pin Type Pin Power Supply Notes DDR SDRAM memory Interface 1 D1_MDQ00 Data AF7 IO G1VDD — D1_MDQ01 Data AE7 IO G1VDD — D1_MDQ02 Data AG6 IO G1VDD — D1_MDQ03 Data AF4 IO G1VDD — D1_MDQ04 Data AE6 IO G1VDD — D1_MDQ05 Data AG5 IO G1VDD — D1_MDQ06 Data AF6 IO G1VDD — D1_MDQ07 Data AH5 IO G1VDD — D1_MDQ08 Data AH4 IO G1VDD — D1_MDQ09 Data AJ4 IO G1VDD — D1_MDQ10 Data AK3 IO G1VDD — D1_MDQ11 Data AJ1 IO G1VDD — D1_MDQ12 Data AJ3 IO G1VDD — D1_MDQ13 Data AH3 IO G1VDD — D1_MDQ14 Data AJ2 IO G1VDD — D1_MDQ15 Data AL2 IO G1VDD — D1_MDQ16 Data AF3 IO G1VDD — D1_MDQ17 Data AG3 IO G1VDD — D1_MDQ18 Data AG2 IO G1VDD — D1_MDQ19 Data AD2 IO G1VDD — D1_MDQ20 Data AG1 IO G1VDD — D1_MDQ21 Data AE1 IO G1VDD — D1_MDQ22 Data AD3 IO G1VDD — D1_MDQ23 Data AE3 IO G1VDD — D1_MDQ24 Data AD6 IO G1VDD — D1_MDQ25 Data AD7 IO G1VDD — D1_MDQ26 Data AB7 IO G1VDD — D1_MDQ27 Data AB6 IO G1VDD — D1_MDQ28 Data AD5 IO G1VDD — D1_MDQ29 Data AB4 IO G1VDD — D1_MDQ30 Data AA4 IO G1VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 9 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes D1_MDQ31 Data AC4 IO G1VDD — D1_MDQ32 Data R1 IO G1VDD — D1_MDQ33 Data N1 IO G1VDD — D1_MDQ34 Data M2 IO G1VDD — D1_MDQ35 Data M1 IO G1VDD — D1_MDQ36 Data R3 IO G1VDD — D1_MDQ37 Data M3 IO G1VDD — D1_MDQ38 Data R4 IO G1VDD — D1_MDQ39 Data P3 IO G1VDD — D1_MDQ40 Data P5 IO G1VDD — D1_MDQ41 Data M4 IO G1VDD — D1_MDQ42 Data M5 IO G1VDD — D1_MDQ43 Data L3 IO G1VDD — D1_MDQ44 Data R5 IO G1VDD — D1_MDQ45 Data L6 IO G1VDD — D1_MDQ46 Data P6 IO G1VDD — D1_MDQ47 Data L5 IO G1VDD — D1_MDQ48 Data L1 IO G1VDD — D1_MDQ49 Data L2 IO G1VDD — D1_MDQ50 Data K1 IO G1VDD — D1_MDQ51 Data H1 IO G1VDD — D1_MDQ52 Data H2 IO G1VDD — D1_MDQ53 Data K3 IO G1VDD — D1_MDQ54 Data K4 IO G1VDD — D1_MDQ55 Data H3 IO G1VDD — D1_MDQ56 Data G3 IO G1VDD — D1_MDQ57 Data K6 IO G1VDD — D1_MDQ58 Data G4 IO G1VDD — D1_MDQ59 Data G2 IO G1VDD — D1_MDQ60 Data H5 IO G1VDD — D1_MDQ61 Data K7 IO G1VDD — D1_MDQ62 Data L7 IO G1VDD — D1_MDQ63 Data H6 IO G1VDD — D1_MECC0 Error Correcting Code Y5 IO G1VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 10 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes D1_MECC1 Error Correcting Code AC3 IO G1VDD — D1_MECC2 Error Correcting Code AB3 IO G1VDD — D1_MECC3 Error Correcting Code Y1 IO G1VDD — D1_MECC4 Error Correcting Code AC2 IO G1VDD — D1_MECC5 Error Correcting Code AC1 IO G1VDD — D1_MECC6 Error Correcting Code AA3 IO G1VDD — D1_MECC7 Error Correcting Code Y3 IO G1VDD — D1_MAPAR_ERR_B Address Parity Error T3 I G1VDD 2, 26 D1_MAPAR_OUT Address Parity Out T7 O G1VDD — D1_MDM0 Data Mask AG4 O G1VDD 2 D1_MDM1 Data Mask AH1 O G1VDD 2 D1_MDM2 Data Mask AD1 O G1VDD 2 D1_MDM3 Data Mask AA5 O G1VDD 2 D1_MDM4 Data Mask N3 O G1VDD 2 D1_MDM5 Data Mask N6 O G1VDD 2 D1_MDM6 Data Mask J3 O G1VDD 2 D1_MDM7 Data Mask K5 O G1VDD 2 D1_MDM8 Data Mask AB1 O G1VDD 2 D1_MDQS0 Data Strobe AE5 IO G1VDD — D1_MDQS1 Data Strobe AK2 IO G1VDD — D1_MDQS2 Data Strobe AF2 IO G1VDD — D1_MDQS3 Data Strobe AC6 IO G1VDD — D1_MDQS4 Data Strobe P1 IO G1VDD — D1_MDQS5 Data Strobe N4 IO G1VDD — D1_MDQS6 Data Strobe J1 IO G1VDD — D1_MDQS7 Data Strobe J4 IO G1VDD — D1_MDQS8 Data Strobe AA2 IO G1VDD — D1_MDQS0_B Data Strobe AE4 IO G1VDD — D1_MDQS1_B Data Strobe AK1 IO G1VDD — D1_MDQS2_B Data Strobe AF1 IO G1VDD — D1_MDQS3_B Data Strobe AC5 IO G1VDD — D1_MDQS4_B Data Strobe P2 IO G1VDD — D1_MDQS5_B Data Strobe N5 IO G1VDD — D1_MDQS6_B Data Strobe J2 IO G1VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 11 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes D1_MDQS7_B Data Strobe J5 IO G1VDD — D1_MDQS8_B Data Strobe AA1 IO G1VDD — D1_MBA0 Bank Select T8 O G1VDD — D1_MBA1 Bank Select T5 O G1VDD — D1_MBA2 Bank Select AA6 O G1VDD — D1_MA00 Address U7 O G1VDD — D1_MA01 Address T6 O G1VDD — D1_MA02 Address T4 O G1VDD — D1_MA03 Address V9 O G1VDD — D1_MA04 Address V8 O G1VDD — D1_MA05 Address T2 O G1VDD — D1_MA06 Address W4 O G1VDD — D1_MA07 Address W5 O G1VDD — D1_MA08 Address W3 O G1VDD — D1_MA09 Address W6 O G1VDD — D1_MA10 Address U8 O G1VDD — D1_MA11 Address W8 O G1VDD — D1_MA12 Address W7 O G1VDD — D1_MA13 Address N9 O G1VDD — D1_MA14 Address AA9 O G1VDD — D1_MA15 Address Y9 O G1VDD — D1_MWE_B Write Enable N7 O G1VDD — D1_MRAS_B Row Address Strobe P8 O G1VDD — D1_MCAS_B Column Address Strobe R8 O G1VDD — D1_MCS0_B Chip Select T9 O G1VDD — D1_MCS1_B Chip Select P9 O G1VDD — D1_MCS2_B Chip Select R7 O G1VDD — D1_MCS3_B Chip Select L9 O G1VDD — D1_MCKE0 Clock Enable AA7 O G1VDD 10 D1_MCKE1 Clock Enable AA8 O G1VDD 10 D1_MCKE2 Clock Enable Y8 O G1VDD 10 D1_MCKE3 Clock Enable Y6 O G1VDD 10 D1_MCK0 Clock V1 O G1VDD — D1_MCK1 Clock V4 O G1VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 12 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes D1_MCK2 Clock U1 O G1VDD — D1_MCK3 Clock U4 O G1VDD — D1_MCK0_B Clock Complements V2 O G1VDD — D1_MCK1_B Clock Complements V5 O G1VDD — D1_MCK2_B Clock Complements U2 O G1VDD — D1_MCK3_B Clock Complements U5 O G1VDD — D1_DDRCLK DDR Clock - Controller 1 AD12 I OVDD — D1_MODT0 On Die Termination M7 O G1VDD 10 D1_MODT1 On Die Termination K8 O G1VDD 10 D1_MODT2 On Die Termination N8 O G1VDD 10 D1_MODT3 On Die Termination M8 O G1VDD 10 D1_MDIC0 Driver Impedance Calibration W2 IO G1VDD 1 D1_MDIC1 Driver Impedance Calibration V7 IO G1VDD 1 DDR SDRAM memory Interface 2 D2_MDQ00 Data AF26 IO G2VDD — D2_MDQ01 Data AE26 IO G2VDD — D2_MDQ02 Data AG27 IO G2VDD — D2_MDQ03 Data AF29 IO G2VDD — D2_MDQ04 Data AE27 IO G2VDD — D2_MDQ05 Data AG28 IO G2VDD — D2_MDQ06 Data AF27 IO G2VDD — D2_MDQ07 Data AH28 IO G2VDD — D2_MDQ08 Data AH29 IO G2VDD — D2_MDQ09 Data AJ29 IO G2VDD — D2_MDQ10 Data AK30 IO G2VDD — D2_MDQ11 Data AJ32 IO G2VDD — D2_MDQ12 Data AJ30 IO G2VDD — D2_MDQ13 Data AH30 IO G2VDD — D2_MDQ14 Data AJ31 IO G2VDD — D2_MDQ15 Data AL31 IO G2VDD — D2_MDQ16 Data AF30 IO G2VDD — D2_MDQ17 Data AG30 IO G2VDD — D2_MDQ18 Data AG31 IO G2VDD — D2_MDQ19 Data AD31 IO G2VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 13 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes D2_MDQ20 Data AG32 IO G2VDD — D2_MDQ21 Data AE32 IO G2VDD — D2_MDQ22 Data AD30 IO G2VDD — D2_MDQ23 Data AE30 IO G2VDD — D2_MDQ24 Data AD27 IO G2VDD — D2_MDQ25 Data AD26 IO G2VDD — D2_MDQ26 Data AB26 IO G2VDD — D2_MDQ27 Data AB27 IO G2VDD — D2_MDQ28 Data AD28 IO G2VDD — D2_MDQ29 Data AB29 IO G2VDD — D2_MDQ30 Data AA29 IO G2VDD — D2_MDQ31 Data AC29 IO G2VDD — D2_MDQ32 Data R32 IO G2VDD — D2_MDQ33 Data N32 IO G2VDD — D2_MDQ34 Data M31 IO G2VDD — D2_MDQ35 Data M32 IO G2VDD — D2_MDQ36 Data R30 IO G2VDD — D2_MDQ37 Data M30 IO G2VDD — D2_MDQ38 Data R29 IO G2VDD — D2_MDQ39 Data P30 IO G2VDD — D2_MDQ40 Data P28 IO G2VDD — D2_MDQ41 Data M29 IO G2VDD — D2_MDQ42 Data M28 IO G2VDD — D2_MDQ43 Data L30 IO G2VDD — D2_MDQ44 Data R28 IO G2VDD — D2_MDQ45 Data L27 IO G2VDD — D2_MDQ46 Data P27 IO G2VDD — D2_MDQ47 Data L28 IO G2VDD — D2_MDQ48 Data L32 IO G2VDD — D2_MDQ49 Data L31 IO G2VDD — D2_MDQ50 Data K32 IO G2VDD — D2_MDQ51 Data H32 IO G2VDD — D2_MDQ52 Data H31 IO G2VDD — D2_MDQ53 Data K30 IO G2VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 14 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes D2_MDQ54 Data K29 IO G2VDD — D2_MDQ55 Data H30 IO G2VDD — D2_MDQ56 Data G30 IO G2VDD — D2_MDQ57 Data K27 IO G2VDD — D2_MDQ58 Data G29 IO G2VDD — D2_MDQ59 Data G31 IO G2VDD — D2_MDQ60 Data H28 IO G2VDD — D2_MDQ61 Data K26 IO G2VDD — D2_MDQ62 Data L26 IO G2VDD — D2_MDQ63 Data H27 IO G2VDD — D2_MECC0 Error Correcting Code Y28 IO G2VDD — D2_MECC1 Error Correcting Code AC30 IO G2VDD — D2_MECC2 Error Correcting Code AB30 IO G2VDD — D2_MECC3 Error Correcting Code Y32 IO G2VDD — D2_MECC4 Error Correcting Code AC31 IO G2VDD — D2_MECC5 Error Correcting Code AC32 IO G2VDD — D2_MECC6 Error Correcting Code AA30 IO G2VDD — D2_MECC7 Error Correcting Code Y30 IO G2VDD — D2_MAPAR_ERR_B Address Parity Error T30 I G2VDD 26 D2_MAPAR_OUT Address Parity Out T26 O G2VDD 2 D2_MDM0 Data Mask AG29 O G2VDD 2 D2_MDM1 Data Mask AH32 O G2VDD 2 D2_MDM2 Data Mask AD32 O G2VDD 2 D2_MDM3 Data Mask AA28 O G2VDD 2 D2_MDM4 Data Mask N30 O G2VDD 2 D2_MDM5 Data Mask N27 O G2VDD 2 D2_MDM6 Data Mask J30 O G2VDD 2 D2_MDM7 Data Mask K28 O G2VDD 2 D2_MDM8 Data Mask AB32 O G2VDD 2 D2_MDQS0 Data Strobe AE28 IO G2VDD — D2_MDQS1 Data Strobe AK31 IO G2VDD — D2_MDQS2 Data Strobe AF31 IO G2VDD — D2_MDQS3 Data Strobe AC27 IO G2VDD — D2_MDQS4 Data Strobe P32 IO G2VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 15 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes D2_MDQS5 Data Strobe N29 IO G2VDD — D2_MDQS6 Data Strobe J32 IO G2VDD — D2_MDQS7 Data Strobe J29 IO G2VDD — D2_MDQS8 Data Strobe AA31 IO G2VDD — D2_MDQS0_B Data Strobe AE29 IO G2VDD — D2_MDQS1_B Data Strobe AK32 IO G2VDD — D2_MDQS2_B Data Strobe AF32 IO G2VDD — D2_MDQS3_B Data Strobe AC28 IO G2VDD — D2_MDQS4_B Data Strobe P31 IO G2VDD — D2_MDQS5_B Data Strobe N28 IO G2VDD — D2_MDQS6_B Data Strobe J31 IO G2VDD — D2_MDQS7_B Data Strobe J28 IO G2VDD — D2_MDQS8_B Data Strobe AA32 IO G2VDD — D2_MBA0 Bank Select T25 O G2VDD — D2_MBA1 Bank Select T28 O G2VDD — D2_MBA2 Bank Select AA27 O G2VDD — D2_MA00 Address U26 O G2VDD — D2_MA01 Address T27 O G2VDD — D2_MA02 Address T29 O G2VDD — D2_MA03 Address V24 O G2VDD — D2_MA04 Address V25 O G2VDD — D2_MA05 Address T31 O G2VDD — D2_MA06 Address W29 O G2VDD — D2_MA07 Address W28 O G2VDD — D2_MA08 Address W30 O G2VDD — D2_MA09 Address W27 O G2VDD — D2_MA10 Address U25 O G2VDD — D2_MA11 Address W25 O G2VDD — D2_MA12 Address W26 O G2VDD — D2_MA13 Address N24 O G2VDD — D2_MA14 Address AA24 O G2VDD — D2_MA15 Address Y24 O G2VDD — D2_MWE_B Write Enable N26 O G2VDD — D2_MRAS_B Row Address Strobe P25 O G2VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 16 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes D2_MCAS_B Column Address Strobe R25 O G2VDD — D2_MCS0_B Chip Select T24 O G2VDD — D2_MCS1_B Chip Select P24 O G2VDD — D2_MCS2_B Chip Select R26 O G2VDD — D2_MCS3_B Chip Select L24 O G2VDD — D2_MCKE0 Clock Enable AA26 O G2VDD 10 D2_MCKE1 Clock Enable AA25 O G2VDD 10 D2_MCKE2 Clock Enable Y25 O G2VDD 10 D2_MCKE3 Clock Enable Y27 O G2VDD 10 D2_MCK0 Clock V32 O G2VDD — D2_MCK1 Clock V29 O G2VDD — D2_MCK2 Clock U32 O G2VDD — D2_MCK3 Clock U29 O G2VDD — D2_MCK0_B Clock Complements V31 O G2VDD — D2_MCK1_B Clock Complements V28 O G2VDD — D2_MCK2_B Clock Complements U31 O G2VDD — D2_MCK3_B Clock Complements U28 O G2VDD — D2_DDRCLK DDR Clock–Controller 2 AD21 I OVDD — D2_MODT0 On Die Termination M26 O G2VDD 10 D2_MODT1 On Die Termination K25 O G2VDD 10 D2_MODT2 On Die Termination N25 O G2VDD 10 D2_MODT3 On Die Termination M25 O G2VDD 10 D2_MDIC0 Driver Impedance Calibration W31 IO G2VDD 1 D2_MDIC1 Driver Impedance Calibration V26 IO G2VDD 1 Integrated Flash Controller Interface IFC_AD00/CFG_GPINPUT0 Muxed Data/Address AG12 IO OVDD 22 IFC_AD01/CFG_GPINPUT1 Muxed Data/Address AG13 IO OVDD 22 IFC_AD02/CFG_GPINPUT2 Muxed Data/Address AF13 IO OVDD 22 IFC_AD03/CFG_GPINPUT3 Muxed Data/Address AF19 IO OVDD 22 IFC_AD04/CFG_GPINPUT4 Muxed Data/Address AH15 IO OVDD 22 IFC_AD05/CFG_GPINPUT5 Muxed Data/Address AL13 IO OVDD 22 IFC_AD06/CFG_GPINPUT6 Muxed Data/Address AL17 IO OVDD 22 IFC_AD07/CFG_GPINPUT7 Muxed Data/Address AK18 IO OVDD 22 IFC_AD08/CFG_RCW_SRC0 Muxed Data/Address AF14 IO OVDD 22 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 17 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes IFC_AD09/CFG_RCW_SRC1 Muxed Data/Address AF15 IO OVDD 22 IFC_AD10/CFG_RCW_SRC2 Muxed Data/Address AF16 IO OVDD 22 IFC_AD11/CFG_RCW_SRC3 Muxed Data/Address AH16 IO OVDD 22 IFC_AD12/CFG_RCW_SRC4 Muxed Data/Address AF17 IO OVDD 22 IFC_AD13/CFG_RCW_SRC5 Muxed Data/Address AF18 IO OVDD 22 IFC_AD14/CFG_RCW_SRC6 Muxed Data/Address AH19 IO OVDD 22 IFC_AD15/CFG_RCW_SRC7 Muxed Data/Address AG18 IO OVDD 22 IFC_A16 Address AG15 O OVDD 2, 8 IFC_A17 Address AH14 O OVDD 2, 8 IFC_A18 Address AG16 O OVDD 2, 8 IFC_A19 Address AH18 O OVDD 2, 8 IFC_A20 Address AH17 O OVDD 2, 8 IFC_A21/CFG_DRAM_TYPE Address AG19 O OVDD 2, 22, 23 IFC_A22/IFC_WP1_B Address AJ20 O OVDD 2, IFC_A23/IFC_WP2_B Address AK17 O OVDD 2, IFC_A24/IFC_WP3_B Address AH12 O OVDD 2, IFC_A25/GPIO2[25]/ IFC_RB2_B/IFC_FCTA2 Address AJ14 O OVDD 2 IFC_A26/GPIO2[26]/ IFC_RB3_B/IFC_FCTA3 Address AJ15 O OVDD 2 IFC_A27/GPIO2[27] Address AJ17 O OVDD 2 IFC_PAR0/GPIO2[13] Data Parity / Address and Data Parity for byte 0 AH13 IO OVDD — IFC_PAR1/GPIO2[14] Data Parity / Address and Data Parity for byte 1 AJ12 IO OVDD — IFC_CS0_B Chip Select AK15 O OVDD 2, 27 IFC_CS1_B/GPIO2[10] Chip Select AK13 O OVDD 2, 27 IFC_CS2_B/GPIO2[11] Chip Select AK14 O OVDD 2, 27 IFC_CS3_B/GPIO2[12] Chip Select AJ18 O OVDD 2, 27 IFC_WE_B/IFC_WBE0 Write Enable (NAND/NOR) AK12 IO OVDD 2, 8 IFC_WE_B/IFC_WBE0 Write byte 0 enable (GPCM) AK12 IO OVDD 2, 8 IFC_CLE/IFC_WBE1/ CFG_RCW_SRC8 Write byte 1 enable (GPCM) AM14 IO OVDD 22 IFC_BCTL External Buffer control AL16 O OVDD 2 IFC_TE/CFG_IFC_TE External Transceiver Enable AM16 O OVDD 2, 22, 25 B4860 QorIQ Qonverge Data Sheet, Rev. 3 18 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes IFC_AVD/IFC_ALE/ CFG_RSP_DIS Address Latch Enable– NAND/NOR & GPCM (NAND) AL19 IO OVDD 22, 15 IFC_AVD/IFC_ALE/ CFG_RSP_DIS Address Valid Data for internal latched based NOR AL19 IO OVDD 22, 15 IFC_CLE/IFC_WBE1/ CFG_RCW_SRC8 Command Latch Enable (NAND) AM14 IO OVDD 22 IFC_OE_B/IFC_RE_B Output Enable–NOR & GPCM AK16 IO OVDD 8 IFC_OE_B/IFC_RE_B Read Enable–NAND AK16 IO OVDD 8 IFC_WP0_B NAND write protect signal 0 AL14 O OVDD 8 IFC_A22/IFC_WP1_B NAND write protect signal 1 AJ20 IO OVDD — IFC_A23/IFC_WP2_B NAND write protect signal 2 AK17 IO OVDD — IFC_A24/IFC_WP3_B NAND write protect signal 3 AH12 IO OVDD — IFC_RB0_B/IFC_FCTA0 CS0: NAND/NOR Flash Ready Busy AM15 I OVDD 2, 28 IFC_RB1_B/IFC_FCTA1 CS1: NAND/NOR Flash Ready Busy AM17 I OVDD 2, 28 IFC_A25/GPIO2[25]/ IFC_RB2_B/IFC_FCTA2 CS2: NAND/NOR Flash Ready Busy AJ14 I OVDD 2 IFC_A26/GPIO2[26]/ IFC_RB3_B/IFC_FCTA3 CS3: NAND/NOR Flash Ready Busy AJ15 I OVDD 2 IFC_RB0_B/IFC_FCTA0 CS0: GPCM External Access Termination AM15 I OVDD 2, 28 IFC_RB1_B/IFC_FCTA1 CS1: GPCM External Access Termination AM17 I OVDD 2, 28 IFC_A25/GPIO2[25]/ IFC_RB2_B/IFC_FCTA2 CS2: GPCM External Access Termination AJ14 I OVDD 2 IFC_A26/GPIO2[26]/ IFC_RB3_B/IFC_FCTA3 CS3: GPCM External Access Termination AJ15 I OVDD 2 IFC_CLK0 Clock AM18 O OVDD 2 IFC_CLK1 Clock AM19 O OVDD 2 DUART Interface UART1_SOUT/GPIO1[15]/ CP_LOS4 Transmit Data AL29 O DVDD 2 UART1_SIN/GPIO1[17]/ CP_LOS5 Receive Data AM28 I DVDD 2 UART1_RTS_B/GPIO1[19]/ UART3_SOUT/CP_LOS6 Ready to Send AF24 O DVDD 2 UART1_CTS_B/GPIO1[21]/ UART3_SIN/CP_LOS7 Clear to Send AE24 I DVDD 2 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 19 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes UART2_SOUT/GPIO1[16] Transmit Data AF25 O DVDD 2 UART2_SIN/GPIO1[18] Receive Data AH26 I DVDD 2 UART2_RTS_B/GPIO1[20]/ UART4_SOUT Ready to Send AG25 O DVDD 2 UART2_CTS_B/GPIO1[22]/ UART4_SIN Clear to Send AK28 I DVDD 2 UART1_RTS_B/GPIO1[19]/ UART3_SOUT/CP_LOS6 Transmit Data AF24 O DVDD 2 UART1_CTS_B/GPIO1[21]/ UART3_SIN/CP_LOS7 Receive Data AE24 I DVDD 2 UART2_RTS_B/GPIO1[20]/ UART4_SOUT Transmit Data AG25 O DVDD 2 UART2_CTS_B/GPIO1[22]/ UART4_SIN Receive Data AK28 I DVDD 2 I2C Interface IIC1_SCL Serial Clock (supports PBL) AH27 IO DVDD 4 IIC1_SDA Serial Data (supports PBL) AH25 IO DVDD 4 IIC2_SCL Serial Clock AE23 IO DVDD 4 IIC2_SDA Serial Data AG24 IO DVDD 4 IIC3_SCL/GPIO3[3] Serial Clock AM30 IO DVDD 4 IIC3_SDA/GPIO3[4] Serial Data AK29 IO DVDD 4 IIC4_SCL/GPIO3[5]/EVT5_B Serial Clock AJ27 IO DVDD 4 IIC4_SDA/GPIO3[6]/EVT6_B/ USB_PWRFAULT Serial Data AE25 IO DVDD 4 eSPI Interface SPI_MOSI Master Out Slave In AM21 IO OVDD — SPI_MISO Master In Slave Out AL20 I OVDD — SPI_CLK Clock AG21 O OVDD 2 SPI_CS0_B/GPIO2[0]/ SDHC_DAT4 Chip Select AJ21 O OVDD 2 SPI_CS1_B/GPIO2[1]/ SDHC_DAT5 Chip Select AK19 O OVDD 2 SPI_CS2_B/GPIO2[2]/ SDHC_DAT6 Chip Select AH20 O OVDD 2 SPI_CS3_B/GPIO2[3]/ SDHC_DAT7 Chip Select AM20 O OVDD 2 eSDHC Interface B4860 QorIQ Qonverge Data Sheet, Rev. 3 20 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes SDHC_CMD/GPIO2[4] Command/Response AK20 IO OVDD 32 SDHC_DAT0/GPIO2[5] Data AG22 IO OVDD 32 SDHC_DAT1/GPIO2[6] Data AH21 IO OVDD 32 SDHC_DAT2/GPIO2[7] Data AL22 IO OVDD 32 SDHC_DAT3/GPIO2[8] Data AF21 IO OVDD 32 SPI_CS0_B/GPIO2[0]/ SDHC_DAT4 Data AJ21 IO OVDD 32 SPI_CS1_B/GPIO2[1]/ SDHC_DAT5 Data AK19 IO OVDD 32 SPI_CS2_B/GPIO2[2]/ SDHC_DAT6 Data AH20 IO OVDD 32 SPI_CS3_B/GPIO2[3]/ SDHC_DAT7 Data AM20 IO OVDD 32 SDHC_CLK/GPIO2[9] Host to Card Clock AM22 O OVDD 2 Programmable Interrupt Controller Interface IRQ00 External Interrupts AF23 I OVDD 2 IRQ01 External Interrupts AF22 I OVDD 2 IRQ02 External Interrupts AH22 I OVDD 2 IRQ03/GPIO1[23] External Interrupts AH23 I OVDD 2 IRQ04/GPIO1[24] External Interrupts AH24 I OVDD 2 IRQ05/GPIO1[25] External Interrupts AK23 I OVDD 2 IRQ06/GPIO1[26]/TMR0 External Interrupts AK21 I OVDD 2 IRQ07/GPIO1[27]/TMR1 External Interrupts AK24 I OVDD 2 IRQ08/GPIO1[28]/TMR2 External Interrupts AK22 I OVDD 2 IRQ09/GPIO1[29]/TMR3 External Interrupts AM24 I OVDD 2 IRQ10/GPIO1[30]/TMR4 External Interrupts AJ24 I OVDD 2 IRQ11/GPIO1[31]/TMR5 External Interrupts AL23 I OVDD 2 IRQ_OUT_B/EVT9_B Interrupt Output AJ23 O OVDD 2, 5 AF20 I OVDD 2, 6 E1 I QVDD 7 Trust TMP_DETECT_B Tamper Detect System Control PORESET_B Power On Reset HRESET_B Hard Reset AM12 IO OVDD 3 RESET_REQ_B Reset Request (POR or Hard) AM9 O OVDD 2, 8 Power Management B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 21 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description ASLEEP/GPIO1[13]/CFG_XVDD_ Asleep SEL Package Pin Type Pin Power Supply Notes O OVDD 2, 22, 24 F1 I QVDD 7 AM23 I OVDD 2 AK10 Clock Signals SYSCLK System Clock RTC/GPIO1[14] Real Time Clock Debug Signals EVT0_B Event 0 AE10 I OVDD 9 EVT1_B Event 1 AE11 IO OVDD — EVT2_B Event 2 AH11 IO OVDD — EVT3_B Event 3 AJ11 IO OVDD — EVT4_B Event 4 AF12 IO OVDD — IIC4_SCL/GPIO3[5]/EVT5_B Event 5 AJ27 IO DVDD — IIC4_SDA/GPIO3[6]/EVT6_B/ USB_PWRFAULT Event 6 AE25 IO DVDD — DMA1_DACK0_B/GPIO3[1]/ EVT7_B/TMR6 Event 7 AL7 IO OVDD — DMA1_DDONE0_B/GPIO3[2]/ EVT8_B/TMR7 Event 8 AM7 IO OVDD — IRQ_OUT_B/EVT9_B Event 9 AJ23 IO OVDD — CKSTP_OUT_B Checkstop Out AK11 O OVDD 2, 3 CLK_OUT Clock Out AM13 O OVDD 10 JTAG Signals TCK Test Clock AL26 I OVDD — TDI Test Data In AM26 I OVDD 9 TDO Test Data Out AL25 O OVDD 10 TMS Test Mode Select AM25 I OVDD 9 TRST_B Test Reset AK25 I OVDD 9 SerDes 1 (x8) CPRI, Aurora, 1GE, 2.5GE SD1_TX0 SerDes Tx Data (pos) D19 O XVDD — SD1_TX1 SerDes Tx Data (pos) D20 O XVDD — SD1_TX2 SerDes Tx Data (pos) D22 O XVDD — SD1_TX3 SerDes Tx Data (pos) D23 O XVDD — SD1_TX4 SerDes Tx Data (pos) D25 O XVDD — SD1_TX5 SerDes Tx Data (pos) D26 O XVDD — SD1_TX6 SerDes Tx Data (pos) D28 O XVDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 22 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes SD1_TX7 SerDes Tx Data (pos) D29 O XVDD — SD1_TX0_B SerDes Tx Data (neg) E19 O XVDD — SD1_TX1_B SerDes Tx Data (neg) E20 O XVDD — SD1_TX2_B SerDes Tx Data (neg) E22 O XVDD — SD1_TX3_B SerDes Tx Data (neg) E23 O XVDD — SD1_TX4_B SerDes Tx Data (neg) E25 O XVDD — SD1_TX5_B SerDes Tx Data (neg) E26 O XVDD — SD1_TX6_B SerDes Tx Data (neg) E28 O XVDD — SD1_TX7_B SerDes Tx Data (neg) E29 O XVDD — SD1_RX0 SerDes Rx Data (pos) A19 I SVDD — SD1_RX1 SerDes Rx Data (pos) A20 I SVDD — SD1_RX2 SerDes Rx Data (pos) A24 I SVDD — SD1_RX3 SerDes Rx Data (pos) A26 I SVDD — SD1_RX4 SerDes Rx Data (pos) A27 I SVDD — SD1_RX5 SerDes Rx Data (pos) A29 I SVDD — SD1_RX6 SerDes Rx Data (pos) A30 I SVDD — SD1_RX7 SerDes Rx Data (pos) C32 I SVDD — SD1_RX0_B SerDes Rx Data (neg) B19 I SVDD — SD1_RX1_B SerDes Rx Data (neg) B20 I SVDD — SD1_RX2_B SerDes Rx Data (neg) B24 I SVDD — SD1_RX3_B SerDes Rx Data (neg) B26 I SVDD — SD1_RX4_B SerDes Rx Data (neg) B27 I SVDD — SD1_RX5_B SerDes Rx Data (neg) B29 I SVDD — SD1_RX6_B SerDes Rx Data (neg) B30 I SVDD — SD1_RX7_B SerDes Rx Data (neg) C31 I SVDD — SD1_REF1_CLK SerDes PLL 1 Reference Clock B22 I SVDD — SD1_REF1_CLK_B SerDes PLL 1 Reference Clock Complement A22 I SVDD — SD1_REF2_CLK SerDes PLL 2 Reference Clock E31 I SVDD — SD1_REF2_CLK_B SerDes PLL 2 Reference Clock Complement E32 I SVDD — SD1_IMP_CAL_TX SerDes Tx Impedance Calibration G26 I XVDD 11 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 23 Pin assignments Table 1. Pinout list by bus (continued) Signal SD1_IMP_CAL_RX Signal Description SerDes Rx Impedance Calibration Package Pin Type Pin G20 I Power Supply Notes SVDD 12 SerDes 2 (x8) PCIe, sRIO, Aurora, 10GE, 1GE, 2.5GE SD2_TX0 SerDes Tx Data (pos) D17 O XVDD — SD2_TX1 SerDes Tx Data (pos) D16 O XVDD — SD2_TX2 SerDes Tx Data (pos) D14 O XVDD — SD2_TX3 SerDes Tx Data (pos) D13 O XVDD — SD2_TX4 SerDes Tx Data (pos) D11 O XVDD — SD2_TX5 SerDes Tx Data (pos) D10 O XVDD — SD2_TX6 SerDes Tx Data (pos) D8 O XVDD — SD2_TX7 SerDes Tx Data (pos) D7 O XVDD — SD2_TX0_B SerDes Tx Data (neg) E17 O XVDD — SD2_TX1_B SerDes Tx Data (neg) E16 O XVDD — SD2_TX2_B SerDes Tx Data (neg) E14 O XVDD — SD2_TX3_B SerDes Tx Data (neg) E13 O XVDD — SD2_TX4_B SerDes Tx Data (neg) E11 O XVDD — SD2_TX5_B SerDes Tx Data (neg) E10 O XVDD — SD2_TX6_B SerDes Tx Data (neg) E8 O XVDD — SD2_TX7_B SerDes Tx Data (neg) E7 O XVDD — SD2_RX0 SerDes Rx Data (pos) A17 I SVDD — SD2_RX1 SerDes Rx Data (pos) A16 I SVDD — SD2_RX2 SerDes Rx Data (pos) A12 I SVDD — SD2_RX3 SerDes Rx Data (pos) A11 I SVDD — SD2_RX4 SerDes Rx Data (pos) A9 I SVDD — SD2_RX5 SerDes Rx Data (pos) A8 I SVDD — SD2_RX6 SerDes Rx Data (pos) A6 I SVDD — SD2_RX7 SerDes Rx Data (pos) A5 I SVDD — SD2_RX0_B SerDes Rx Data (neg) B17 I SVDD — SD2_RX1_B SerDes Rx Data (neg) B16 I SVDD — SD2_RX2_B SerDes Rx Data (neg) B12 I SVDD — SD2_RX3_B SerDes Rx Data (neg) B11 I SVDD — SD2_RX4_B SerDes Rx Data (neg) B9 I SVDD — SD2_RX5_B SerDes Rx Data (neg) B8 I SVDD — SD2_RX6_B SerDes Rx Data (neg) B6 I SVDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 24 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes SD2_RX7_B SerDes Rx Data (neg) B5 I SVDD — SD2_REF1_CLK SerDes PLL 1 Reference Clock B14 I SVDD — SD2_REF1_CLK_B SerDes PLL 1 Reference Clock Complement A14 I SVDD — SD2_REF2_CLK SerDes PLL 2 Reference Clock E5 I SVDD — SD2_REF2_CLK_B SerDes PLL 2 Reference Clock Complement D5 I SVDD — SD2_IMP_CAL_TX SerDes Tx Impedance Calibration G10 I XVDD 11 SD2_IMP_CAL_RX SerDes Rx Impedance Calibration G18 I SVDD 12 CPRI Interface CP_SYNC0 Sync AJ9 IO OVDD — CP_SYNC1 Sync AF11 IO OVDD — CP_SYNC2 Sync AG10 IO OVDD — CP_SYNC3 Sync AH10 IO OVDD — CP_SYNC4 Sync AL8 IO OVDD — CP_SYNC5 Sync AK8 IO OVDD — CP_SYNC6 Sync AK9 IO OVDD — CP_SYNC7 Sync AH9 IO OVDD — CP_RCLK0 Reconstructed Clock AL10 O OVDD 2 CP_RCLK1 Reconstructed Clock AL11 O OVDD 2 CP_RCLK0_B Reconstructed Clock Complement AM10 O OVDD 2 CP_RCLK1_B Reconstructed Clock Complement AM11 O OVDD 2 CP_LOS0 Loss Of Signal AM29 I DVDD 2, 29 CP_LOS1 Loss Of Signal AK27 I DVDD 2, 29 CP_LOS2 Loss Of Signal AM27 I DVDD 2, 29 CP_LOS3 Loss Of Signal AL28 I DVDD 2, 29 UART1_SOUT/GPIO1[15]/ CP_LOS4 Loss Of Signal AL29 I DVDD 2, 30 UART1_SIN/GPIO1[17]/ CP_LOS5 Loss Of Signal AM28 I DVDD 2, 30 UART1_RTS_B/GPIO1[19]/ UART3_SOUT/CP_LOS6 Loss Of Signal AF24 I DVDD 2, 30 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 25 Pin assignments Table 1. Pinout list by bus (continued) Signal UART1_CTS_B/GPIO1[21]/ UART3_SIN/CP_LOS7 Signal Description Loss Of Signal Package Pin Type Pin AE24 Power Supply Notes I DVDD 2, 30 IEEE 1588 Interface TSEC_1588_CLK_IN Clock In AM3 I OVDD 2 TSEC_1588_TRIG_IN1 Trigger In 1 AE9 I OVDD 2 TSEC_1588_TRIG_IN2 Trigger In 2 AF10 I OVDD 2 TSEC_1588_ALARM_OUT1 Alarm Out 1 AG9 O OVDD 2 TSEC_1588_ALARM_OUT2 Alarm Out 2 AH8 O OVDD 2 TSEC_1588_CLK_OUT Clock Out AE8 O OVDD 2 TSEC_1588_PULSE_OUT1 Pulse Out 1 AF9 O OVDD 2 TSEC_1588_PULSE_OUT2 Pulse Out 2 AK7 O OVDD 2 Ethernet MII Management Interface 1 EMI1_MDC Management Data Clock AJ26 O DVDD 2 EMI1_MDIO Management Data In/Out AK26 IO DVDD 27 Ethernet MII Management Interface 2 EMI2_MDC Management Data Clock AM8 O OVDD 13, 14 EMI2_MDIO Management Data In/Out AJ8 IO OVDD 13, 14 USB ULPI Interface USB_D7 Data AK4 IO OVDD — USB_D6 Data AM4 IO OVDD — USB_D5 Data AK6 IO OVDD — USB_D4 Data AK5 IO OVDD — USB_D3 Data AJ6 IO OVDD — USB_D2 Data AH7 IO OVDD — USB_D1 Data AG7 IO OVDD — USB_D0 Data AF8 IO OVDD — USB_STP Stop Data AH6 O OVDD 2 USB_CLK Clock AL4 I OVDD 2 USB_NXT Next Data AL5 I OVDD 2 USB_DIR Data Direction AM5 I OVDD 2 IIC4_SDA/GPIO3[6]/EVT6_B/ USB_PWRFAULT Overcurrent Status on VBUS line AE25 I DVDD — I OVDD 2 DMA Interface DMA1_DREQ0_B/GPIO3[0] DMA1 channel 0 request AM6 B4860 QorIQ Qonverge Data Sheet, Rev. 3 26 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes DMA1_DACK0_B/GPIO3[1]/ EVT7_B/TMR6 DMA1 channel 0 acknowledge AL7 O OVDD 2 DMA1_DDONE0_B/GPIO3[2]/ EVT8_B/TMR7 DMA1 channel 0 done AM7 O OVDD 2 GPIO Signals ASLEEP/GPIO1[13]/ CFG_XVDD_SEL General Purpose Output AK10 O OVDD 2 RTC/GPIO1[14] General Purpose Input / Output AM23 IO OVDD — UART1_SOUT/GPIO1[15]/ CP_LOS4 General Purpose Input / Output AL29 IO DVDD — UART2_SOUT/GPIO1[16] General Purpose Input / Output AF25 IO DVDD — UART1_SIN/GPIO1[17]/ CP_LOS5 General Purpose Input / Output AM28 IO DVDD — UART2_SIN/GPIO1[18] General Purpose Input / Output AH26 IO DVDD — UART1_RTS_B/GPIO1[19]/ UART3_SOUT/CP_LOS6 General Purpose Input / Output AF24 IO DVDD — UART2_RTS_B/GPIO1[20]/ UART4_SOUT General Purpose Input / Output AG25 IO DVDD — UART1_CTS_B/GPIO1[21]/ UART3_SIN/CP_LOS7 General Purpose Input / Output AE24 IO DVDD — UART2_CTS_B/GPIO1[22]/ UART4_SIN General Purpose Input / Output AK28 IO DVDD — IRQ03/GPIO1[23] General Purpose Input / Output AH23 IO OVDD — IRQ04/GPIO1[24] General Purpose Input / Output AH24 IO OVDD — IRQ05/GPIO1[25] General Purpose Input / Output AK23 IO OVDD — IRQ06/GPIO1[26]/TMR0 General Purpose Input / Output AK21 IO OVDD — IRQ07/GPIO1[27]/TMR1 General Purpose Input / Output AK24 IO OVDD — IRQ08/GPIO1[28]/TMR2 General Purpose Input / Output AK22 IO OVDD — IRQ09/GPIO1[29]/TMR3 General Purpose Input / Output AM24 IO OVDD — IRQ10/GPIO1[30]/TMR4 General Purpose Input / Output AJ24 IO OVDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 27 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes IRQ11/GPIO1[31]/TMR5 General Purpose Input / Output AL23 IO OVDD — SPI_CS0_B/GPIO2[0]/ SDHC_DAT4 General Purpose Input / Output AJ21 IO OVDD — SPI_CS1_B/GPIO2[1]/ SDHC_DAT5 General Purpose Input / Output AK19 IO OVDD — SPI_CS2_B/GPIO2[2]/ SDHC_DAT6 General Purpose Input / Output AH20 IO OVDD — SPI_CS3_B/GPIO2[3]/ SDHC_DAT7 General Purpose Input / Output AM20 IO OVDD — SDHC_CMD/GPIO2[4] General Purpose Input / Output AK20 IO OVDD — SDHC_DAT0/GPIO2[5] General Purpose Input / Output AG22 IO OVDD — SDHC_DAT1/GPIO2[6] General Purpose Input / Output AH21 IO OVDD — SDHC_DAT2/GPIO2[7] General Purpose Input / Output AL22 IO OVDD — SDHC_DAT3/GPIO2[8] General Purpose Input / Output AF21 IO OVDD — SDHC_CLK/GPIO2[9] General Purpose Input / Output AM22 IO OVDD — IFC_CS1_B/GPIO2[10] General Purpose Input / Output AK13 IO OVDD — IFC_CS2_B/GPIO2[11] General Purpose Input / Output AK14 IO OVDD — IFC_CS3_B/GPIO2[12] General Purpose Input / Output AJ18 IO OVDD — IFC_PAR0/GPIO2[13] General Purpose Input / Output AH13 IO OVDD — IFC_PAR1/GPIO2[14] General Purpose Input / Output AJ12 IO OVDD — IFC_A25/GPIO2[25]/ IFC_RB2_B/IFC_FCTA2 General Purpose Input / Output AJ14 IO OVDD — IFC_A26/GPIO2[26]/ IFC_RB3_B/IFC_FCTA3 General Purpose Input / Output AJ15 IO OVDD — IFC_A27/GPIO2[27] General Purpose Input / Output AJ17 IO OVDD — DMA1_DREQ0_B/GPIO3[0] General Purpose Input / Output AM6 IO OVDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 28 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes DMA1_DACK0_B/GPIO3[1]/ EVT7_B/TMR6 General Purpose Input / Output AL7 IO OVDD — DMA1_DDONE0_B/GPIO3[2]/ EVT8_B/TMR7 General Purpose Input / Output AM7 IO OVDD — IIC3_SCL/GPIO3[3] General Purpose Input / Output AM30 IO DVDD — IIC3_SDA/GPIO3[4] General Purpose Input / Output AK29 IO DVDD — IIC4_SCL/GPIO3[5]/EVT5_B General Purpose Input / Output AJ27 IO DVDD — IIC4_SDA/GPIO3[6]/EVT6_B/ USB_PWRFAULT General Purpose Input / Output AE25 IO DVDD — Timer Signals IRQ06/GPIO1[26]/TMR0 Timer Input / Output AK21 IO OVDD — IRQ07/GPIO1[27]/TMR1 Timer Input / Output AK24 IO OVDD — IRQ08/GPIO1[28]/TMR2 Timer Input / Output AK22 IO OVDD — IRQ09/GPIO1[29]/TMR3 Timer Input / Output AM24 IO OVDD — IRQ10/GPIO1[30]/TMR4 Timer Input / Output AJ24 IO OVDD — IRQ11/GPIO1[31]/TMR5 Timer Input / Output AL23 IO OVDD — DMA1_DACK0_B/GPIO3[1]/ EVT7_B/TMR6 Timer Input / Output AL7 IO OVDD — DMA1_DDONE0_B/GPIO3[2]/ EVT8_B/TMR7 Timer Input / Output AM7 IO OVDD — Analog Signals TD_ANODE Thermal diode anode J7 — Internal diode 31 TD_CATHODE Thermal diode cathode J8 — Internal diode 31 M1VREF SSTL 1.35/1.5 Reference Voltage AC9 — G1VDD/2 — M2VREF SSTL 1.35/1.5 Reference Voltage AC24 — G2VDD/2 — POVDD Fuse Programming Override Supply H11 — POVDD 16 Power-on-Reset Configuration Signals IFC_AD00/CFG_GPINPUT0 General-Purpose Input, application defined AG12 I OVDD 22 IFC_AD01/CFG_GPINPUT1 General-Purpose Input, application defined AG13 I OVDD 22 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 29 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes IFC_AD02/CFG_GPINPUT2 General-Purpose Input, application defined AF13 I OVDD 22 IFC_AD03/CFG_GPINPUT3 General-Purpose Input, application defined AF19 I OVDD 22 IFC_AD04/CFG_GPINPUT4 General-Purpose Input, application defined AH15 I OVDD 22 IFC_AD05/CFG_GPINPUT5 General-Purpose Input, application defined AL13 I OVDD 22 IFC_AD06/CFG_GPINPUT6 General-Purpose Input, application defined AL17 I OVDD 22 IFC_AD07/CFG_GPINPUT7 General-Purpose Input, application defined AK18 I OVDD 22 IFC_AD08/CFG_RCW_SRC0 RCW Source AF14 I OVDD 22 IFC_AD09/CFG_RCW_SRC1 RCW Source AF15 I OVDD 22 IFC_AD10/CFG_RCW_SRC2 RCW Source AF16 I OVDD 22 IFC_AD11/CFG_RCW_SRC3 RCW Source AH16 I OVDD 22 IFC_AD12/CFG_RCW_SRC4 RCW Source AF17 I OVDD 22 IFC_AD13/CFG_RCW_SRC5 RCW Source AF18 I OVDD 22 IFC_AD14/CFG_RCW_SRC6 RCW Source AH19 I OVDD 22 IFC_AD15/CFG_RCW_SRC7 RCW Source AG18 I OVDD 22 IFC_CLE/IFC_WBE1/ CFG_RCW_SRC8 RCW Source AM14 I OVDD 22 IFC_AVD/IFC_ALE/ CFG_RSP_DIS Reset Sequence Pause Disable AL19 I OVDD 22, 15 IFC_A21/CFG_DRAM_TYPE DRAM Type Select AG19 I OVDD 22, 23 ASLEEP/GPIO1[13]/ CFG_XVDD_SEL XVDD Voltage Select AK10 I OVDD 2, 22, 24 IFC_TE/CFG_IFC_TE IFC External Transceiver Enable Pin Polarity Select AM16 I OVDD 22, 25 Power and Ground Signals AVDD_CGA1 Cluster Group A PLL1 supply A3 — AVDD_CGA1 — AVDD_CGA2 Cluster Group A PLL2 supply C1 — AVDD_CGA2 — AVDD_CGB1 Cluster Group B PLL1 supply B2 — AVDD_CGB1 — AVDD_CGB2 Cluster Group B PLL2 supply C3 — AVDD_CGB2 — AVDD_PLAT Platform PLL supply B3 — AVDD_PLAT — AVDD_DDR1 DDR1 PLL supply AC8 — AVDD_DDR1 — AVDD_DDR2 DDR2 PLL supply AC25 — AVDD_DDR2 — B4860 QorIQ Qonverge Data Sheet, Rev. 3 30 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes AVDD_SRDS1_PLL1 SerDes1 PLL 1 supply H21 — AVDD_SRDS1_PLL1 — AVDD_SRDS1_PLL2 SerDes1 PLL 2 supply H24 — AVDD_SRDS1_PLL2 — AVDD_SRDS2_PLL1 SerDes2 PLL 1 supply H17 — AVDD_SRDS2_PLL1 — AVDD_SRDS2_PLL2 SerDes2 PLL 2 supply H14 — AVDD_SRDS2_PLL2 — SENSEVDD1 VDD sense pin 1 K9 — — 17 SENSEVDD2 VDD sense pin 2 AE12 — — 17 AGND_SRDS1_PLL1 SerDes1 PLL 1 GND H20 — — — AGND_SRDS1_PLL2 SerDes1 PLL 2 GND G24 — — — AGND_SRDS2_PLL1 SerDes2 PLL 1 GND H18 — — — AGND_SRDS2_PLL2 SerDes2 PLL 2 GND G14 — — — SENSEGND1 Vss sense pin 1 J9 — — 17 SENSEGND2 Vss sense pin 2 AD11 — — 17 OVDD General I/O supply AD13 — OVDD — OVDD General I/O supply AD15 — OVDD — OVDD General I/O supply AD17 — OVDD — OVDD General I/O supply AE14 — OVDD — OVDD General I/O supply AE16 — OVDD — OVDD General I/O supply AE18 — OVDD — DVDD UART/I2C/CPRI_LOS I/O supply AD19 — DVDD — DVDD UART/I2C/CPRI_LOS I/O supply AE20 — DVDD — G1VDD DDR supply for port 1 L8 — G1VDD — G1VDD DDR supply for port 1 P7 — G1VDD — G1VDD DDR supply for port 1 R9 — G1VDD — G1VDD DDR supply for port 1 T1 — G1VDD — G1VDD DDR supply for port 1 T10 — G1VDD — G1VDD DDR supply for port 1 U3 — G1VDD — G1VDD DDR supply for port 1 U6 — G1VDD — G1VDD DDR supply for port 1 U9 — G1VDD — G1VDD DDR supply for port 1 V3 — G1VDD — G1VDD DDR supply for port 1 V6 — G1VDD — G1VDD DDR supply for port 1 V10 — G1VDD — G1VDD DDR supply for port 1 W1 — G1VDD — G1VDD DDR supply for port 1 W9 — G1VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 31 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes G1VDD DDR supply for port 1 Y7 — G1VDD — G1VDD DDR supply for port 1 Y10 — G1VDD — G1VDD DDR supply for port 1 AA10 — G1VDD — G2VDD DDR supply for port 2 L25 — G2VDD — G2VDD DDR supply for port 2 P26 — G2VDD — G2VDD DDR supply for port 2 R24 — G2VDD — G2VDD DDR supply for port 2 T23 — G2VDD — G2VDD DDR supply for port 2 T32 — G2VDD — G2VDD DDR supply for port 2 U24 — G2VDD — G2VDD DDR supply for port 2 U27 — G2VDD — G2VDD DDR supply for port 2 U30 — G2VDD — G2VDD DDR supply for port 2 V23 — G2VDD — G2VDD DDR supply for port 2 V27 — G2VDD — G2VDD DDR supply for port 2 V30 — G2VDD — G2VDD DDR supply for port 2 W24 — G2VDD — G2VDD DDR supply for port 2 W32 — G2VDD — G2VDD DDR supply for port 2 Y23 — G2VDD — G2VDD DDR supply for port 2 Y26 — G2VDD — G2VDD DDR supply for port 2 AA23 — G2VDD — SVDD SerDes core logic supply K15 — SVDD — SVDD SerDes core logic supply K16 — SVDD — SVDD SerDes core logic supply K17 — SVDD — SVDD SerDes core logic supply K18 — SVDD — SVDD SerDes core logic supply K19 — SVDD — SVDD SerDes core logic supply K20 — SVDD — SVDD SerDes core logic supply K21 — SVDD — SVDD SerDes core logic supply K22 — SVDD — SVDD SerDes core logic supply K23 — SVDD — TH_VDD Thermal Monitor Unit supply J26 — THVDD 21 XVDD SerDes transceiver supply F9 — XVDD — XVDD SerDes transceiver supply F12 — XVDD — XVDD SerDes transceiver supply F15 — XVDD — XVDD SerDes transceiver supply F17 — XVDD — XVDD SerDes transceiver supply F19 — XVDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 32 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes XVDD SerDes transceiver supply F21 — XVDD — XVDD SerDes transceiver supply F24 — XVDD — XVDD SerDes transceiver supply F27 — XVDD — XVDD SerDes transceiver supply F30 — XVDD — QVDD Quiet I/O supply E2 — QVDD 19 QVDD Quiet I/O supply F2 — QVDD 19 QVDD Quiet I/O supply H9 — QVDD 7 VDD Core and Platform supply J10 — VDD — VDD Core and Platform supply J12 — VDD — VDD Core and Platform supply K11 — VDD — VDD Core and Platform supply K13 — VDD — VDD Core and Platform supply L10 — VDD — VDD Core and Platform supply L12 — VDD — VDD Core and Platform supply L14 — VDD — VDD Core and Platform supply L16 — VDD — VDD Core and Platform supply L18 — VDD — VDD Core and Platform supply L20 — VDD — VDD Core and Platform supply L22 — VDD — VDD Core and Platform supply M11 — VDD — VDD Core and Platform supply M13 — VDD — VDD Core and Platform supply M15 — VDD — VDD Core and Platform supply M17 — VDD — VDD Core and Platform supply M19 — VDD — VDD Core and Platform supply M21 — VDD — VDD Core and Platform supply M23 — VDD — VDD Core and Platform supply N10 — VDD — VDD Core and Platform supply N12 — VDD — VDD Core and Platform supply N14 — VDD — VDD Core and Platform supply N16 — VDD — VDD Core and Platform supply N18 — VDD — VDD Core and Platform supply N20 — VDD — VDD Core and Platform supply N22 — VDD — VDD Core and Platform supply P11 — VDD — VDD Core and Platform supply P13 — VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 33 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes VDD Core and Platform supply P15 — VDD — VDD Core and Platform supply P17 — VDD — VDD Core and Platform supply P19 — VDD — VDD Core and Platform supply P21 — VDD — VDD Core and Platform supply P23 — VDD — VDD Core and Platform supply R10 — VDD — VDD Core and Platform supply R12 — VDD — VDD Core and Platform supply R14 — VDD — VDD Core and Platform supply R16 — VDD — VDD Core and Platform supply R18 — VDD — VDD Core and Platform supply R20 — VDD — VDD Core and Platform supply R22 — VDD — VDD Core and Platform supply T11 — VDD — VDD Core and Platform supply T13 — VDD — VDD Core and Platform supply T15 — VDD — VDD Core and Platform supply T17 — VDD — VDD Core and Platform supply T19 — VDD — VDD Core and Platform supply T21 — VDD — VDD Core and Platform supply U12 — VDD — VDD Core and Platform supply U14 — VDD — VDD Core and Platform supply U16 — VDD — VDD Core and Platform supply U18 — VDD — VDD Core and Platform supply U20 — VDD — VDD Core and Platform supply U22 — VDD — VDD Core and Platform supply V11 — VDD — VDD Core and Platform supply V13 — VDD — VDD Core and Platform supply V15 — VDD — VDD Core and Platform supply V17 — VDD — VDD Core and Platform supply V19 — VDD — VDD Core and Platform supply V21 — VDD — VDD Core and Platform supply W12 — VDD — VDD Core and Platform supply W14 — VDD — VDD Core and Platform supply W16 — VDD — VDD Core and Platform supply W18 — VDD — B4860 QorIQ Qonverge Data Sheet, Rev. 3 34 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes VDD Core and Platform supply W20 — VDD — VDD Core and Platform supply W22 — VDD — VDD Core and Platform supply Y11 — VDD — VDD Core and Platform supply Y13 — VDD — VDD Core and Platform supply Y15 — VDD — VDD Core and Platform supply Y17 — VDD — VDD Core and Platform supply Y19 — VDD — VDD Core and Platform supply Y21 — VDD — VDD Core and Platform supply AA12 — VDD — VDD Core and Platform supply AA14 — VDD — VDD Core and Platform supply AA16 — VDD — VDD Core and Platform supply AA18 — VDD — VDD Core and Platform supply AA20 — VDD — VDD Core and Platform supply AA22 — VDD — VDD Core and Platform supply AB11 — VDD — VDD Core and Platform supply AB13 — VDD — VDD Core and Platform supply AB15 — VDD — VDD Core and Platform supply AB17 — VDD — VDD Core and Platform supply AB19 — VDD — VDD Core and Platform supply AB21 — VDD — VDD Core and Platform supply AC12 — VDD — VDD Core and Platform supply AC14 — VDD — VDD Core and Platform supply AC16 — VDD — VDD Core and Platform supply AC18 — VDD — VDD Core and Platform supply AC20 — VDD — VDD Core and Platform supply AC22 — VDD — GND GND A2 — — — GND GND B1 — — — GND GND C2 — — — GND GND D1 — — — GND GND D3 — — — GND GND F3 — — — GND GND G1 — — — GND GND G6 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 35 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes GND GND G7 — — 20 GND GND G8 — — 20 GND GND G32 — — — GND GND H4 — — — GND GND H8 — — 20 GND GND H29 — — — GND GND J6 — — — GND GND J11 — — — GND GND J13 — — — GND GND J25 — — — GND GND J27 — — — GND GND K2 — — — GND GND K10 — — — GND GND K12 — — — GND GND K14 — — — GND GND K24 — — 20 GND GND K31 — — — GND GND L4 — — — GND GND L11 — — — GND GND L13 — — — GND GND L15 — — — GND GND L17 — — — GND GND L19 — — — GND GND L21 — — — GND GND L23 — — — GND GND L29 — — — GND GND M6 — — — GND GND M9 — — — GND GND M10 — — — GND GND M12 — — — GND GND M14 — — — GND GND M16 — — — GND GND M18 — — — GND GND M20 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 36 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes GND GND M22 — — — GND GND M24 — — — GND GND M27 — — — GND GND N2 — — — GND GND N11 — — — GND GND N13 — — — GND GND N15 — — — GND GND N17 — — — GND GND N19 — — — GND GND N21 — — — GND GND N23 — — — GND GND N31 — — — GND GND P4 — — — GND GND P10 — — — GND GND P12 — — — GND GND P14 — — — GND GND P16 — — — GND GND P18 — — — GND GND P20 — — — GND GND P22 — — — GND GND P29 — — — GND GND R2 — — — GND GND R6 — — — GND GND R11 — — — GND GND R13 — — — GND GND R15 — — — GND GND R17 — — — GND GND R19 — — — GND GND R21 — — — GND GND R23 — — — GND GND R27 — — — GND GND R31 — — — GND GND T12 — — — GND GND T14 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 37 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes GND GND T16 — — — GND GND T18 — — — GND GND T20 — — — GND GND T22 — — — GND GND U10 — — — GND GND U11 — — — GND GND U13 — — — GND GND U15 — — — GND GND U17 — — — GND GND U19 — — — GND GND U21 — — — GND GND U23 — — — GND GND V12 — — — GND GND V14 — — — GND GND V16 — — — GND GND V18 — — — GND GND V20 — — — GND GND V22 — — — GND GND W10 — — — GND GND W11 — — — GND GND W13 — — — GND GND W15 — — — GND GND W17 — — — GND GND W19 — — — GND GND W21 — — — GND GND W23 — — — GND GND Y2 — — — GND GND Y4 — — — GND GND Y12 — — — GND GND Y14 — — — GND GND Y16 — — — GND GND Y18 — — — GND GND Y20 — — — GND GND Y22 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 38 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes GND GND Y29 — — — GND GND Y31 — — — GND GND AA11 — — — GND GND AA13 — — — GND GND AA15 — — — GND GND AA17 — — — GND GND AA19 — — — GND GND AA21 — — — GND GND AB2 — — — GND GND AB5 — — — GND GND AB8 — — — GND GND AB9 — — — GND GND AB10 — — — GND GND AB12 — — — GND GND AB14 — — — GND GND AB16 — — — GND GND AB18 — — — GND GND AB20 — — — GND GND AB22 — — — GND GND AB23 — — — GND GND AB24 — — — GND GND AB25 — — — GND GND AB28 — — — GND GND AB31 — — — GND GND AC7 — — — GND GND AC10 — — — GND GND AC11 — — — GND GND AC13 — — — GND GND AC15 — — — GND GND AC17 — — — GND GND AC19 — — — GND GND AC21 — — — GND GND AC23 — — — GND GND AC26 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 39 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes GND GND AD4 — — — GND GND AD8 — — — GND GND AD9 — — — GND GND AD14 — — — GND GND AD16 — — — GND GND AD18 — — — GND GND AD20 — — — GND GND AD22 — — — GND GND AD24 — — — GND GND AD25 — — — GND GND AD29 — — — GND GND AE2 — — — GND GND AE13 — — — GND GND AE15 — — — GND GND AE17 — — — GND GND AE19 — — — GND GND AE21 — — — GND GND AE22 — — — GND GND AE31 — — — GND GND AF5 — — — GND GND AF28 — — — GND GND AG8 — — — GND GND AG11 — — — GND GND AG14 — — — GND GND AG17 — — — GND GND AG20 — — — GND GND AG23 — — — GND GND AG26 — — — GND GND AH2 — — — GND GND AH31 — — — GND GND AJ5 — — — GND GND AJ7 — — — GND GND AJ10 — — — GND GND AJ13 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 40 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes GND GND AJ16 — — — GND GND AJ19 — — — GND GND AJ22 — — — GND GND AJ25 — — — GND GND AJ28 — — — GND GND AL1 — — — GND GND AL3 — — — GND GND AL6 — — — GND GND AL9 — — — GND GND AL12 — — — GND GND AL15 — — — GND GND AL18 — — — GND GND AL21 — — — GND GND AL24 — — — GND GND AL27 — — — GND GND AL30 — — — GND GND AL32 — — — GND GND AM2 — — — GND GND AM31 — — — XGND SerDes transceiver GND D6 — — — XGND SerDes transceiver GND D9 — — — XGND SerDes transceiver GND D12 — — — XGND SerDes transceiver GND D15 — — — XGND SerDes transceiver GND D18 — — — XGND SerDes transceiver GND D21 — — — XGND SerDes transceiver GND D24 — — — XGND SerDes transceiver GND D27 — — — XGND SerDes transceiver GND D30 — — — XGND SerDes transceiver GND E6 — — — XGND SerDes transceiver GND E9 — — — XGND SerDes transceiver GND E12 — — — XGND SerDes transceiver GND E15 — — — XGND SerDes transceiver GND E18 — — — XGND SerDes transceiver GND E21 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 41 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes XGND SerDes transceiver GND E24 — — — XGND SerDes transceiver GND E27 — — — XGND SerDes transceiver GND E30 — — — XGND SerDes transceiver GND F18 — — — SGND SerDes core logic GND A4 — — — SGND SerDes core logic GND A7 — — — SGND SerDes core logic GND A10 — — — SGND SerDes core logic GND A13 — — — SGND SerDes core logic GND A15 — — — SGND SerDes core logic GND A18 — — — SGND SerDes core logic GND A21 — — — SGND SerDes core logic GND A23 — — — SGND SerDes core logic GND A25 — — — SGND SerDes core logic GND A28 — — — SGND SerDes core logic GND A31 — — — SGND SerDes core logic GND B4 — — — SGND SerDes core logic GND B7 — — — SGND SerDes core logic GND B10 — — — SGND SerDes core logic GND B13 — — — SGND SerDes core logic GND B15 — — — SGND SerDes core logic GND B18 — — — SGND SerDes core logic GND B21 — — — SGND SerDes core logic GND B23 — — — SGND SerDes core logic GND B25 — — — SGND SerDes core logic GND B28 — — — SGND SerDes core logic GND B31 — — — SGND SerDes core logic GND C4 — — — SGND SerDes core logic GND C5 — — — SGND SerDes core logic GND C6 — — — SGND SerDes core logic GND C7 — — — SGND SerDes core logic GND C8 — — — SGND SerDes core logic GND C9 — — — SGND SerDes core logic GND C10 — — — SGND SerDes core logic GND C11 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 42 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes SGND SerDes core logic GND C12 — — — SGND SerDes core logic GND C13 — — — SGND SerDes core logic GND C14 — — — SGND SerDes core logic GND C15 — — — SGND SerDes core logic GND C16 — — — SGND SerDes core logic GND C17 — — — SGND SerDes core logic GND C18 — — — SGND SerDes core logic GND C19 — — — SGND SerDes core logic GND C20 — — — SGND SerDes core logic GND C21 — — — SGND SerDes core logic GND C22 — — — SGND SerDes core logic GND C23 — — — SGND SerDes core logic GND C24 — — — SGND SerDes core logic GND C25 — — — SGND SerDes core logic GND C26 — — — SGND SerDes core logic GND C27 — — — SGND SerDes core logic GND C28 — — — SGND SerDes core logic GND C29 — — — SGND SerDes core logic GND C30 — — — SGND SerDes core logic GND D4 — — — SGND SerDes core logic GND D31 — — — SGND SerDes core logic GND D32 — — — SGND SerDes core logic GND E4 — — — SGND SerDes core logic GND F5 — — — SGND SerDes core logic GND F6 — — — SGND SerDes core logic GND F7 — — — SGND SerDes core logic GND F8 — — — SGND SerDes core logic GND F10 — — — SGND SerDes core logic GND F11 — — — SGND SerDes core logic GND F13 — — — SGND SerDes core logic GND F14 — — — SGND SerDes core logic GND F16 — — — SGND SerDes core logic GND F20 — — — SGND SerDes core logic GND F22 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 43 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes SGND SerDes core logic GND F23 — — — SGND SerDes core logic GND F25 — — — SGND SerDes core logic GND F26 — — — SGND SerDes core logic GND F28 — — — SGND SerDes core logic GND F29 — — — SGND SerDes core logic GND F31 — — — SGND SerDes core logic GND F32 — — — SGND SerDes core logic GND G9 — — — SGND SerDes core logic GND G11 — — — SGND SerDes core logic GND G12 — — — SGND SerDes core logic GND G15 — — — SGND SerDes core logic GND G17 — — — SGND SerDes core logic GND G19 — — — SGND SerDes core logic GND G21 — — — SGND SerDes core logic GND G23 — — — SGND SerDes core logic GND G27 — — — SGND SerDes core logic GND H10 — — — SGND SerDes core logic GND H12 — — — SGND SerDes core logic GND H13 — — — SGND SerDes core logic GND H19 — — — SGND SerDes core logic GND H25 — — — SGND SerDes core logic GND H26 — — — SGND SerDes core logic GND J14 — — — SGND SerDes core logic GND J15 — — — SGND SerDes core logic GND J16 — — — SGND SerDes core logic GND J17 — — — SGND SerDes core logic GND J18 — — — SGND SerDes core logic GND J19 — — — SGND SerDes core logic GND J20 — — — SGND SerDes core logic GND J21 — — — SGND SerDes core logic GND J22 — — — SGND SerDes core logic GND J23 — — — SGND SerDes core logic GND J24 — — — B4860 QorIQ Qonverge Data Sheet, Rev. 3 44 NXP Semiconductors Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes No connection pins NC_D2 No Connection D2 — — 18 NC_E3 No Connection E3 — — 18 NC_F4 No Connection F4 — — 18 NC_G5 No Connection G5 — — 18 NC_G13 No Connection G13 — — 18 NC_G16 No Connection G16 — — 18 NC_G22 No Connection G22 — — 18 NC_G25 No Connection G25 — — 18 NC_G28 No Connection G28 — — 18 NC_H7 No Connection H7 — — 18 NC_H15 No Connection H15 — — 18 NC_H16 No Connection H16 — — 18 NC_H22 No Connection H22 — — 18 NC_H23 No Connection H23 — — 18 NC_AD10 No Connection AD10 — — 18 NC_AD23 No Connection AD23 — — 18 NC_DET Orientation Detect B32 — — 18 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 45 Pin assignments Table 1. Pinout list by bus (continued) Signal Signal Description Package Pin Type Pin Power Supply Notes 1. MDIC[0] is grounded through a 237 Ω for B4860 Rev. 1 and 187 Ω for B4860 Rev. 2 precision 1% resistor and MDIC[1] is connected to GnVDD through a 237 Ω for B4860 Rev. 1 and 187 Ω for B4860 Rev. 2 precision 1% resistor. For either full or half driver strength calibration of DDR IOs, use the same MDIC resistor value of 237 Ω for B4860 Rev. 1 and 187 Ω for B4860 Rev. 2. The memory controller register setting can be used to determine automatic calibration is done to full or half-drive strength. These pins are used for automatic calibration of the DDR3/DDR3L IOs. 2. Functionally, this pin is an output or an input, but structurally it is an I/O because it either samples configuration input during reset, is a muxed pin, or it has other manufacturing test functions. Thus, this pin is described as an I/O for boundary scan. 3. This pin is an open drain signal. Recommend that a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD. 4. When used as an I2C interface, this pin functions as an open drain I/O. Recommend that a pull-up resistor (1 kΩ) be placed on this pin to DVDD. 5. When used as an IRQ_OUT_B pin, this pin functions as an open drain I/O. Recommend that a weak pull-up resistor (2–10 kΩ) be placed on this pin to OVDD. 6. See Section 3.5, “Connection recommendations for unused pins,” for additional details on this signal. 7. QVDD is an internal IO quiet power domain. Externally, it should be connected to the OVDD supply. 8. Pin must NOT be pulled down during power-on reset. This pin may be pulled up, driven high, or if there are any externally connected devices, left in tristate. If this pin is connected to a device that pulls down during reset, external pull-up is required to drive this pin to a safe state during reset. 9. Pin has a weak (~20 kΩ) internal pull-up P-FET, which is always enabled. 10.This output is actively driven during reset rather than being tristated during reset. 11.This pin requires a 698 Ω (1% accuracy) pull-up to XVDD. 12.This pin requires a 200 Ω (1% accuracy) pull-up to SVDD. 13.These pins should be pulled up to 1.2 V through a 180 Ω (1% accuracy) resistor for EMI2_MDC and 330 Ω (1% accuracy) resistor for EMI2_MDIO. 14.Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels. OVDD must be powered to use this interface. 15.CFG_RSP_DIS configuration pin allows the B4860 to enter debug mode immediately after reset. The board should be configured (by some FPGA/dip-switch) to drive the CFG_RSP_DIS pin during PORESET sequence to logic 0 or logic 1, with a default level of logic 1, and with the timing as defined for all other CFG pins. After POR completion, the pin is used as IFC_AVD function. 16.See Section 2.2, “Power sequencing,” and Section 5, “Security fuse processor,” for additional details on this signal. 17.These pins are connected to the same global power and ground (VDD and GND) nets internally and may be connected as a differential pair to be used by the voltage regulators with remote sense function. 18.Do not connect. These pins should be left floating. 19.The QVDD supply to these pins is not an actual supply pin, but a functional pin requires the QVDD supply connectivity. Pin must be connected with a pull up resistor of 10 kΩ. 20.The GND supply to these pins is not an actual supply pin, but a functional pin requires the GND supply connectivity. Pin must be connected with a pull down resistor of 10 kΩ. 21.The Thermal Monitoring Unit (TMU) is defeatured on this device. TH_VDD should be connected to an OVDD supply. 22.This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that is enabled only when the processor is in its reset state. This pull-up is designed such that it can be overpowered by an external 4.7 kΩ resistor. However, when the signal is intended to be high after reset, and when there is a device on the net that might pull down the value of the net at reset, a pull-up or active driver is needed. 23.CFG_DRAM_TYPE configuration pin selects the DRAM type: “0”—DDR3 (IO is 1.5 V), “1”—DDR3L (IO is 1.35 V) 24.CFG_XVDD_SEL configuration pin selects the XVDD voltage: “0”—XVDD is 1.5 V, “1”—XVDD is 1.35 V. 25.CFG_IFC_TE configuration pin selects the IFC External Transceiver Enable Pin Polarity: “0”—Default value of IFC’s CSPR0[TE] is logic 1, “1”—Default value of IFC’s CSPR0[TE] is logic 0. 26.Recommend that a weak pull-up resistor (4.7-kΩ) be placed on this pin to the respective power supply. 27.Recommend that a weak pull-up resistor (2-10 kΩ) be placed on this pin to the respective power supply. 28.Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective power supply. 29.Must be pulled down externally (for any active CPRI lane that is not connected to an SFP). 30.When configured as DUART (using RCW[UART_EXT] bits), pins are internally pulled down. When the pins are configured as CP_LOSi, they should be pulled down externally for any active CPRI lane that is not connected to an SFP. 31.When the thermal diode is not used, its pins (anode, cathode) should be connected to GND. 32.If used as an SDHC signal, pull-up 10 to 100 kΩ. to the respective IO supply. B4860 QorIQ Qonverge Data Sheet, Rev. 3 46 NXP Semiconductors Pin assignments WARNING See Section 3.5, “Connection recommendations for unused pins,” for additional details on properly connecting these pins for specific applications. 1.3 Pinout list by package pin number This table provides the pinout list for the chip sorted by package pin number. Table 2. Pinout by package pin number Package pin number Package pin name Package pin number A1 — B1 GND Package Pin Name A2 GND B2 AVDD_CGB1 A3 AVDD_CGA1 B3 AVDD_PLAT A4 SGND B4 SGND A5 SD2_RX7 B5 SD2_RX7_B A6 SD2_RX6 B6 SD2_RX6_B A7 SGND B7 SGND A8 SD2_RX5 B8 SD2_RX5_B A9 SD2_RX4 B9 SD2_RX4_B A10 SGND B10 SGND A11 SD2_RX3 B11 SD2_RX3_B A12 SD2_RX2 B12 SD2_RX2_B A13 SGND B13 SGND A14 SD2_REF1_CLK_B B14 SD2_REF1_CLK A15 SGND B15 SGND A16 SD2_RX1 B16 SD2_RX1_B A17 SD2_RX0 B17 SD2_RX0_B A18 SGND B18 SGND A19 SD1_RX0 B19 SD1_RX0_B A20 SD1_RX1 B20 SD1_RX1_B A21 SGND B21 SGND A22 SD1_REF1_CLK_B B22 SD1_REF1_CLK A23 SGND B23 SGND A24 SD1_RX2 B24 SD1_RX2_B A25 SGND B25 SGND A26 SD1_RX3 B26 SD1_RX3_B A27 SD1_RX4 B27 SD1_RX4_B B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 47 Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name A28 SGND B28 SGND A29 SD1_RX5 B29 SD1_RX5_B A30 SD1_RX6 B30 SD1_RX6_B A31 SGND B31 SGND B32 NC_DET A32 — C1 AVDD_CGA2 D1 GND C2 GND D2 NC_D2 C3 AVDD_CGB2 D3 GND C4 SGND D4 SGND C5 SGND D5 SD2_REF2_CLK_B C6 SGND D6 XGND C7 SGND D7 SD2_TX7 C8 SGND D8 SD2_TX6 C9 SGND D9 XGND C10 SGND D10 SD2_TX5 C11 SGND D11 SD2_TX4 C12 SGND D12 XGND C13 SGND D13 SD2_TX3 C14 SGND D14 SD2_TX2 C15 SGND D15 XGND C16 SGND D16 SD2_TX1 C17 SGND D17 SD2_TX0 C18 SGND D18 XGND C19 SGND D19 SD1_TX0 C20 SGND D20 SD1_TX1 C21 SGND D21 XGND C22 SGND D22 SD1_TX2 C23 SGND D23 SD1_TX3 C24 SGND D24 XGND C25 SGND D25 SD1_TX4 C26 SGND D26 SD1_TX5 C27 SGND D27 XGND C28 SGND D28 SD1_TX6 C29 SGND D29 SD1_TX7 B4860 QorIQ Qonverge Data Sheet, Rev. 3 48 NXP Semiconductors Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name C30 SGND D30 XGND C31 SD1_RX7_B D31 SGND C32 SD1_RX7 D32 SGND E1 PORESET_B F1 SYSCLK E2 QVDD F2 QVDD E3 NC_E3 F3 GND E4 SGND F4 NC_F4 E5 SD2_REF2_CLK F5 SGND E6 XGND F6 SGND E7 SD2_TX7_B F7 SGND E8 SD2_TX6_B F8 SGND E9 XGND F9 XVDD E10 SD2_TX5_B F10 SGND E11 SD2_TX4_B F11 SGND E12 XGND F12 XVDD E13 SD2_TX3_B F13 SGND E14 SD2_TX2_B F14 SGND E15 XGND F15 XVDD E16 SD2_TX1_B F16 SGND E17 SD2_TX0_B F17 XVDD E18 XGND F18 XGND E19 SD1_TX0_B F19 XVDD E20 SD1_TX1_B F20 SGND E21 XGND F21 XVDD E22 SD1_TX2_B F22 SGND E23 SD1_TX3_B F23 SGND E24 XGND F24 XVDD E25 SD1_TX4_B F25 SGND E26 SD1_TX5_B F26 SGND E27 XGND F27 XVDD E28 SD1_TX6_B F28 SGND E29 SD1_TX7_B F29 SGND E30 XGND F30 XVDD E31 SD1_REF2_CLK F31 SGND B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 49 Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name E32 SD1_REF2_CLK_B F32 SGND G1 GND H1 D1_MDQ51 G2 D1_MDQ59 H2 D1_MDQ52 G3 D1_MDQ56 H3 D1_MDQ55 G4 D1_MDQ58 H4 GND G5 NC_G5 H5 D1_MDQ60 G6 GND H6 D1_MDQ63 G7 GND H7 NC_H7 G8 GND H8 GND G9 SGND H9 QVDD G10 SD2_IMP_CAL_TX H10 SGND G11 SGND H11 POVDD G12 SGND H12 SGND G13 NC_G13 H13 SGND G14 AGND_SRDS2_PLL2 H14 AVDD_SRDS2_PLL2 G15 SGND H15 NC_H15 G16 NC_G16 H16 NC_H16 G17 SGND H17 AVDD_SRDS2_PLL1 G18 SD2_IMP_CAL_RX H18 AGND_SRDS2_PLL1 G19 SGND H19 SGND G20 SD1_IMP_CAL_RX H20 AGND_SRDS1_PLL1 G21 SGND H21 AVDD_SRDS1_PLL1 G22 NC_G22 H22 NC_H22 G23 SGND H23 NC_H23 G24 AGND_SRDS1_PLL2 H24 AVDD_SRDS1_PLL2 G25 NC_G25 H25 SGND G26 SD1_IMP_CAL_TX H26 SGND G27 SGND H27 D2_MDQ63 G28 NC_G28 H28 D2_MDQ60 G29 D2_MDQ58 H29 GND G30 D2_MDQ56 H30 D2_MDQ55 G31 D2_MDQ59 H31 D2_MDQ52 G32 GND H32 D2_MDQ51 K1 D1_MDQ50 J1 D1_MDQS6 B4860 QorIQ Qonverge Data Sheet, Rev. 3 50 NXP Semiconductors Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name J2 D1_MDQS6_B K2 GND J3 D1_MDM6 K3 D1_MDQ53 J4 D1_MDQS7 K4 D1_MDQ54 J5 D1_MDQS7_B K5 D1_MDM7 J6 GND K6 D1_MDQ57 J7 TD_ANODE K7 D1_MDQ61 J8 TD_CATHODE K8 D1_MODT1 J9 SENSEGND1 K9 SENSEVDD1 J10 VDD K10 GND J11 GND K11 VDD J12 VDD K12 GND J13 GND K13 VDD J14 SGND K14 GND J15 SGND K15 SVDD J16 SGND K16 SVDD J17 SGND K17 SVDD J18 SGND K18 SVDD J19 SGND K19 SVDD J20 SGND K20 SVDD J21 SGND K21 SVDD J22 SGND K22 SVDD J23 SGND K23 SVDD J24 SGND K24 GND J25 GND K25 D2_MODT1 J26 TH_VDD K26 D2_MDQ61 J27 GND K27 D2_MDQ57 J28 D2_MDQS7_B K28 D2_MDM7 J29 D2_MDQS7 K29 D2_MDQ54 J30 D2_MDM6 K30 D2_MDQ53 J31 D2_MDQS6_B K31 GND J32 D2_MDQS6 K32 D2_MDQ50 L1 D1_MDQ48 M1 D1_MDQ35 L2 D1_MDQ49 M2 D1_MDQ34 L3 D1_MDQ43 M3 D1_MDQ37 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 51 Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name L4 GND M4 D1_MDQ41 L5 D1_MDQ47 M5 D1_MDQ42 L6 D1_MDQ45 M6 GND L7 D1_MDQ62 M7 D1_MODT0 L8 G1VDD M8 D1_MODT3 L9 D1_MCS3_B M9 GND L10 VDD M10 GND L11 GND M11 VDD L12 VDD M12 GND L13 GND M13 VDD L14 VDD M14 GND L15 GND M15 VDD L16 VDD M16 GND L17 GND M17 VDD L18 VDD M18 GND L19 GND M19 VDD L20 VDD M20 GND L21 GND M21 VDD L22 VDD M22 GND L23 GND M23 VDD L24 D2_MCS3_B M24 GND L25 G2VDD M25 D2_MODT3 L26 D2_MDQ62 M26 D2_MODT0 L27 D2_MDQ45 M27 GND L28 D2_MDQ47 M28 D2_MDQ42 L29 GND M29 D2_MDQ41 L30 D2_MDQ43 M30 D2_MDQ37 L31 D2_MDQ49 M31 D2_MDQ34 L32 D2_MDQ48 M32 D2_MDQ35 N1 D1_MDQ33 P1 D1_MDQS4 N2 GND P2 D1_MDQS4_B N3 D1_MDM4 P3 D1_MDQ39 N4 D1_MDQS5 P4 GND N5 D1_MDQS5_B P5 D1_MDQ40 B4860 QorIQ Qonverge Data Sheet, Rev. 3 52 NXP Semiconductors Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name N6 D1_MDM5 P6 D1_MDQ46 N7 D1_MWE_B P7 G1VDD N8 D1_MODT2 P8 D1_MRAS_B N9 D1_MA13 P9 D1_MCS1_B N10 VDD P10 GND N11 GND P11 VDD N12 VDD P12 GND N13 GND P13 VDD N14 VDD P14 GND N15 GND P15 VDD N16 VDD P16 GND N17 GND P17 VDD N18 VDD P18 GND N19 GND P19 VDD N20 VDD P20 GND N21 GND P21 VDD N22 VDD P22 GND N23 GND P23 VDD N24 D2_MA13 P24 D2_MCS1_B N25 D2_MODT2 P25 D2_MRAS_B N26 D2_MWE_B P26 G2VDD N27 D2_MDM5 P27 D2_MDQ46 N28 D2_MDQS5_B P28 D2_MDQ40 N29 D2_MDQS5 P29 GND N30 D2_MDM4 P30 D2_MDQ39 N31 GND P31 D2_MDQS4_B N32 D2_MDQ33 P32 D2_MDQS4 R1 D1_MDQ32 T1 G1VDD R2 GND T2 D1_MA05 R3 D1_MDQ36 T3 D1_MAPAR_ERR_B R4 D1_MDQ38 T4 D1_MA02 R5 D1_MDQ44 T5 D1_MBA1 R6 GND T6 D1_MA01 R7 D1_MCS2_B T7 D1_MAPAR_OUT B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 53 Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name R8 D1_MCAS_B T8 D1_MBA0 R9 G1VDD T9 D1_MCS0_B R10 VDD T10 G1VDD R11 GND T11 VDD R12 VDD T12 GND R13 GND T13 VDD R14 VDD T14 GND R15 GND T15 VDD R16 VDD T16 GND R17 GND T17 VDD R18 VDD T18 GND R19 GND T19 VDD R20 VDD T20 GND R21 GND T21 VDD R22 VDD T22 GND R23 GND T23 G2VDD R24 G2VDD T24 D2_MCS0_B R25 D2_MCAS_B T25 D2_MBA0 R26 D2_MCS2_B T26 D2_MAPAR_OUT R27 GND T27 D2_MA01 R28 D2_MDQ44 T28 D2_MBA1 R29 D2_MDQ38 T29 D2_MA02 R30 D2_MDQ36 T30 D2_MAPAR_ERR_B R31 GND T31 D2_MA05 R32 D2_MDQ32 T32 G2VDD U1 D1_MCK2 V1 D1_MCK0 U2 D1_MCK2_B V2 D1_MCK0_B U3 G1VDD V3 G1VDD U4 D1_MCK3 V4 D1_MCK1 U5 D1_MCK3_B V5 D1_MCK1_B U6 G1VDD V6 G1VDD U7 D1_MA00 V7 D1_MDIC1 U8 D1_MA10 V8 D1_MA04 U9 G1VDD V9 D1_MA03 B4860 QorIQ Qonverge Data Sheet, Rev. 3 54 NXP Semiconductors Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name U10 GND V10 G1VDD U11 GND V11 VDD U12 VDD V12 GND U13 GND V13 VDD U14 VDD V14 GND U15 GND V15 VDD U16 VDD V16 GND U17 GND V17 VDD U18 VDD V18 GND U19 GND V19 VDD U20 VDD V20 GND U21 GND V21 VDD U22 VDD V22 GND U23 GND V23 G2VDD U24 G2VDD V24 D2_MA03 U25 D2_MA10 V25 D2_MA04 U26 D2_MA00 V26 D2_MDIC1 U27 G2VDD V27 G2VDD U28 D2_MCK3_B V28 D2_MCK1_B U29 D2_MCK3 V29 D2_MCK1 U30 G2VDD V30 G2VDD U31 D2_MCK2_B V31 D2_MCK0_B U32 D2_MCK2 V32 D2_MCK0 W1 G1VDD Y1 D1_MECC3 W2 D1_MDIC0 Y2 GND W3 D1_MA08 Y3 D1_MECC7 W4 D1_MA06 Y4 GND W5 D1_MA07 Y5 D1_MECC0 W6 D1_MA09 Y6 D1_MCKE3 W7 D1_MA12 Y7 G1VDD W8 D1_MA11 Y8 D1_MCKE2 W9 G1VDD Y9 D1_MA15 W10 GND Y10 G1VDD W11 GND Y11 VDD B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 55 Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name W12 VDD Y12 GND W13 GND Y13 VDD W14 VDD Y14 GND W15 GND Y15 VDD W16 VDD Y16 GND W17 GND Y17 VDD W18 VDD Y18 GND W19 GND Y19 VDD W20 VDD Y20 GND W21 GND Y21 VDD W22 VDD Y22 GND W23 GND Y23 G2VDD W24 G2VDD Y24 D2_MA15 W25 D2_MA11 Y25 D2_MCKE2 W26 D2_MA12 Y26 G2VDD W27 D2_MA09 Y27 D2_MCKE3 W28 D2_MA07 Y28 D2_MECC0 W29 D2_MA06 Y29 GND W30 D2_MA08 Y30 D2_MECC7 W31 D2_MDIC0 Y31 GND W32 G2VDD Y32 D2_MECC3 AA1 D1_MDQS8_B AB1 D1_MDM8 AA2 D1_MDQS8 AB2 GND AA3 D1_MECC6 AB3 D1_MECC2 AA4 D1_MDQ30 AB4 D1_MDQ29 AA5 D1_MDM3 AB5 GND AA6 D1_MBA2 AB6 D1_MDQ27 AA7 D1_MCKE0 AB7 D1_MDQ26 AA8 D1_MCKE1 AB8 GND AA9 D1_MA14 AB9 GND AA10 G1VDD AB10 GND AA11 GND AB11 VDD AA12 VDD AB12 GND AA13 GND AB13 VDD B4860 QorIQ Qonverge Data Sheet, Rev. 3 56 NXP Semiconductors Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name AA14 VDD AB14 GND AA15 GND AB15 VDD AA16 VDD AB16 GND AA17 GND AB17 VDD AA18 VDD AB18 GND AA19 GND AB19 VDD AA20 VDD AB20 GND AA21 GND AB21 VDD AA22 VDD AB22 GND AA23 G2VDD AB23 GND AA24 D2_MA14 AB24 GND AA25 D2_MCKE1 AB25 GND AA26 D2_MCKE0 AB26 D2_MDQ26 AA27 D2_MBA2 AB27 D2_MDQ27 AA28 D2_MDM3 AB28 GND AA29 D2_MDQ30 AB29 D2_MDQ29 AA30 D2_MECC6 AB30 D2_MECC2 AA31 D2_MDQS8 AB31 GND AA32 D2_MDQS8_B AB32 D2_MDM8 AC1 D1_MECC5 AD1 D1_MDM2 AC2 D1_MECC4 AD2 D1_MDQ19 AC3 D1_MECC1 AD3 D1_MDQ22 AC4 D1_MDQ31 AD4 GND AC5 D1_MDQS3_B AD5 D1_MDQ28 AC6 D1_MDQS3 AD6 D1_MDQ24 AC7 GND AD7 D1_MDQ25 AC8 AVDD_DDR1 AD8 GND AC9 M1VREF AD9 GND AC10 GND AD10 NC_AD10 AC11 GND AD11 SENSEGND2 AC12 VDD AD12 D1_DDRCLK AC13 GND AD13 OVDD AC14 VDD AD14 GND AC15 GND AD15 OVDD B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 57 Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name AC16 VDD AD16 GND AC17 GND AD17 OVDD AC18 VDD AD18 GND AC19 GND AD19 DVDD AC20 VDD AD20 GND AC21 GND AD21 D2_DDRCLK AC22 VDD AD22 GND AC23 GND AD23 NC_AD23 AC24 M2VREF AD24 GND AC25 AVDD_DDR2 AD25 GND AC26 GND AD26 D2_MDQ25 AC27 D2_MDQS3 AD27 D2_MDQ24 AC28 D2_MDQS3_B AD28 D2_MDQ28 AC29 D2_MDQ31 AD29 GND AC30 D2_MECC1 AD30 D2_MDQ22 AC31 D2_MECC4 AD31 D2_MDQ19 AC32 D2_MECC5 AD32 D2_MDM2 AE1 D1_MDQ21 AF1 D1_MDQS2_B AE2 GND AF2 D1_MDQS2 AE3 D1_MDQ23 AF3 D1_MDQ16 AE4 D1_MDQS0_B AF4 D1_MDQ03 AE5 D1_MDQS0 AF5 GND AE6 D1_MDQ04 AF6 D1_MDQ06 AE7 D1_MDQ01 AF7 D1_MDQ00 AE8 TSEC_1588_CLK_OUT AF8 USB_D0 AE9 TSEC_1588_TRIG_IN1 AF9 TSEC_1588_PULSE_OUT1 AE10 EVT0_B AF10 TSEC_1588_TRIG_IN2 AE11 EVT1_B AF11 CP_SYNC1 AE12 SENSEVDD2 AF12 EVT4_B AE13 GND AF13 IFC_AD02/CFG_GPINPUT2 AE14 OVDD AF14 IFC_AD08/CFG_RCW_SRC0 AE15 GND AF15 IFC_AD09/CFG_RCW_SRC1 AE16 OVDD AF16 IFC_AD10/CFG_RCW_SRC2 AE17 GND AF17 IFC_AD12/CFG_RCW_SRC4 B4860 QorIQ Qonverge Data Sheet, Rev. 3 58 NXP Semiconductors Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name AE18 OVDD AF18 IFC_AD13/CFG_RCW_SRC5 AE19 GND AF19 IFC_AD03/CFG_GPINPUT3 AE20 DVDD AF20 TMP_DETECT_B AE21 GND AF21 SDHC_DAT3/GPIO2[8] AE22 GND AF22 IRQ01 AE23 IIC2_SCL AF23 IRQ00 AE24 UART1_CTS_B/GPIO1[21]/UART3_SIN/ CP_LOS7 AF24 UART1_RTS_B/GPIO1[19]/UART3_SOUT/ CP_LOS6 AE25 IIC4_SDA/GPIO3[6]/EVT6_B/ USB_PWRFAULT AF25 UART2_SOUT/GPIO1[16] AE26 D2_MDQ01 AF26 D2_MDQ00 AE27 D2_MDQ04 AF27 D2_MDQ06 AE28 D2_MDQS0 AF28 GND AE29 D2_MDQS0_B AF29 D2_MDQ03 AE30 D2_MDQ23 AF30 D2_MDQ16 AE31 GND AF31 D2_MDQS2 AE32 D2_MDQ21 AF32 D2_MDQS2_B AG1 D1_MDQ20 AH1 D1_MDM1 AG2 D1_MDQ18 AH2 GND AG3 D1_MDQ17 AH3 D1_MDQ13 AG4 D1_MDM0 AH4 D1_MDQ08 AG5 D1_MDQ05 AH5 D1_MDQ07 AG6 D1_MDQ02 AH6 USB_STP AG7 USB_D1 AH7 USB_D2 AG8 GND AH8 TSEC_1588_ALARM_OUT2 AG9 TSEC_1588_ALARM_OUT1 AH9 CP_SYNC7 AG10 CP_SYNC2 AH10 CP_SYNC3 AG11 GND AH11 EVT2_B AG12 IFC_AD00/CFG_GPINPUT0 AH12 IFC_A24/IFC_WP3_B AG13 IFC_AD01/CFG_GPINPUT1 AH13 IFC_PAR0/GPIO2[13] AG14 GND AH14 IFC_A17 AG15 IFC_A16 AH15 IFC_AD04/CFG_GPINPUT4 AG16 IFC_A18 AH16 IFC_AD11/CFG_RCW_SRC3 AG17 GND AH17 IFC_A20 AG18 IFC_AD15/CFG_RCW_SRC7 AH18 IFC_A19 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 59 Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name AG19 IFC_A21/CFG_DRAM_TYPE AH19 IFC_AD14/CFG_RCW_SRC6 AG20 GND AH20 SPI_CS2_B/GPIO2[2]/SDHC_DAT6 AG21 SPI_CLK AH21 SDHC_DAT1/GPIO2[6] AG22 SDHC_DAT0/GPIO2[5] AH22 IRQ02 AG23 GND AH23 IRQ03/GPIO1[23] AG24 IIC2_SDA AH24 IRQ04/GPIO1[24] AG25 UART2_RTS_B/GPIO1[20]/UART4_SOUT AH25 IIC1_SDA AG26 GND AH26 UART2_SIN/GPIO1[18] AG27 D2_MDQ02 AH27 IIC1_SCL AG28 D2_MDQ05 AH28 D2_MDQ07 AG29 D2_MDM0 AH29 D2_MDQ08 AG30 D2_MDQ17 AH30 D2_MDQ13 AG31 D2_MDQ18 AH31 GND AG32 D2_MDQ20 AH32 D2_MDM1 AJ1 D1_MDQ11 AK1 D1_MDQS1_B AJ2 D1_MDQ14 AK2 D1_MDQS1 AJ3 D1_MDQ12 AK3 D1_MDQ10 AJ4 D1_MDQ09 AK4 USB_D7 AJ5 GND AK5 USB_D4 AJ6 USB_D3 AK6 USB_D5 AJ7 GND AK7 TSEC_1588_PULSE_OUT2 AJ8 EMI2_MDIO AK8 CP_SYNC5 AJ9 CP_SYNC0 AK9 CP_SYNC6 AJ10 GND AK10 ASLEEP/GPIO1[13]/CFG_XVDD_SEL AJ11 EVT3_B AK11 CKSTP_OUT_B AJ12 IFC_PAR1/GPIO2[14] AK12 IFC_WE_B/IFC_WBE0 AJ13 GND AK13 IFC_CS1_B/GPIO2[10] AJ14 IFC_A25/GPIO2[25]/IFC_RB2_B/ IFC_FCTA2 AK14 IFC_CS2_B/GPIO2[11] AJ15 IFC_A26/GPIO2[26]/IFC_RB3_B/ IFC_FCTA3 AK15 IFC_CS0_B AJ16 GND AK16 IFC_OE_B/IFC_RE_B AJ17 IFC_A27/GPIO2[27] AK17 IFC_A23/IFC_WP2_B AJ18 IFC_CS3_B/GPIO2[12] AK18 IFC_AD07/CFG_GPINPUT7 AJ19 GND AK19 SPI_CS1_B/GPIO2[1]/SDHC_DAT5 B4860 QorIQ Qonverge Data Sheet, Rev. 3 60 NXP Semiconductors Pin assignments Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name AJ20 IFC_A22/IFC_WP1_B AK20 SDHC_CMD/GPIO2[4] AJ21 SPI_CS0_B/GPIO2[0]/SDHC_DAT4 AK21 IRQ06/GPIO1[26]/TMR0 AJ22 GND AK22 IRQ08/GPIO1[28]/TMR2 AJ23 IRQ_OUT_B/EVT9_B AK23 IRQ05/GPIO1[25] AJ24 IRQ10/GPIO1[30]/TMR4 AK24 IRQ07/GPIO1[27]/TMR1 AJ25 GND AK25 TRST_B AJ26 EMI1_MDC AK26 EMI1_MDIO AJ27 IIC4_SCL/GPIO3[5]/EVT5_B AK27 CP_LOS1 AJ28 GND AK28 UART2_CTS_B/GPIO1[22]/UART4_SIN AJ29 D2_MDQ09 AK29 IIC3_SDA/GPIO3[4] AJ30 D2_MDQ12 AK30 D2_MDQ10 AJ31 D2_MDQ14 AK31 D2_MDQS1 AJ32 D2_MDQ11 AK32 D2_MDQS1_B AL1 GND AM1 AL2 D1_MDQ15 AM2 GND AL3 GND AM3 TSEC_1588_CLK_IN AL4 USB_CLK AM4 USB_D6 AL5 USB_NXT AM5 USB_DIR AL6 GND AM6 DMA1_DREQ0_B/GPIO3[0] AL7 DMA1_DACK0_B/GPIO3[1]/EVT7_B/TMR6 AM7 DMA1_DDONE0_B/GPIO3[2]/EVT8_B/TM R7 AL8 CP_SYNC4 AM8 EMI2_MDC AL9 GND AM9 RESET_REQ_B AL10 CP_RCLK0 AM10 CP_RCLK0_B AL11 CP_RCLK1 AM11 CP_RCLK1_B AL12 GND AM12 HRESET_B AL13 IFC_AD05/CFG_GPINPUT5 AM13 CLK_OUT AL14 IFC_WP0_B AM14 IFC_CLE/IFC_WBE1/CFG_RCW_SRC8 AL15 GND AM15 IFC_RB0_B/IFC_FCTA0 AL16 IFC_BCTL AM16 IFC_TE/CFG_IFC_TE AL17 IFC_AD06/CFG_GPINPUT6 AM17 IFC_RB1_B/IFC_FCTA1 AL18 GND AM18 IFC_CLK0 AL19 IFC_AVD/IFC_ALE/CFG_RSP_DIS AM19 IFC_CLK1 AL20 SPI_MISO AM20 SPI_CS3_B/GPIO2[3]/SDHC_DAT7 — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 61 Electrical characteristics Table 2. Pinout by package pin number (continued) Package pin number Package pin name Package pin number Package Pin Name AL21 GND AM21 SPI_MOSI AL22 SDHC_DAT2/GPIO2[7] AM22 SDHC_CLK/GPIO2[9] AL23 IRQ11/GPIO1[31]/TMR5 AM23 RTC/GPIO1[14] AL24 GND AM24 IRQ09/GPIO1[29]/TMR3 AL25 TDO AM25 TMS AL26 TCK AM26 TDI AL27 GND AM27 CP_LOS2 AL28 CP_LOS3 AM28 UART1_SIN/GPIO1[17]/CP_LOS5 AL29 UART1_SOUT/GPIO1[15]/CP_LOS4 AM29 CP_LOS0 AL30 GND AM30 IIC3_SCL/GPIO3[3] AL31 D2_MDQ15 AM31 GND AL32 GND AM32 2 — Electrical characteristics This section provides the AC and DC electrical specifications for the chip. 2.1 Overall DC electrical characteristics This section describes the ratings, conditions, and other characteristics. B4860 QorIQ Qonverge Data Sheet, Rev. 3 62 NXP Semiconductors Electrical characteristics 2.1.1 Absolute maximum ratings This table provides the absolute maximum ratings. Table 3. Absolute operating conditions1 Parameter Platform and cores supply voltage PLL supply voltage: • CGA1 PLL • CGA2 PLL • CGB1 PLL • CGB2 PLL • Platform PLL • DDR1 PLL • DDR2 PLL Symbol Recommended value Unit Notes VDD –0.3 to 1.1 V — –0.3 to 1.9 V — –0.3 to 1.45/1.6 V — AVDD_CGA1 AVDD_CGA2 AVDD_CGB1 AVDD_CGB2 AVDD_PLAT AVDD_DDR1 AVDD_DDR2 PLL supply voltage (SerDes) • SerDes1 PLL1 • SerDes1 PLL2 • SerDes2 PLL1 • SerDes2 PLL2 AVDD_SRDS1_PLL1 AVDD_SRDS1_PLL2 AVDD_SRDS2_PLL1 AVDD_SRDS2_PLL2 Fuse programming override supply POVDD –0.3 to 1.99 V — Thermal monitor unit supply TH_VDD –0.3 to 1.90 V 5 UART, I2C, CPRI LOS and GPIO I/O voltage DVDD –0.3 to 1.9 V/2.6 V — IFC, SPI, (e)SDHC, MPIC, Trust, power management, clocking, debug, JTAG, CPRI SYNC/RCLK, 1588, Ethernet MI, USB ULPI, DMA, GPIO, system control I/O voltage OVDD –0.3 to 1.9 V — SYSCLK, PORESET_B I/O voltage QVDD –0.3 to 1.9 V — DDR DRAM I/O voltage • DDR1 • DDR2 –0.3 to 1.45/1.6 V 2 G1VDD G2VDD Core power supply for SerDes receivers SVDD –0.3 to 1.1 V — Pad power supply for SerDes transmitters XVDD –0.3 to 1.45/1.6 V — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 63 Electrical characteristics Table 3. Absolute operating conditions1 (continued) Parameter Input voltage Symbol Recommended value Unit Notes MVIN –0.3 to (GnVDD + 0.3) V 2 MnVREF –0.3 to (GnVDD/2 + 0.3) V — UART, I2C, Ethernet MI1, CPRI LOS and GPIO signals QVIN –0.3 to (DVDD + 0.3) V 3 SYSCLK and PORESET_B signals QVIN –0.3 to (QVDD + 0.3) V 4 IFC, SPI, (e)SDHC, MPIC, Trust, power management, clocking, debug, JTAG, CPRI SYNC/RCLK, 1588, USB ULPI, DMA, GPIO, system signals OVIN –0.3 to (OVDD + 0.3) V 3 Ethernet Management Interface (EMI2) — –0.3 to 1.98 V 6 SVIN –0.4 to (SVDD + 0.3) V — Tstg –55 to 150 °C — DDR DRAM signals DDR DRAM reference SerDes signals Storage junction temperature range Note: 1. Functional operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only; functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GnVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: QVIN must not exceed QVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. The Thermal Monitoring Unit (TMU) supply is defeatured on this device. TH_VDD should be connected to an OVDD supply. 6. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels. OVDD must be powered to use this interface.. 2.1.2 Recommended operating conditions This table provides the recommended operating conditions for this chip. NOTE The values shown are the recommended operating conditions. Proper device operation outside these conditions is not guaranteed. Table 4. Recommended operating conditions Characteristic Symbol Core and platform supply voltage At initial start-up VDD During normal operation PLL supply voltage (core, platform, DDR) AVDD_CGAn AVDD_CGBn AVDD_PLAT AVDD_DDRn Recommended Value Unit Notes 1.05 V ± 30 mV V 4, 5, 6 VID ± 30 mV V 1, 4, 5 1.8 V ± 90 mV V — B4860 QorIQ Qonverge Data Sheet, Rev. 3 64 NXP Semiconductors Electrical characteristics Table 4. Recommended operating conditions (continued) PLL supply voltage (SerDes, filtered from XnVDD) AVDD_SDRSn_PLLn 1.5 V ± 75 mV 1.35 V ± 67 mV V — Fuse programming override supply POVDD 1.8 V ± 90 mV V 2 IFC, eSPI, eSHDC, MPIC, trust (TMP_DETECT_B), system OVDD control (HRESET_B), power management (ASLEEP), DDRCLK, RTC, debug (EVT*, CKSTP_OUT_B, CLK_OUT), JTAG, CPRI SYNC/RCLK, 1588, US ULPI, DMA 1.8 V ± 90 mV V — UART, I2C, Ethernet MI1, CPRI LOS, and GPIO I/O voltage DVDD 2.5 V ± 125 mV 1.8 V ± 90 mV V — SYSCLK and PORESET I/O voltage QVDD 1.8 V ± 90mV V 7 DDR DRAM I/O voltage GnVDD 1.5 V ± 75 mV V — DDR3 DDR3L 1.35 V ± 67 mV — Main power supply for internal circuitry of SerDes and pad power SVDD supply for SerDes receivers 1.0 V +50mV/-30mV V — Pad power supply for SerDes transmitters XVDD 1.5 V ± 75 mV 1.35 V ± 67 mV V — Ethernet management interface 2 (EMI2) I/O voltage — 1.2 V ± 60 mV V 8 Input voltage DDR3 and DDR3L DRAM signals MVIN GND to GnVDD V — DDR3 and DDR3L DRAM reference Dn_MVREF GnVDD/2 ± 1% V — UART, I2C, Ethernet MI1, CPRI DVIN LOS and GPIO signals GND to DVDD V — eSHDC, eSPI, DMA, MPIC, OVIN GPIO, system control and power management, clocking, debug, IFC, Dn_DDRCLK supply, and JTAG signals GND to OVDD V — SYSCLK, PORESET signals QVIN GND to QVDD V — SerDes signals SVIN GND to SVDD V — Ethernet management interface 2 (EMI2) signals — GND to 1.2 V V 3 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 65 Electrical characteristics Table 4. Recommended operating conditions (continued) Operating temperature range Normal operation TA, TJ TA = 0 (min) to TJ = 105 (max) °C — Extended Temperature TA, TJ TA = -40 (min) to TJ = 105 (max) °C — TA = 0 (min) to TJ = 70 (max) °C 2 Secure boot fuse programming TA, TJ Note: 1. The Voltage ID (VID) operating range is between 0.95 V and 1.05 V. Regulator selection should be based on a Vout range of at least 0.9 V to 1.1 V, with resolution of 12.5 mV or better. See Section 3.2.1, “Voltage ID (VID) controllable supply” for more details. 2. POVDD must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range only –0 –70°C during secure boot fuse programming. For all other operating conditions, POVDD must be tied to GND, subject to the power sequencing constraints shown in Section 2.2, “Power sequencing.” 3. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage levels. 4. See Section 3.2.2, “Core supply voltage filtering,” for additional information. 5. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the sense pin. 6. Operation at 1.05 V is allowable for up to 1 second at initial power on. 7. Add a bypass cap of 0.1uF on this power ball pin. 8. These pins should be pulled up to 1.2 V through a 180 Ω (1% accuracy) resistor for EMI2_MDC and 330 Ω (1% accuracy) resistor for EMI2_MDIO. When Ethernet Management Interface 2 unused, EMI2_MDIO’s external pull-up resistor can be tied to OVDD B4860 QorIQ Qonverge Data Sheet, Rev. 3 66 NXP Semiconductors Electrical characteristics This figure shows the undershoot and overshoot voltages at the interfaces of the chip. [Nominal]D/Q/O/GnVDD + 20% D/Q/O/GnVDD + 5% D/Q/O/GnVDD VIH GND GND – 0.3 V VIL GND – 0.7 V Not to exceed 10% of tCLOCK Note: tCLOCK refers to the clock period associated with the respective interface: For I2C and JTAG, tCLOCK refers to SYSCLK. For DDR GnVDD, tCLOCK refers to Dn_DDRCLK. For SPI OVDD, tCLOCK refers to SPI_CLK. For SerDes XVDD, tCLOCK refers to SD_REF_CLK. Figure 7. Overshoot/Undershoot voltage for DVDD/QVDD/OVDD/GnVDD See Table 4 for actual recommended core voltage. Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in Table 4. The input voltage threshold scales with respect to the associated I/O supply voltage. DVDD, QVDD, and OVDD-based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential receivers referenced by the externally supplied MnVREF signal (nominally set to GnVDD/2) as is appropriate for the SSTL_1.35/SSTL_1.5 electrical signaling standard. The DDR DQS receivers cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded. 2.1.3 Output driver characteristics This chip provides information on the characteristics of the output driver strengths. These values are preliminary estimates. Table 5. Output drive capability Driver type DDR3 signal Output impedance (Ω) Supply voltage Notes 18 (full-strength mode) 27 (half-strength mode) GnVDD= 1.5 V 1 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 67 Electrical characteristics Table 5. Output drive capability (continued) Driver type DDR3L signal Output impedance (Ω) Supply voltage Notes 18 (full-strength mode) 27 (half-strength mode) GnVDD = 1.35 V 1 OVDD = 1.8 V — DVDD = 2.5 V DVDD = 1.8 V — IFC, eSPI, eSDHC, MPIC, Trust, power management, clocking, debug, JTAG, CPRI SYNC/RCLK, 1588, USB ULPI, DMA, GPIO, system control, Reset 45 DUART, I2C, Ethernet MI, CPRI-LOS, GPIO 45 Note: 1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at GnVDD (min). 2.2 Power sequencing The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. For power up, these requirements are as follows: 1. 2. 3. There are no restrictions on the order of Power supplies bringing up. During power up, drive POVDD = GND. — PORESET_B input must be driven asserted and held during this step. Negate PORESET_B input as long as the required assertion/hold time has been met per Table 13. For secure boot fuse programming, use the following steps: a) After negation of PORESET_B, drive POVDD = 1.8 V after a required minimum delay per Table 6. b) After fuse programming is completed, it is required to return POVDD = GND before the system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 6. See Section 5, “Security fuse processor,” for additional details. WARNING No activity other than that required for secure boot fuse programming is permitted while POVDD is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND. From a system standpoint, if any of the I/O power supplies ramp prior to the VDD supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device. WARNING Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary. All supplies must be at their stable values within 75 ms. B4860 QorIQ Qonverge Data Sheet, Rev. 3 68 NXP Semiconductors Electrical characteristics This figure provides the POVDD timing diagram. Fuse programming POVDD 10% POVDD 10% POVDD 90% VDD tPOVDD_VDD VDD tPOVDD_PROG 90% OVDD 90% OVDD PORESET_B tPOVDD_RST tPOVDD_DELAY NOTE: POVDD must be stable at 1.8 V prior to initiating fuse programming. Figure 8. POVDD timing diagram This table provides information on the power-down and power-up sequence parameters for POVDD. Table 6. POVDD timing5 Driver type Min Max Unit Notes tPOVDD_DELAY 100 — SYSCLKs 1 tPOVDD_PROG 0 — μs 2 tPOVDD_VDD 0 — μs 3 tPOVDD_RST 0 — μs 4 Note: 1. Delay required from the deassertion of PORESET_B to driving POVDD ramp up. Delay measured from PORESET_B deassertion at 90% OVDD to 10% POVDD ramp up. 2. Delay required from fuse programming finished to POVDD ramp down start. Fuse programming must complete while POVDD is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted while POVDD is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while POVDD = GND. After fuse programming is completed, it is required to return POVDD = GND. 3. Delay required from POVDD ramp down complete to VDD ramp down start. POVDD must be grounded to minimum 10% POVDD before VDD is at 90% VDD. 4. Delay required from POVDD ramp down complete to PORESET_B assertion. POVDD must be grounded to minimum 10% POVDD before PORESET_B assertion reaches 90% OVDD. 5. Only two secure boot fuse programming events are permitted per lifetime of a device. NOTE While VDD is ramping, current may be supplied from VDD through the chip to GnVDD. Nevertheless, GnVDD from an external supply should follow the sequencing described above. 2.3 Power-down requirements The power-down cycle must complete such that power supply values are below 0.4 V before a new power-up cycle can be started. If performing secure boot fuse programming per Section 2.2, “Power sequencing,” it is required that POVDD = GND before the system is power cycled (PORESET_B assertion) or powered down (VDD ramp down) per the required timing specified in Table 6. B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 69 Electrical characteristics 2.4 Power characteristics Because it depends strongly on application type, the power characteristics for the average power and instantaneous peak current numbers are supplied by the device’s detailed power calculator. 2.5 Power-on ramp rate This section describes the AC electrical specifications for the power-on ramp rate requirements. Controlling the maximum power-on ramp rate is required to avoid excess in-rush current. This table provides the power supply ramp rate specifications. Table 7. Power supply ramp rate Parameter Min Max Unit Notes Required ramp rate for all voltage supplies (including OVDD/DVDD/ GnVDD/QVDD/SVDD/XVDD, core VDD supply, MnVREF and all AVDD supplies.) — 25 V/ms 1, 2 Required ramp rate for POVDD — 25 V/ms 1, 2 Note: 1. Ramp rate is specified as a linear ramp from 10 to 90%. If nonlinear (for example, exponential), the maximum rate of change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry. If needed to slow down the rate, usage of larger capacitors is recommended. 2. Over full recommended operating temperature range (see Table 4) 2.6 2.6.1 Input clocks System clock (SYSCLK) timing specifications This section provides the system clock DC and AC timing specifications. 2.6.1.1 System clock DC timing specifications This table provides the system clock (SYSCLK) DC specifications. Table 8. SYSCLK DC electrical characteristics At recommended operating conditions with QVDD = 1.8 V, see Table 4. Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 1.25 — — V 1 Input low voltage VIL — — 0.6 V 1 Input capacitance CIN — 7 12 pF — Input current (OVIN= 0 V or OVIN = QVDD) IIN — — ± 50 μA 2 Note: 1. The min VILand max VIH values are based on the respective min and max QVIN values found in Table 4. 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” B4860 QorIQ Qonverge Data Sheet, Rev. 3 70 NXP Semiconductors Electrical characteristics 2.6.1.2 System clock AC timing specifications This table provides the system clock (SYSCLK) AC timing specifications. Table 9. SYSCLK AC timing specifications At recommended operating conditions with OVDD = 1.8 V, see Table 4. Parameter/Condition Symbol Min Typ Max Unit Notes SYSCLK frequency fSYSCLK 66.667 — 133.333 MHz 1, 2 SYSCLK cycle time tSYSCLK 7.5 — 15 ns 1, 2 SYSCLK duty cycle tKHK / tSYSCLK 40 50 60 % 2 SYSCLK slew rate — 1 — 4 V/ns 3 SYSCLK peak period jitter — — — ±150 ps — SYSCLK jitter phase noise at –56 dBc — — — 500 KHz 4 AC Input Swing Limits at 1.8 V QVDD ΔVAC 0.35 x QVDD — 0.65 x QVDD V — Notes: 1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their respective maximum or minimum operating frequencies. 2. Measured at the rising edge and/or the falling edge at QVDD/2. 3. Slew rate is measured from 10% ~ 90% of VIL to VIH. 4. Phase noise is calculated as FFT of TIE jitter. 2.6.2 Spread-spectrum sources Spread-spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet industry and government requirements. These clock sources intentionally add long-term jitter to diffuse the EMI spectral content. The jitter specification given in this table considers short-term (cycle-to-cycle) jitter only. The clock generator’s cycle-to-cycle output jitter should meet the chip’s input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns; the chip is compatible with spread spectrum sources if the recommendations listed in this table are observed. Table 10. Spread-spectrum clock source recommendations At recommended operating conditions with OVDD = 1.8 V, see Table 4. Parameter Min Max Unit Notes Frequency modulation — 60 kHz — Frequency spread — 1.0 % 1, 2 Notes: 1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and maximum specifications given in Table 9. 2. Maximum spread spectrum frequency may not result in exceeding any maximum operating frequency of the device. CAUTION The processor’s minimum and maximum SYSCLK and core/platform/DDR frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated core/platform/DDR frequency should avoid violating the stated limits by using down-spreading only. B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 71 Electrical characteristics 2.6.3 Real-time clock timing The real-time clock timing (RTC) input is sampled by the platform clock. The output of the sampling latch is then used as an input to the counters of the MPIC and the time base unit of the core; there is no need for jitter specification. The minimum period of the RTC signal should be greater than or equal to 16× the period of the platform clock with a 50% duty cycle. There is no minimum RTC frequency; RTC may be grounded if not needed. 2.6.4 DDR clock timing 2.6.4.1 DDR D1_DDRCLK/D2_DDRCLK clocks DC timing specifications This table provides the system clock (MCLK) DC specifications. Table 11. D1_DDRCLK3/D2_DDRCLK DC electrical characteristics At recommended operating conditions with OVDD = 1.8v, see Table 4. Parameter Symbol Min Typical Max Unit Notes Input high voltage VIH 1.25 — — V 1 Input low voltage VIL — — 0.6 V 1 Input capacitance CIN — 7 12 pF — Input current (OVIN= 0 V or OVIN = OVDD) IIN — — ± 50 μA 2 Note: 1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 4. 2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Section 2.1.2, “Recommended operating conditions.” 3. D1_DDRCLK must toggle in order to get out of PORESET, even if the DDR1 interface is not required. AVDD_DDR1 voltage must be supplied. 2.6.4.2 DDR D1_DDRCLK/D2_DDRCLK clocks AC timing specifications This table provides the system clock (D1_DDRCLK/D2_DDRCLK) AC timing specifications. Table 12. Dn_DDRCLK AC timing specifications At recommended operating conditions with OVDD = 1.8V, see Table 4. Parameter/Condition Symbol Min Typ Max Unit Notes Dn_DDRCLK frequency fMCLK 66.667 — 133.333 MHz 1, 2 Dn_DDRCLK cycle time tMCLK 7.5 — 15 ns 1, 2 Dn_DDRCLK duty cycle tKHK / tMCLK 40 50 60 % 2 Dn_DDRCLK slew rate — 1 — 4 V/ns 3 B4860 QorIQ Qonverge Data Sheet, Rev. 3 72 NXP Semiconductors Electrical characteristics Table 12. Dn_DDRCLK AC timing specifications (continued) At recommended operating conditions with OVDD = 1.8V, see Table 4. Parameter/Condition Symbol Min Typ Max Unit Notes Dn_DDRCLK peak period jitter — — — ± 150 ps — Dn_DDRCLK jitter phase noise at –56 dBc — — — 500 KHz 4 ΔVAC 0.35 x OVDD — 0.65 x OVDD V — AC Input Swing Limits at 1.8 V OVDD Notes: 1. Caution: The relevant clock ratio settings must be chosen such that the resulting D1_DDRCLK/D2_DDRCLK frequency do not exceed their respective maximum or minimum operating frequencies. 2. Measured at the rising edge and/or the falling edge at OVDD/2. 3. Slew rate is measured from 10% ~ 90% of VIL to VIH. 4. Phase noise is calculated as FFT of TIE jitter. 2.6.5 Other input clocks A description of the overall clocking of this device is available in the chip reference manual in the form of a clock subsystem block diagram. For information about the input clock requirements of functional modules sourced external of the chip, such as SerDes, I2C, eSDHC, IFC, USB, and 1588, see the specific interface section. 2.7 RESET initialization This table describes the AC electrical specifications for the RESET initialization timing. Table 13. RESET Initialization timing specifications Parameter/Condition Min Max Unit Notes Required assertion time of PORESET_B 1 — ms 3 Required input assertion time of HRESET_B 32 — SYSCLKs 1, 2 Maximum rise/fall time of HRESET_B — 1 SYSCLK 4 100 — μs — Input setup time for POR configs with respect to negation of PORESET_B 4 — SYSCLKs 1 Input hold time for all POR configs with respect to negation of PORESET_B 2 — SYSCLKs 1 Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of PORESET_B — 5 SYSCLKs 1 PLL input setup time with stable SYSCLK before HRESET_B negation Notes: 1. SYSCLK is the primary clock input for the chip. 2. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is documented in the “Power-On Reset Sequence” section of the chip reference manual. 3. PORESET_B must be driven asserted before the core and platform power supplies are powered up. 4. The system/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 73 Electrical characteristics This table provides the PLL lock times. Table 14. PLL lock times Parameter/Condition PLL lock times 2.8 Min Max Unit Notes — 100 μs — DDR3 and DDR3L SDRAM controller This section describes the DC and AC electrical specifications for the DDR3 and DDR3L SDRAM controller interface. Note that the required GnVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the GnVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM. NOTE When operating at DDR data rates of 1866 MT/s, only one dual-ranked module per memory controller is supported. 2.8.1 DDR3 and DDR3L SDRAM interface DC electrical characteristics This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM. Table 15. DDR3 SDRAM interface DC electrical characteristics (GnVDD = 1.5 V)1 For recommended operating conditions, see Table 4. Parameter Symbol Min Max Unit Note MnVREF 0.49 × GnVDD 0.51 × GnVDD V 2, 3, 4 Input high voltage VIH MnVREF + 0.100 GnVDD V 5 Input low voltage VIL GND MnVREF – 0.100 V 5 I/O leakage current IOZ –50 50 μA 6 I/O reference voltage Notes: 1. GnVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage supply may or may not be from the same source. 2. MnVREFis expected to be equal to 0.5 × GnVDD and to track GnVDD DC variations as measured at the receiver. Peak-to-peak noise on MnVREFmay not exceed the MnVREFDC level by more than ±1% of the DC value (that is, ±15 mV). 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to MnVREFwith a min value of MnVREF – 0.04 and a max value of MnVREF + 0.04. VTT should track variations in the DC level of MnVREF. 4. The voltage regulator for MnVREFmust meet the specifications stated in Table 18. 5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models. 6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GnVDD. B4860 QorIQ Qonverge Data Sheet, Rev. 3 74 NXP Semiconductors Electrical characteristics This table provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3L SDRAM. Table 16. DDR3L SDRAM interface DC electrical characteristics (GnVDD = 1.35 V)1 For recommended operating conditions, see Table 4. Parameter Symbol Min Max Unit Note MnVREF 0.49 × GnVDD 0.51 × GnVDD V 2, 3, 4 Input high voltage VIH MnVREF + 0.090 GnVDD V 5 Input low voltage VIL GND MnVREF – 0.090 V 5 I/O leakage current IOZ –100 100 μA 6 I/O reference voltage Notes: 1. GnVDD is expected to be within 50 mV of the DRAM’s voltage supply at all times. The DRAM’s and memory controller’s voltage supply may or may not be from the same source. 2. MnVREF is expected to be equal to 0.5 × GnVDD and to track GnVDD DC variations as measured at the receiver. Peak-to-peak noise on MnVREF may not exceed the MnVREF DC level by more than ±1% of the DC value (that is, ±13.5mV). 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be equal to MnVREF with a min value of MnVREF – 0.04 and a max value of MnVREF + 0.04. VTT should track variations in the DC level of MnVREF. 4. The voltage regulator for MnVREF must meet the specifications stated in Table 18. 5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models. 6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GnVDD. 7. See the IBIS model for the complete output IV curve characteristics. This table provides the DDR controller interface capacitance for DDR3 and DDR3L. Table 17. DDR3 and DDR3L SDRAM capacitance For recommended operating conditions, see Table 4. Parameter Symbol Min Max Unit Notes Input/output capacitance: DQ, DQS, DQS_B CIO 6 8 pF — Delta input/output capacitance: DQ, DQS, DQS_B CDIO — 0.5 pF — This table provides the current draw characteristics for MnVREF. Table 18. Current draw characteristics for MnVREF For recommended operating conditions, see Table 4. Parameter Symbol Min Max Unit Notes Current draw for DDR3 SDRAM for MnVREF IMnVREF — 500 μA — Current draw for DDR3L SDRAM for MnVREF IMnVREF — 500 μA — B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 75 Electrical characteristics 2.8.2 DDR3 and DDR3L SDRAM interface AC timing specifications This section provides the AC timing specifications for the DDR SDRAM controller interface. The DDR controller supports DDR3 and DDR3L memories. Note that the required GnVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the required GnVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM. 2.8.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications This table provides the input AC timing specifications for the DDR controller when interfacing to DDR3 SDRAM. Table 19. DDR3 and DDR3L SDRAM interface input AC timing specifications For recommended operating conditions, see Table 4. Parameter Symbol Controller Skew for MDQS—MDQ/MECC Min Max tCISKEW 1866 MT/s data rate –93 93 1600 MT/s data rate –112 112 1333 MT/s data rate –125 125 1200 MT/s data rate –142 142 1066 MT/s data rate –170 170 Tolerated Skew for MDQS—MDQ/MECC tDISKEW 1866 MT/s data rate –175 175 1600 MT/s data rate –200 200 1333 MT/s data rate –250 250 1200 MT/s data rate –275 275 1066 MT/s data rate –300 300 Unit Notes ps 1 ps 2 Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This must be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW = ±(T ÷ 4 – abs(tCISKEW)), where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. B4860 QorIQ Qonverge Data Sheet, Rev. 3 76 NXP Semiconductors Electrical characteristics This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram. MCK_B[n] MCK[n] tMCK MDQS[n] tDISKEW MDQ[x] D0 D1 tDISKEW tDISKEW Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram 2.8.2.2 DDR3 and DDR3L SDRAM interface output AC timing specifications This table contains the output AC timing targets for the DDR3 SDRAM interface. Table 20. DDR3 and DDR3L SDRAM interface output AC timing specifications For recommended operating conditions, see Table 4 Parameter MCK[n] cycle time ADDR/CMD output setup with respect to MCK Symbol1 Min Max Unit Notes tMCK 1.072 1.876 ns 2 ns 3 ns 3 ns 4 tDDKHAS 1866 MT/s data rate 0.410 — 1600 MT/s data rate 0.495 — 1333 MT/s data rate 0.606 — 1200 MT/s data rate 0.675 — 1066 MT/s data rate 0.744 — ADDR/CMD output hold with respect to MCK tDDKHAX 1866 MT/s data rate 0.390 — 1600 MT/s data rate 0.495 — 1333 MT/s data rate 0.606 — 1200 MT/s data rate 0.675 — 1066 MT/s data rate 0.744 — MCK to MDQS skew tDDKHMH > 1600 MT/s data rate -0.150 -0.150 4,6 data rate > 1066MT/s & =< 1600 MT/s -0.245 0.245 4,6 B4860 QorIQ Qonverge Data Sheet, Rev. 3 NXP Semiconductors 77 Electrical characteristics Table 20. DDR3 and DDR3L SDRAM interface output AC timing specifications (continued) For recommended operating conditions, see Table 4 Parameter MDQ/MECC/MDM output Data eye Symbol1 Min Max tDDKXDEYE 1866 MT/s data rate 0.350 — 1600 MT/s data rate 0.400 — 1333 MT/s data rate 0.500 — 1200 MT/s data rate 0.550 — 1066 MT/s data rate 0.600 — Unit Notes ns 5 MDQS preamble tDDKHMP 0.9 x tMCK — ns — MDQS postamble tDDKHME 0.4 x tMCK 0.6 x tMCK ns — Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. 2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of the timing modifications enabled by use of these bits. 5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization. 6. For data rates of 1200 MT/s and higher, it is required to program the start value of the DQS adjust for write leveling. NOTE For the ADDR/CMD setup and hold specifications in Table 20, it is assumed that the clock control register is set to adjust the memory clocks by ½ applied cycle. B4860 QorIQ Qonverge Data Sheet, Rev. 3 78 NXP Semiconductors Electrical characteristics This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] tMCK tDDKHMH(max) MDQS tDDKHMH(min) MDQS Figure 10. tDDKHMH timing diagram This figure shows the DDR3 and DDR3L SDRAM output timing diagram. 0&.B% 0&. V0&. W''.+$6 W''.+$; $''5&0' :ULWH$ 1223 W''.+03 W''.+0+ 0'46>Q@ W''.+0( 0'4>[@ ' ' W''.;'(