BF1202WR

DISCRETE SEMICONDUCTORS DATA SHEET BF1202; BF1202R; BF1202WR N-channel dual-gate PoLo MOS-FETs Product specification Supersedes data of 2000 Mar 29 2010 Sep 16 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs FEATURES  Short channel transistor with high forward transfer admittance to input capacitance ratio  Low noise gain controlled amplifier  Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. APPLICATIONS  VHF and UHF applications with 3 to 9 V supply voltage, such as digital and analogue television tuners and professional communications equipment. DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1202, BF1202R and BF1202WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-ss Crss F Xmod Tj PARAMETER drain-source voltage drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation operating junction temperature CAUTION f = 1 MHz f = 800 MHz PINNING PIN 1 2 3 4 BF1202; BF1202R; BF1202WR DESCRIPTION source drain gate 2 gate 1 handbook, 2 columns 3 4 2 Top view 1 MSB035 Marking code legend: * = - : made in Hong Kong * = p : made in Hong Kong * = t : made in Malaysia BF1202R marking code: LE* Fig.2 Simplified outline (SOT143R). handbook, 2 columns 4 3 lfpage 3 4 1 Top view 2 MSB014 2 Top view 1 MSB842 BF1202 marking code: LD* BF1202WR marking code: LE* Fig.1 Simplified outline (SOT143B). Fig.3 Simplified outline (SOT343R). CONDITIONS    MIN.    TYP. MAX. 10 30 200 40 2.2 30 1.8  150 UNIT V mA mW mS pF fF dB dBV C 25    100  30 1.7 15 1.1 105  input level for k = 1% at 40 dB AGC This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. 2010 Sep 16 2 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDS ID IG1 IG2 Ptot PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation BF1202; BF1202R BF1202WR Tstg Tj Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s BF1202; BF1202R BF1202WR PARAMETER thermal resistance from junction to soldering point 185 155 K/W K/W VALUE UNIT storage temperature operating junction temperature Ts  113 C; note 1 Ts  119 C; note 1   65  200 200 +150 150 mW mW C C CONDITIONS     MIN. MAX. 10 30 10 10 V mA mA mA UNIT handbook, halfpage 250 Ptot MCD951 (mW) 200 (2) (1) 150 100 50 0 0 50 100 150 Ts (°C) 200 (1) BF1202WR. (2) BF1202; BF1202R. Fig.4 Power derating curve. 2010 Sep 16 3 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs STATIC CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL V(BR)DSS PARAMETER drain-source breakdown voltage BF1202; BF1202R; BF1202WR CONDITIONS VG1-S = VG2-S = 0; ID = 10 A VG2-S = VDS = 0; IG1-S = 10 mA VG1-S = VDS = 0; IG2-S = 10 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VG2-S = 4 V; VDS = 5 V; ID = 100 A VG1-S = 5 V; VDS = 5 V; ID = 100 A VG2-S = 4 V; VDS = 5 V; RG1 = 120 k; note 1 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 4 V MIN. 10 6 6 0.5 0.5 0.3 0.3 8   MAX.    1.5 1.5 1.0 1.2 16 50 20 UNIT V V V V V V V mA nA nA V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS gate 2-source breakdown voltage V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-SS IG2-SS Note 1. RG1 connects G1 to VGG = 5 V. forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance noise figure f = 1 MHz f = 1 MHz f = 1 MHz f = 10.7 MHz; GS = 20 mS; BS = 0 f = 400 MHz; YS = YS opt f = 800 MHz; YS = YS opt Gtr power gain f = 200 MHz; GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt f = 400 MHz; GS = 2 mS; BS = BS opt; GL = 1 mS; BL = BL opt f = 800 MHz; GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt Xmod cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 1 at 0 dB AGC at 10 dB AGC at 40 dB AGC Note 1. Measured in Fig.21 test circuit. 90  100  92 105    dBV dBV dBV CONDITIONS pulsed; Tj = 25 C MIN. 25           TYP. 30 1.7 1 0.85 15 9 0.9 1.1 34.5 30.5 26.5 MAX. 40 2.2   30 11 1.5 1.8    UNIT mS pF pF pF fF dB dB dB dB dB dB reverse transfer capacitance f = 1 MHz 2010 Sep 16 4 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 20 MCD952 ID (mA) VG2-S = 4 V 3.5 V 3V 2.5 V handbook, halfpage 24 MCD953 16 2V ID (mA) 16 VG1-S = 1.5 V 1.4 V 1.3 V 12 8 1.5 V 8 1.2 V 1.1 V 1V 4 1V 0 0 0.4 0.8 1.2 1.6 2 VG1-S (V) 0 0 2 4 6 8 0.9 V 10 VDS (V) VDS = 5 V. Tj = 25 C. VG2-S = 4 V. Tj = 25 C. Fig.5 Transfer characteristics; typical values. Fig.6 Output characteristics; typical values. handbook, halfpage 100 MCD954 IG1 (μA) VG2-S = 4 V 3.5 V 3V handbook, halfpage 40 MCD955 yfs (mS) 30 VG2-S = 4 V 3.5 V 80 3V 60 2.5 V 20 2.5 V 40 2V 10 20 1.5 V 0 0 0.5 1 1.5 1V 2V 0 2 2.5 VG1-S (V) 0 4 8 12 16 20 ID (mA) VDS = 5 V. Tj = 25 C. VDS = 5 V. Tj = 25 C. Fig.7 Gate 1 current as a function of gate 1 voltage; typical values. Fig.8 Forward transfer admittance as a function of drain current; typical values. 2010 Sep 16 5 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 20 MCD956 ID (mA) handbook, halfpage 16 MCD957 16 ID (mA) 12 12 8 8 4 4 0 0 10 20 30 40 50 IG1 (μA) 0 0 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V. Tj = 25 C. VDS = 5 V; VG2-S = 4 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21. Fig.9 Drain current as a function of gate 1 current; typical values. Fig.10 Drain current as a function of gate 1 supply voltage (= VGG); typical values. handbook, halfpage 20 MCD958 ID (mA) RG1 = 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 180 kΩ handbook, halfpage 16 MCD959 ID (mA) 12 VGG = 5 V 4.5 V 4V 3.5 V 16 12 8 3V 8 220 kΩ 4 4 0 0 2 4 6 VGG = VDS (V) 0 0 2 4 VG2-S (V) 6 VG2-S = 4 V; Tj = 25 C. RG1 connected to VGG; see Fig.21. VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21. Fig.11 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. Fig.12 Drain current as a function of gate 2 voltage; typical values. 2010 Sep 16 6 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 40 MCD960 IG1 (μA) 30 handbook, halfpage gain 0 MCD961 VGG = 5 V 4.5 V 4V reduction (dB) −10 −20 20 3.5 V 3V −30 10 −40 0 0 2 4 VG2-S (V) 6 −50 0 1 2 3 VAGC (V) 4 VDS = 5 V; Tj = 25 C. RG1 = 120 k (connected to VGG); see Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 120 k; f = 50 MHz; Tamb = 25 C. Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. handbook, halfpage 120 MCD962 Vunw (dBμV) 110 handbook, halfpage 16 MCD963 ID (mA) 12 100 8 90 4 80 0 10 20 30 40 50 gain reduction (dB) 0 0 10 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 120 k; f= 50 MHz; funw = 60 MHz; Tamb = 25 C. VDS = 5 V; VGG = 5 V; RG1 = 120 k; f = 50 MHz; Tamb = 25 C. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; Fig.21. Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. 2010 Sep 16 7 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR 102 handbook, halfpage Yis (mS) 10 MCD964 103 handbook, halfpage yrs (μS) 102 bis gis yrs 10 ϕrs MCD965 −103 ϕrs (deg) −102 1 −10 10−1 10 102 f (GHz) 103 1 10 102 f (MHz) −1 103 VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. Fig.17 Input admittance as a function of frequency; typical values. Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. 102 handbook, halfpage yfs (mS) MCD966 −102 ϕfs (deg) handbook, halfpage 10 MCD967 yfs Yos (mS) 1 bos 10 ϕfs −10 10−1 gos 1 10 102 f (MHz) −1 103 10−2 10 102 f (MHz) 103 VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 C. Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. Fig.20 Output admittance as a function of frequency; typical values. 2010 Sep 16 8 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, full pagewidth VAGC R1 10 kΩ C1 4.7 nF C3 4.7 nF C2 RGEN 50 Ω VI R2 50 Ω 4.7 nF RG1 DUT ≈ 2.2 μH C4 4.7 nF L1 RL 50 Ω VGG VDS MGS315 Fig.21 Cross-modulation test set-up. Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C s11 MAGNITUDE (ratio) 0.988 0.988 0.984 0.977 0.965 0.951 0.936 0.919 0.903 0.887 0.870 ANGLE (deg) 3.26 6.52 12.99 19.39 25.65 31.76 37.68 43.42 48.94 54.25 59.34 s21 MAGNITUDE (ratio) 2.989 3.017 2.990 2.949 2.913 2.853 2.793 2.727 2.664 2.593 2.518 ANGLE (deg) 176.2 172.5 165.0 157.6 150.3 143.2 136.3 129.5 123.0 116.7 110.5 s12 MAGNITUDE (ratio) 0.0005 0.0009 0.0018 0.0027 0.0036 0.0039 0.0042 0.0044 0.0043 0.0041 0.0038 ANGLE (deg) 92.6 88.0 82.5 78.2 75.4 71.8 69.9 68.9 68.5 70.7 72.4 s22 MAGNITUDE (ratio) 0.995 0.995 0.994 0.992 0.990 0.988 0.986 0.984 0.980 0.975 0.970 ANGLE (deg) 1.50 3.01 5.95 8.86 11.79 14.65 17.41 20.10 22.69 25.27 27.90 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C f (MHz) 400 800 Fmin (dB) 0.9 1.1 opt (ratio) 0.805 0.725 (deg) 28.5 47.2 Rn () 50 40 2010 Sep 16 9 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs PACKAGE OUTLINES Plastic surface-mounted package; 4 leads BF1202; BF1202R; BF1202WR SOT143B D B E A X y vMA HE e bp wM B 4 3 Q A A1 c 1 b1 e1 2 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT143B REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-11-16 06-03-16 2010 Sep 16 10 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR Plastic surface-mounted package; reverse pinning; 4 leads SOT143R D B E A X y vMA HE e bp wM B 3 4 Q A A1 c 2 b1 e1 1 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT143R REFERENCES IEC JEDEC JEITA SC-61AA EUROPEAN PROJECTION ISSUE DATE 04-11-16 06-03-16 2010 Sep 16 11 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR Plastic surface-mounted package; reverse pinning; 4 leads SOT343R D B E A X y HE e vMA 3 4 Q A A1 c 2 wM B bp e1 b1 1 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 b1 0.7 0.5 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 1.15 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT343R REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-21 06-03-16 2010 Sep 16 12 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs DATA SHEET STATUS DOCUMENT STATUS(1) Objective data sheet Preliminary data sheet Product data sheet Notes PRODUCT STATUS(2) Development Qualification Production BF1202; BF1202R; BF1202WR DEFINITION This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DISCLAIMERS Limited warranty and liability  Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use  NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2010 Sep 16 13 property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications  Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs Limiting values  Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale  NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license  Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control  This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. BF1202; BF1202R; BF1202WR Quick reference data  The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products  Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 2010 Sep 16 14 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for the marking codes and the package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/03/pp15 Date of release: 2010 Sep 16