BF904AWR

BF904A; BF904AR; BF904AWR N-channel dual gate MOS-FETs Rev. 04 — 13 November 2007 Product data sheet IMPORTANT NOTICE Dear customer, As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors, which will be used in future data sheets together with new contact details. In data sheets where the previous Philips references remain, please use the new links as shown below. http://www.philips.semiconductors.com use http://www.nxp.com http://www.semiconductors.philips.com use http://www.nxp.com (Internet) sales.addresses@www.semiconductors.philips.com use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - © Koninklijke Philips Electronics N.V. (year). All rights reserved is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, NXP Semiconductors NXP Semiconductors Product specification N-channel dual gate MOS-FETs FEATURES • Specially designed for use at 5 V supply voltage • Short channel transistor with high transfer admittance to input capacitance ratio • Low noise gain controlled amplifier up to 1 GHz • Superior cross-modulation performance during AGC. APPLICATIONS • VHF and UHF applications with 3 to 7 V supply voltage such as television tuners and professional communications equipment. DESCRIPTION Enhancement type field-effect transistors. The transistors consist of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. The BF904A, BF904AR and BF904AWR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-ss Crss F Tj PARAMETER drain-source voltage drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure operating junction temperature CAUTION f = 1 MHz f = 800 MHz Ts ≤ 110 °C 2 Top view BF904A; BF904AR; BF904AWR PINNING PIN 1 2 3 4 DESCRIPTION source drain gate 2 gate 1 1 Top view 2 MSB014 handbook, 2 columns 4 3 BF904A marking code: %M7. Fig.1 Simplified outline (SOT143B). handbook, 2 columns 3 4 halfpage 3 4 1 2 MSB035 1 MSB842 Top view BF904AR marking code: %M8. BF904AWR marking code: MH. Fig.2 Simplified outline (SOT143R). Fig.3 Simplified outline (SOT343R). CONDITIONS MIN. − − − 22 − − − − TYP. − − − 25 2.2 25 2 − MAX. 7 30 200 30 2.6 35 − 150 UNIT V mA mW mS pF fF dB °C This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. Rev. 04 - 13 November 2007 2 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot Tstg Tj Note 1. Ts is the temperature of the soldering point of the source lead. PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation storage temperature operating junction temperature Ts ≤ 110 °C; note 1; see Fig.4 CONDITIONS − − − − − −65 − MIN. 7 30 ±10 ±10 200 +150 150 MAX. V mA mA mA mW °C °C UNIT MGL615 handbook, halfpage 250 Ptot (mW) 200 150 100 50 0 0 50 100 150 Ts (°C) 200 Fig.4 Power derating curve. Rev. 04 - 13 November 2007 3 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs THERMAL CHARACTERISTICS SYMBOL Rth j-s Note 1. Soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-SS IG2-SS Note 1. RG1 connects gate 1 to VGG = 5 V; see Fig.21. PARAMETER gate 1-source breakdown voltage gate 2-source breakdown voltage forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current PARAMETER thermal resistance from junction to soldering point BF904A; BF904AR; BF904AWR CONDITIONS note 1 VALUE 200 UNIT K/W CONDITIONS VG2-S = VDS = 0; IG1-S = 10 mA VG1-S = VDS = 0; IG2-S = 10 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VG2-S = 4 V; VDS = 5 V; ID = 20 µA VG1-S = VDS = 5 V; ID = 20 µA VG2-S = 4 V; VDS = 5 V; RG1 = 120 kΩ; note 1 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 5 V MIN. 6 6 0.5 0.5 0.3 0.3 8 − − MAX. 15 15 1.5 1.5 1 1.2 13 50 50 UNIT V V V V V V mA nA nA DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VDS = 5 V; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL yfs Cig1-s Cig2-s Cos Crs F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 drain-source capacitance noise figure f = 1 MHz f = 1 MHz f = 1 MHz f = 200 MHz; GS = 2 mS; BS = BSopt f = 800 MHz; GS = GSopt; BS = BSopt CONDITIONS pulsed; Tj = 25 °C MIN. 22 − 1 1 − − − TYP. 25 2.2 1.5 1.4 25 1 2 MAX. 30 2.6 2 1.7 35 1.5 2.8 UNIT mS pF pF pF fF dB dB reverse transfer capacitance f = 1 MHz Rev. 04 - 13 November 2007 4 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR 40 Y fs (mS) 30 MLD268 MRA769 handbook, halfpage gain 0 reduction (dB) 10 20 20 30 10 40 50 0 50 0 50 100 150 o T j ( C) 0 1 2 3 VAGC (V) 4 f = 50 MHz. Fig.5 Transfer admittance as a function of the junction temperature; typical values. Fig.6 Typical gain reduction as a function of the AGC voltage; see Fig.21. handbook, halfpage 120 MRA771 MLD270 20 ID (mA) 15 2V V G2 S = 4 V 3V 2.5 V Vunw (dB µV) 110 100 10 1.5 V 90 5 1V 80 0 10 20 30 40 50 gain reduction (dB) 0 0 0.4 0.8 1.2 1.6 2.0 V G1 S (V) VDS = 5 V; VGG = 5 V; fw = 50 MHz. funw = 60 MHz; Tamb = 25 °C; RG1 = 120 kΩ. Fig.7 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.21. VDS = 5 V. Tj = 25 °C. Fig.8 Transfer characteristics; typical values. Rev. 04 - 13 November 2007 5 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR MLD269 MLD271 handbook, halfpage 20 ID (mA) 16 V G1 S = 1.4 V handbook, halfpage 150 I G1 1.3 V 1.2 V 1.1 V (µA) 100 V G2 S = 4 V 3.5 V 3V 12 2.5 V 50 8 1.0 V 0.9 V 2V 4 0 0 2 4 6 8 10 V DS (V) 0 0 0.5 1.0 1.5 2.0 2.5 V G1 S (V) VG2-S = 4 V. Tj = 25 °C. VDS = 5 V. Tj = 25 °C. Fig.9 Output characteristics; typical values. Fig.10 Gate 1 current as a function of gate 1 voltage; typical values. MLD272 MLD273 handbook, halfpage 40 handbook, halfpage 16 y fs (mS) 30 V G2 S = 4 V 3.5 V 3V ID (mA) 12 20 2.5 V 8 10 4 2V 0 0 4 8 12 16 20 I D (mA) 0 0 10 20 30 40 50 I G1 (µA) VDS = 5 V. VDS = 5 V. Tj = 25 °C. VG2-S = 4 V. Tj = 25 °C. Fig.11 Forward transfer admittance as a function of drain current; typical values. Fig.12 Drain current as a function of gate 1 current; typical values. Rev. 04 - 13 November 2007 6 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR MLD275 MLD274 handbook, halfpage 12 handbook, halfpage 20 ID (mA) ID (mA) 15 8 R G1 = 47 kΩ 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 10 180 kΩ 220 kΩ 5 4 0 0 1 2 3 4 VGG (V) VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.21. 5 0 0 2 4 6 V GG = V DS (V) 8 VG2-S = 4 V; Tj = 25 °C. RG1 connected to VGG; see Fig.21. Fig.13 Drain current as a function of gate 1 supply voltage (= VGG); typical values. Fig.14 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. MLD276 handbook, halfpage 12 ID (mA) 8 V GG = 5 V 4.5 V 4V 3.5 V 3V handbook, halfpage 40 MLB945 I G1 (µA) 30 V GG = 5 V 4.5 V 4V 20 3.5 V 3V 4 10 0 0 2 4 V G2 S (V) 6 0 0 2 4 V G2 S (V) 6 VDS = 5 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.21. VDS = 5 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.21. Fig.15 Drain current as a function of gate 2 voltage; typical values. Fig.16 Gate 1 current as a function of gate 2 voltage; typical values. Rev. 04 - 13 November 2007 7 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR 10 2 handbook, halfpage y is (mS) 10 MLD277 10 3 y rs (µS) 10 2 b is MLD278 10 3 ϕ rs (deg) ϕ rs y rs 10 2 1 10 10 g is 10 1 10 102 f (MHz) 10 3 1 10 1 102 f (MHz) 10 3 VDS = 5 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.17 Input admittance as a function of frequency; typical values. Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. 10 2 MLD279 10 2 handbook, halfpage 10 MGL614 y fs (mS) y fs ϕ fs (deg) yos (mS) bos 1 10 ϕ fs 10 10−1 gos 1 10 1 102 f (MHz) 10 3 10−2 10 102 f (MHz) 103 VDS = 5 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. Fig.20 Output admittance as a function of frequency; typical values. Rev. 04 - 13 November 2007 8 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR VAGC R1 10 k Ω C1 4.7 nF C3 12 pF C2 R GEN 50 Ω VI R2 50 Ω 4.7 nF DUT R G1 L1 ≈ 450 nH C4 4.7 nF RL 50 Ω VGG V DS MLD171 Fig.21 Cross-modulation test set-up. Rev. 04 - 13 November 2007 9 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs Table 1 f (MHz) 40 100 200 300 400 500 600 700 800 900 1 000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 Table 2 BF904A; BF904AR; BF904AWR Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C S11 MAGNITUDE (ratio) 0.989 0.987 0.976 0.972 0.947 0.925 0.905 0.883 0.861 0.841 0.822 0.787 0.752 0.723 0.685 0.665 0.659 0.670 0.700 0.729 0.726 ANGLE (deg) −3.2 −7.9 −15.7 −23.3 −30.6 −37.6 −44.4 −50.9 −57.0 −63.0 −68.4 −78.9 −88.1 −97.3 −106.3 −114.0 −119.8 −124.2 −129.3 −138.7 −150.1 S21 MAGNITUDE (ratio) 2.52 2.52 2.47 2.43 2.36 2.26 2.19 2.10 2.01 1.93 1.85 1.71 1.59 1.47 1.36 1.31 1.30 1.26 1.10 0.82 0.52 ANGLE (deg) 175.9 169.4 159.2 150.5 139.6 130.3 121.1 112.3 103.6 95.5 87.8 72.3 57.3 40.1 25.0 7.7 −14.0 −42.2 −78.2 −120.8 −162.8 S12 MAGNITUDE (ratio) 0.001 0.001 0.003 0.004 0.005 0.005 0.005 0.006 0.006 0.006 0.006 0.007 0.011 0.019 0.021 0.026 0.035 0.050 0.076 0.106 0.128 ANGLE (deg) 87.9 86.1 81.4 80.5 76.9 75.6 75.5 78.0 85.3 90.7 102.6 127.1 143.7 150.0 149.4 151.5 158.2 163.4 162.2 150.5 137.4 S22 MAGNITUDE (ratio) 0.989 0.988 0.984 0.985 0.975 0.968 0.961 0.954 0.946 0.934 0.931 0.923 0.926 0.935 0.931 0.930 0.944 0.941 0.849 0.642 0.480 ANGLE (deg) −1.7 −4.3 −8.6 −12.7 −16.9 −20.8 −24.7 −28.4 −32.0 −35.6 −39.3 −46.7 −54.2 −62.2 −69.3 −77.7 −89.1 −103.5 −119.7 −130.9 −130.6 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 10 mA; Tamb = 25 °C f (MHz) 800 Fmin (dB) 2.0 Γopt (ratio) 0.686 (deg) 49.6 Rn (Ω) 50.4 Rev. 04 - 13 November 2007 10 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs PACKAGE OUTLINES Plastic surface mounted package; 4 leads BF904A; BF904AR; BF904AWR SOT143B D B E A X y vMA HE e bp wM B 4 3 Q A A1 c 1 b1 e1 2 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT143B REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-02-28 Rev. 04 - 13 November 2007 11 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR Plastic surface mounted package; reverse pinning; 4 leads SOT143R D B E A X y vMA HE e bp wM B 3 4 Q A A1 c 2 b1 e1 1 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT143R REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-03-10 Rev. 04 - 13 November 2007 12 of 15 NXP Semiconductors Product specification N-channel dual gate MOS-FETs BF904A; BF904AR; BF904AWR Plastic surface mounted package; reverse pinning; 4 leads SOT343R D B E A X y HE e vMA 3 4 Q A A1 c 2 wM B bp e1 b1 1 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 b1 0.7 0.5 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 1.15 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT343R REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-21 Rev. 04 - 13 November 2007 13 of 15 NXP Semiconductors BF904A; BF904AR; BF904AWR N-channel dual gate MOS-FETs Legal information Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com Rev. 04 - 13 November 2007 14 of 15 NXP Semiconductors BF904A; BF904AR; BF904AWR N-channel dual gate MOS-FETs Revision history Revision history Document ID BF904A_AR_AWR_N_4 Modifications: BF904A_AR_AWR_3 (9397 750 05271) BF904A_AR_AWR_N_2 (9397 750 05234) BF904A_AR_AWR_N_1 (9397 750 04748) Release date 20071113 Data sheet status Product data sheet Product specification Preliminary specification Preliminary specification Change notice Supersedes BF904A_AR_AWR_3 BF904A_AR_AWR_N_2 BF904A_AR_AWR_N_1 - • Fig. 1 and 2 on page 2; Figure note changed 19990514 19990201 19981130 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2007 Document identifier: BF904A_AR_AWR_N_4