BLD6G21L-50

BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor Rev. 01 — 28 October 2009 Objective data sheet 1. Product profile 1.1 General description The BLD6G21L-50 and BLD6G21LS-50 incorporate a fully integrated Doherty solution using NXP’s state of the art GEN6 LDMOS technology. This device is perfectly suited for TD-SCDMA base station applications at frequencies from 2010 MHz to 2025 MHz. The main and peak device, input splitter and output combiner are integrated in a single package. This package consists of one gate and drain lead and two extra leads of which one is used for biasing the peak amplifier and the other is not connected. It only requires the proper input/output match and bias setting as with a normal class-AB transistor. Table 1. Typical performance RF performance at Th = 25 °C. Mode of operation TD-SCDMA [1] [2] [1][2] f (MHz) 2010 to 2025 VDS (V) 28 PL(AV) (W) 8 Gp (dB) 13.5 ηD (%) 42 ACPR (dBc) −23 PL(3dB) (W) 50 Test signal: 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. IDq = 170 mA (main); VGS(amp)peak = 0 V. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features I Typical TD-SCDMA performance at frequencies from 2010 MHz to 2025 MHz: N Average output power = 8 W N Power gain = 13.5 dB N Efficiency = 42 % I Fully optimized integrated Doherty concept: N integrated asymmetrical power splitter at input N integrated power combiner N peak biasing down to 0 V N low junction temperature N high efficiency I Integrated ESD protection NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor I I I I I Good pair match (main and peak on the same chip) Independent control of main and peak bias Internally matched for ease of use Excellent ruggedness Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances (RoHS) 1.3 Applications I High efficiency RF power amplifiers with digital pre-distortion for TD-SCDMA multi carrier applications in the 2010 MHz to 2025 MHz range. 2. Pinning information Table 2. Pin 1 2 3 4 5 Pinning Description drain gate + bias main source n.c. bias peak 4 2 5 001aak920 Simplified outline Graphic symbol BLD6G21L-50 (SOT1130A) 1 [1] 1 2 3 3 5 BLD6G21LS-50 (SOT1130B) 1 2 3 4 5 drain gate + bias main source n.c. bias peak 001aak920 1 [1] 1 2 3 3 5 2 4 5 [1] Connected to flange. 3. Ordering information Table 3. Ordering information Package Name BLD6G21L-50 BLD6G21LS-50 Description flanged ceramic package; 2 mounting holes; 4 leads earless flanged ceramic package; 4 leads Version SOT1130A SOT1130B Type number BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 2 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 4. Block diagram main amplifier RF-input/bias main 2 90 Ω 90 Ω 1 bias peak 5 peak amplifier 001aak932 RF-output/VDS Fig 1. Block diagram of BLD6G21L-50 and BLD6G21LS-50 5. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Valid for both main and peak device. Symbol VDS VGS(amp)main VGS(amp)peak ID Tstg Tj Parameter drain-source voltage main amplifier gate-source voltage peak amplifier gate-source voltage drain current storage temperature junction temperature Conditions Min −0.5 −0.5 −65 Max 65 +13 +13 10.2 +150 200 Unit V V V A °C °C 6. Thermal characteristics Table 5. Symbol Thermal characteristics Parameter Conditions Tcase = 80 °C; PL = 8 W [1] Typ 2.4 Unit K/W Rth(j-case) thermal resistance from junction to case [1] When operated with a 6-carrier TD-SCDMA modulated signal with PAR = 10.8 dB at 0.01 % probability on CCDF. BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 3 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 7. Characteristics Table 6. Characteristics Valid for both main and peak device. Symbol V(BR)DSS VGS(th) VGSq IDSS IDSX IGSS gfs RDS(on) Parameter drain-source breakdown voltage gate-source threshold voltage gate-source quiescent voltage drain leakage current drain cut-off current gate leakage current forward transconductance drain-source on-state resistance Conditions VGS = 0 V; ID = 0.62 mA VDS = 10 V; ID = 31 mA VDS = 28 V; ID = 170 mA VGS = 0 V; VDS = 28 V VGS = VGS(th) + 3.75 V; VDS = 10 V VGS = 11 V; VDS = 0 V VDS = 10 V; ID = 1.55 A VGS = VGS(th) + 3.75 V; ID = 1.085 A Min 65 1.4 1.55 4.6 1.4 Typ 1.8 2.05 5.1 2.2 0.52 Max 2.4 2.55 1.4 140 0.736 Unit V V V µA A nA S Ω 8. Application information Table 7. Application information Mode of operation: 6-carrier TD-SCDMA; PAR 10.8 dB at 0.01 % probability on CCDF; f = 2017.5 MHz; RF performance at VDS = 28 V; IDq = 170 mA; VGS(amp)peak = 0 V; Tcase = 25 °C; unless otherwise specified; in a production circuit. Symbol PL(AV) Gp ηD PARO RLin ACPR Parameter average output power power gain drain efficiency output peak-to-average ratio input return loss adjacent channel power ratio PL(AV) = 8 W PL(AV) = 8 W PL(AV) = 8 W PL(AV) = 8 W PL(AV) = 8 W Conditions Min Typ 8 13.5 42 9.4 20 −23 Max Unit W dB % dB dB dBc 8.1 Ruggedness in Doherty operation The BLD6G21L-50 and BLD6G21LS-50 are capable of withstanding a load mismatch corresponding to VSWR = 10 : 1 through all phases under the following conditions: VDS = 28 V; IDq = 170 mA; PL = 8 W (TD-SCDMA); f = 2017.5 MHz. 8.2 Impedance information Table 8. Typical impedance Measured Load Pull data; typical values unless otherwise specified. f MHz 1995 2010 2017.5 2025 2040 ZS Ω 3.5 − 12.3j 3.6 − 12.7j 3.6 − 12.7j 3.7 − 12.7j 4.0 − 12.9j ZL Ω 6.7 − 6.1j 6.7 − 6.1j 6.7 − 5.7j 6.4 − 5.2j 5.7 − 4.8j BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 4 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor drain ZL gate ZS 001aaf059 Fig 2. Definition of transistor impedance 8.3 Performance curves Performance curves are measured in a BLD6G21L-50 application circuit. 8.3.1 CW pulsed 001aak934 001aak935 16 Gp (dB) 14 (6) (5) 60 ηD (%) (1) 40 (2) (3) (4) (4) (5) (3) 12 (2) (1) 20 (6) 10 30 35 40 45 PL (dBm) 50 0 30 35 40 45 PL (dBm) 50 VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; f = 2017.5 MHz; δ = 10 %; tp = 100 µs on 1 ms period. (1) VGS(amp)peak = 0 V (2) VGS(amp)peak = 0.2 V (3) VGS(amp)peak = 0.4 V (4) VGS(amp)peak = 0.5 V (5) VGS(amp)peak = 0.6 V (6) VGS(amp)peak = 0.8 V VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; f = 2017.5 MHz; δ = 10 %; tp = 100 µs on 1 ms period. (1) VGS(amp)peak = 0 V (2) VGS(amp)peak = 0.2 V (3) VGS(amp)peak = 0.4 V (4) VGS(amp)peak = 0.5 V (5) VGS(amp)peak = 0.6 V (6) VGS(amp)peak = 0.8 V Fig 3. Power gain as a function of load power; typical values Fig 4. Drain efficiency as a function of load power; typical values BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 5 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 16 Gp (dB) 14 (3) (2) (1) 001aak936 60 ηD (%) (3) 001aak937 40 (2) (1) 12 20 10 30 36 42 PL (dBm) 48 0 30 36 42 PL (dBm) 48 VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; VGS(amp)peak = 0 V; δ = 10 %; tp = 100 µs on 1 ms period. (1) f = 2010 MHz (2) f = 2018 MHz (3) f = 2025 MHz VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; VGS(amp)peak = 0 V; δ = 10 %; tp = 100 µs on 1 ms period. (1) f = 2010 MHz (2) f = 2018 MHz (3) f = 2025 MHz Fig 5. Power gain as a function of load power; typical values Fig 6. Drain efficiency as a function of load power; typical values 50 RLin (dB) 40 001aak938 30 20 (3) 10 (2) (1) 0 30 36 42 PL (dBm) 48 VDS = 28 V; IDq = 170 mA; VGS(amp)peak = 0 V; Tcase = 25 °C; δ = 10 %; tp = 100 µs on 1 ms period. (1) f = 2010 MHz (2) f = 2018 MHz (3) f = 2025 MHz Fig 7. Input return loss as a function of load power; typical values BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 6 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 8.3.2 TD-SCDMA 001aak939 001aak940 16 Gp (dB) 14 (6) (5) (4) (3) (2) (1) 48 ηD (%) 32 (1) (2) (3) (4) (5) (6) 12 16 10 18 26 34 PL(AV) (dBm) 42 0 18 26 34 PL(AV) (dBm) 42 VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; f = 2017.5 MHz; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. (1) VGS(amp)peak = 0 V (2) VGS(amp)peak = 0.2 V (3) VGS(amp)peak = 0.4 V (4) VGS(amp)peak = 0.5 V (5) VGS(amp)peak = 0.6 V (6) VGS(amp)peak = 0.8 V VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; f = 2017.5 MHz; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. (1) VGS(amp)peak = 0 V (2) VGS(amp)peak = 0.2 V (3) VGS(amp)peak = 0.4 V (4) VGS(amp)peak = 0.5 V (5) VGS(amp)peak = 0.6 V (6) VGS(amp)peak = 0.8 V Fig 8. Power gain as a function of average load power; typical values Fig 9. Drain efficiency as a function of average load power; typical values BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 7 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 15.0 Gp (dB) 14.5 001aak941 43 ηD (%) 41 ηD 14.0 Gp 39 13.5 0 0.2 0.4 0.6 37 1 VGS(amp)peak (V) 0.8 VDS = 28 V; IDq = 170 mA; PL(AV) = 8 W; Tcase = 25 °C; f = 2017.5 MHz; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. Fig 10. Power gain and drain efficiency as function of peak amplifier gate-source voltage; typical values 16 Gp (dB) 14 (3) (1) (2) 001aak942 48 ηD (%) 32 001aak943 12 16 (1) (2) (3) 10 18 26 34 PL(AV) (dBm) 42 0 18 26 34 PL(AV) (W) 42 VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; VGS(amp)peak = 0 V; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. (1) f = 2010 MHz (2) f = 2018 MHz (3) f = 2025 MHz VDS = 28 V; IDq = 170 mA (main); Tcase = 25 °C; VGS(amp)peak = 0 V; 6-carrier TD-SCDMA; PAR = 10.8 dB at 0.01 % probability on CCDF. (1) f = 2010 MHz (2) f = 2018 MHz (3) f = 2025 MHz Fig 11. Power gain as a function of average load power; typical values Fig 12. Drain efficiency as a function of average load power; typical values BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 8 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 9. Test information VGS(amp)main VDD C2 R1 C7 C11 L1 C6 VGS(amp)peak C3 C12 C13 INPUT BLD6G21-50-V2 C1 C21 C19 C9 C20 C10 C17 C14 L2 C15 C16 C5 C8 C18 C4 R2 OUTPUT BLD6G21-50-V2 001aak944 The striplines are on a double copper-clad gold plated Rogers 4350B Printed-Circuit Board (PCB) with εr = 3.5 and thickness = 0.76 mm. See Table 9 for list of components. Fig 13. Component layout Table 9. List of components See Figure 13 for component layout. Component C1, C3, C5, C18 C2, C4, C12, C15 C6 C7, C8 C9, C10 C11, C13, C14, C16 C17 C19, C20 C21 L1, L2 R1 R2 [1] BLD6G21L-50_BLD6G21LS-50_1 Description multilayer ceramic chip capacitor multilayer ceramic chip capacitor electrolytic capacitor multilayer ceramic chip capacitor multilayer ceramic chip capacitor multilayer ceramic chip capacitor multilayer ceramic chip capacitor multilayer ceramic chip capacitor multilayer ceramic chip capacitor copper wire SMD resistor SMD resistor Value 9.1 pF 100 nF 470 µF; 63 V 10 µF 1.5 pF 8.2 pF 1.2 pF 0.7 pF 1.2 pF 3.6 Ω 33 Ω [1] [1] [1] [1] [1] [1] Dimensions diameter = 0.8 mm; length = 8 mm 1206 1206 American Technical Ceramics type 100B or capacitor of same quality. © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 9 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 10. Package outline Flanged ceramic package; 2 mounting holes; 4 leads SOT1130A D A F L D1 U1 q 1 B C c H U2 p E1 E 3 w1 A B A 4 b 2 b1 w2 C 5 Q 0 Dimensions Unit(1) mm A b 1.14 0.89 b1 5.26 5.00 c D D1 E E1 F 5 scale H L 10 mm p 3.30 2.92 Q 1.70 q 15.24 U1 U2 w1 w2 max 4.65 nom min 3.76 0.18 9.65 9.65 9.65 9.65 1.14 17.12 3.00 0.10 9.40 9.40 9.40 9.40 0.89 16.10 2.69 20.45 9.91 0.25 0.51 20.19 9.65 0.805 0.39 0.6 0.795 0.38 sot1130a_po 1.45 max 0.183 0.045 0.207 0.007 0.38 0.38 0.38 0.38 0.045 0.674 0.118 0.130 0.067 inches nom min 0.148 0.035 0.197 0.004 0.37 0.37 0.37 0.37 0.035 0.634 0.106 0.115 0.057 Note 1. Millimeter dimensions are derived from the original inch dimensions. Outline version SOT1130A References IEC JEDEC JEITA 0.01 0.02 European projection Issue date 09-07-23 09-10-12 Fig 14. Package outline SOT1130A BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 10 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor Earless flanged ceramic package; 4 leads SOT1130B D A F L 3 D1 D U1 1 c H Z Z1 α U2 E1 E 4 b 2 b1 w2 5 D Q 0 Dimensions Unit(1) mm A b 1.14 0.89 b1 5.26 5.00 c 0.18 0.10 D 9.65 9.40 D1 9.65 9.40 0.38 0.37 E 9.65 9.40 0.38 0.37 E1 9.65 9.40 5 scale F H L 10 mm Q 1.70 1.45 U1 U2 w2 0.51 Z Z1 α 64° max 4.65 nom min 3.76 1.14 17.12 3.00 0.89 16.10 2.69 9.91 9.91 9.65 9.65 0.02 3.05 5.66 max 0.183 0.045 0.207 0.007 0.38 inches nom min 0.148 0.035 0.197 0.004 0.37 0.38 0.045 0.674 0.118 0.069 0.39 0.39 0.37 0.035 0.634 0.106 0.059 0.38 0.38 2.79 5.41 62° 0.120 0.223 64° 0.110 0.213 62° sot1130b_po Note 1. millimeter dimensions are derived from the original inch dimensions. Outline version SOT1130B References IEC JEDEC JEITA European projection Issue date 09-07-23 09-10-12 Fig 15. Package outline SOT1130B BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 11 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 11. Abbreviations Table 10. Acronym CCDF CW LDMOS PAR RF SMD TD-SCDMA VSWR Abbreviations Description Complementary Cumulative Distribution Function Continuous Wave Laterally Diffused Metal-Oxide Semiconductor Peak-to-Average power Ratio Radio Frequency Surface Mounted Device Time Division-Synchronous Code Division Multiple Access Voltage Standing-Wave Ratio 12. Revision history Table 11. Revision history Release date 20091028 Data sheet status Objective data sheet Change notice Supersedes Document ID BLD6G21L-50_BLD6G21LS-50_1 BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 12 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 13. Legal information 13.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com BLD6G21L-50_BLD6G21LS-50_1 © NXP B.V. 2009. All rights reserved. Objective data sheet Rev. 01 — 28 October 2009 13 of 14 NXP Semiconductors BLD6G21L-50; BLD6G21LS-50 TD-SCDMA 2010 MHz to 2025 MHz fully integrated Doherty transistor 15. Contents 1 1.1 1.2 1.3 2 3 4 5 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application information. . . . . . . . . . . . . . . . . . . 4 Ruggedness in Doherty operation . . . . . . . . . . 4 Impedance information . . . . . . . . . . . . . . . . . . . 4 Performance curves . . . . . . . . . . . . . . . . . . . . . 5 CW pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TD-SCDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 October 2009 Document identifier: BLD6G21L-50_BLD6G21LS-50_1