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BLF369

BLF369

  • 厂商:

    NXP(恩智浦)

  • 封装:

  • 描述:

    BLF369 - Multi-use VHF power LDMOS transistor - NXP Semiconductors

  • 数据手册
  • 价格&库存
BLF369 数据手册
BLF369 Multi-use VHF power LDMOS transistor Rev. 03 — 29 January 2008 Preliminary data sheet 1. Product profile 1.1 General description A general purpose 500 W LDMOS RF power transistor for pulsed and continuous wave applications in the HF/VHF band up to 500 MHz. Table 1. Typical performance Typical RF performance at VDS = 32 V and Th = 25 °C in a common-source 225 MHz test circuit.[1] Mode of operation CW, class AB 2-tone, class AB pulsed, class AB [1] [2] [2] f (MHz) 225 f1 = 225; f2 = 225.1 225 PL (W) 500 500 PL(PEP) (W) 500 - Gp (dB) 18 19 19 ηD (%) 60 47 55 IMD3 (dBc) −28 - Th is the heatsink temperature. tp = 2 ms; δ = 10 %. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features I Typical pulsed performance at 225 MHz, a drain-source voltage VDS of 32 V and a quiescent drain current IDq = 2 × 1.0 A: N Load power PL = 500 W N Power gain Gp = 19 dB N Drain efficiency ηD = 55 % I Advanced flange material for optimum thermal behavior and reliability I Excellent ruggedness I High power gain I Designed for broadband operation (HF/VHF band) I Source on underside eliminates DC isolators, reducing common-mode inductance I Easy power control I Integrated ESD protection I Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances (RoHS), using exemption No. 7 of the annex NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 1.3 Applications I Pulsed applications up to 500 MHz I Communication transmitter applications in the HF/VHF/UHF band under specific conditions I Industrial applications up to 500 MHz under special conditions 2. Pinning information Table 2. Pin 1 2 3 4 5 Pinning Description drain1 drain2 gate1 gate2 source [1] Simplified outline 1 2 Symbol 1 5 3 5 4 3 4 2 sym117 [1] Connected to flange. 3. Ordering information Table 3. Ordering information Package Name BLF369 Description Version flanged LDMOST ceramic package; 2 mounting holes; SOT800-2 4 leads Type number 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDS VGS Tstg Tj Parameter drain-source voltage gate-source voltage storage temperature junction temperature Conditions Min −0.5 −65 Max 65 +13 +150 200 Unit V V °C °C BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 2 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 5. Thermal characteristics Table 5. Symbol Rth(j-case) Rth(j-h) Zth(j-h) Thermal characteristics Parameter thermal resistance from junction to case thermal resistance from junction to heatsink transient thermal impedance from junction to heatsink Conditions Tj = 200 °C Tj = 200 °C Tj = 200 °C tp = 100 µs; δ = 10 % tp = 1 ms; δ = 10 % tp = 2 ms; δ = 10 % tp = 3 ms; δ = 10 % tp = 1 ms; δ = 20 % [1] [2] [3] [4] Tj is the junction temperature. Rth(j-case) and Rth(j-h) are measured under RF conditions. Rth(j-h) is dependent on the applied thermal compound and clamping/mounting of the device. See Figure 1. [4] [4] [4] [4] [4] [1][2] Typ 0.26 0.35 Unit K/W K/W [1][2][3] 0.063 K/W 0.117 K/W 0.133 K/W 0.142 K/W 0.140 K/W 0.4 Zth(j-h) (K/W) 0.3 (7) 001aah494 0.2 (6) (3) (2) (1) (5) (4) 0.1 0 10−7 10−6 10−5 10−4 10−3 10−2 10−1 1 tp (s) 10 (1) δ = 1 % (2) δ = 2 % (3) δ = 5 % (4) δ = 10 % (5) δ = 20 % (6) δ = 50 % (7) δ = 100 % (DC) Fig 1. Transient thermal impedance from junction to heatsink as function of pulse duration BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 3 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 6. Characteristics Table 6. Characteristics Tj = 25 °C unless otherwise specified. Symbol V(BR)DSS VGS(th) IDSS IDSX IGSS gfs RDS(on) Ciss Coss Crss [1] [2] Parameter drain-source breakdown voltage gate-source threshold voltage drain leakage current drain cut-off current gate leakage current forward transconductance drain-source on-state resistance input capacitance output capacitance reverse transfer capacitance Conditions VGS = 0 V; ID = 6 mA VDS = 20 V; ID = 600 mA VGS = 0 V; VDS = 32 V VGS = VGS(th) + 9 V; VDS = 10 V VGS = 20 V; VDS = 0 V VGS = 20 V; ID = 13 A VGS = VGS(th) + 9 V; ID = 13 A VGS = 0 V; VDS = 32 V; f = 1 MHz VGS = 0 V; VDS = 32 V; f = 1 MHz VGS = 0 V; VDS = 32 V; f = 1 MHz [1] [1] [2] [2] [1] [1] Min 65 4 - Typ 100 15 40 400 230 15 Max 5.5 4.2 60 - Unit V V µA A nA S mΩ pF pF pF ID is the drain current. Ciss and Coss include reverse transfer capacitance (Crss). 600 Coss (pF) 400 001aae484 200 0 0 10 20 30 40 50 VDS (V) VGS = 0 V; f = 1 MHz. Fig 2. Output capacitance as a function of drain-source voltage; typical values per section BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 4 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 7. Application information Table 7. RF performance in a common-source 225 MHz test circuit Th = 25 °C unless otherwise specified. Mode of operation CW, class AB 2-tone, class AB pulsed, class AB [1] [1] f (MHz) 225 f1 = 225; f2 = 225.1 225 VDS (V) 32 32 - IDq (A) PL (W) PL(PEP) Gp (W) 500 (dB) > 17 > 18 > 18 ηD (%) > 55 > 43 > 50 IMD3 (dBc) < −24 - ∆Gp (dB) 1 - 2 × 1.0 500 2 × 1.0 500 tp = 2 ms; δ = 10 %. 7.1 CW 22 GP (dB) 20 ηD 001aae501 70 ηD (%) 50 GP 18 30 16 0 100 200 300 10 400 500 PL (W) Fig 3. CW power gain and drain efficiency as a function of output power; typical values BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 5 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 7.2 2-Tone 22 GP (dB) 20 ηD GP 001aae502 60 ηD (%) 40 0 IMD3 (dBc) −20 001aae503 18 20 −40 16 0 200 400 PL(PEP) (W) 0 600 −60 0 200 400 PL(PEP) (W) 600 VDS = 32 V; f1 = 225 MHz; f2 = 225.1 MHz; IDq = 2 × 1.0 A; Th = 25 °C. VDS = 32 V; f1 = 225 MHz; f2 = 225.1 MHz; IDq = 2 × 1.0 A; Th = 25 °C. Fig 4. 2-Tone power gain and drain efficiency as a function of peak envelope power; typical values Fig 5. 2-Tone third order intermodulation distortion as a function of peak envelope power; typical values 7.3 Pulsed 20 Gp (dB) 19 001aah498 70 ηD (%) 50 001aah499 18 17 30 16 15 0 200 400 600 PL (W) 800 10 0 200 400 600 PL (W) 800 f = 225 MHz; VDS = 32 V; IDq = 2 × 1 A; tp = 2 ms; δ = 10 %. f = 225 MHz; VDS = 32 V; IDq = 2 × 1 A; tp = 2 ms; δ = 10 %. Fig 6. Pulsed power gain as function of load power; typical values Fig 7. Pulsed drain efficiency as function of load power; typical values BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 6 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 21 Gp (dB) 19 001aah500 70 ηD (%) 50 001aah501 17 30 15 0 200 400 600 PL (W) 800 10 0 200 400 600 PL (W) 800 f = 225 MHz; VDS = 32 V; IDq = 2 × 1 A; tp = 100 µs; δ = 10 %. f = 225 MHz; VDS = 32 V; IDq = 2 × 1 A; tp = 100 µs; δ = 10 %. Fig 8. Pulsed power gain as function of load power; typical values Fig 9. Pulsed drain efficiency as function of load power; typical values 7.4 Maximum heatsink temperature The heatsink temperature is defined 1 mm below the surface of the heatsink at the center of the flange. The maximum allowable heatsink temperature is given in the following graphs at several pulsed conditions as well as for CW. BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 7 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 100 Th (°C) 80 001aah502 (1) (2) (3) 100 Th (°C) 80 001aah503 (1) (2) (3) 60 (4) 60 (4) 40 (5) 40 (5) 20 20 0 0 200 400 600 800 1000 P (W) 0 0 200 400 600 800 1000 P (W) δ = 10 %. (1) tp ≤ 2 ms (2) tp = 10 ms (3) tp = 20 ms (4) tp = 50 ms (5) tp = 100 ms δ = 20 %. (1) tp ≤ 2 ms (2) tp = 10 ms (3) tp = 20 ms (4) tp = 50 ms (5) tp = 100 ms Fig 10. Heatsink temperature as function of power dissipation at a duty cycle of 10 % Fig 11. Heatsink temperature as function of power dissipation at a duty cycle of 20 % 100 Th (°C) 80 001aah504 60 40 20 0 100 300 500 P (W) 700 Fig 12. CW heatsink temperature as function of power dissipation 7.5 Ruggedness in class-AB operation The BLF369 is capable of withstanding a load mismatch corresponding to VSWR = 10 : 1 through all phases under the following conditions: 2-tone signal; VDS = 32 V; f = 225 MHz at rated load power (PL(PEP) = 500 W). BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 8 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 7.6 Reliability 106 Years 105 (1) (2) (3) (4) (5) (6) 001aae504 104 103 102 10 (7) (8) (9) (10) (11) 1 0 6 12 18 24 Idc (A) 30 TTF (0.1 % failure fraction); best estimate values. The reliability at pulsed conditions can be calculated as follows: TTF (0.1 %) × 1 / δ. (1) Tj = 100 °C (2) Tj = 110 °C (3) Tj = 120 °C (4) Tj = 130 °C (5) Tj = 140 °C (6) Tj = 150 °C (7) Tj = 160 °C (8) Tj = 170 °C (9) Tj = 180 °C (10) Tj = 190 °C (11) Tj = 200 °C Fig 13. BLF369 electromigration (ID, total device) 8. Test information Table 8. List of components For test circuit, see Figure 14, Figure 15 and Figure 16. Component B1 B2 C1 C2, C3 C4, C7 C5, C8 C6, C9 C10, C11, C13, C14 C12, C15 BLF369_3 Description semi rigid coax semi rigid coax multilayer ceramic chip capacitor multilayer ceramic chip capacitor multilayer ceramic chip capacitor ceramic capacitor electrolytic capacitor multilayer ceramic chip capacitor ceramic capacitor Value 25 Ω; 120 mm 25 Ω; 56 mm 91 pF 56 pF 100 pF 15 nF 220 µF 220 pF 15 nF [1] [1] [1] [1] [1] Remarks EZ90-25-TP EZ90-25-TP © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 9 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor Table 8. List of components …continued For test circuit, see Figure 14, Figure 15 and Figure 16. Component C20 C21 C22, C25 C23, C26 C24, C27 C28, C31 C29, C32 C30, C33 L1, L3 L2, L4 L5, L6 R1, R2, R3, R4 R5, R6, R8, R9 R7, R10 R11, R12 T1, T2 T3, T4 [1] [2] Description multilayer ceramic chip capacitor multilayer ceramic chip capacitor multilayer ceramic chip capacitor ceramic capacitor electrolytic capacitor multilayer ceramic chip capacitor multilayer ceramic chip capacitor ceramic capacitor stripline air coil stripline resistor resistor potentiometer resistor semi rigid coax semi rigid coax Value 100 pF 20 pF 100 pF 15 nF 10 µF 100 pF 220 pF 15 nF 0.25 W; 4 Ω 0.25 W; 10 Ω 10 kΩ 0.25 W; 1 Ω 25 Ω; 68 mm 25 Ω; 60 mm [2] [2] [1] [1] [1] [1] Remarks (W × L) 12 mm × 15 mm 4 windings; D = 8 mm; d = 1 mm (W × L) 14 mm × 15 mm EZ90-25-TP EZ90-25-TP American technical ceramics type 100B or capacitor of same quality. Printed-Circuit Board (PCB): Rogers 5880; εr = 2.2 F/m; height = 0.79 mm; Cu (top/bottom metallization); thickness copper plating = 35 µm. BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 10 of 17 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Preliminary data sheet Rev. 03 — 29 January 2008 © NXP B.V. 2008. All rights reserved. BLF369_3 NXP Semiconductors + VG1(test) C24 + VD1(test) R7 C6 C5 C4 C23 C22 C30 L5 R5 R6 L2 L1 C12 R11 C29 C10 C11 R1 R2 C28 T3 T1 C2 B1 50 Ω B2 C31 T4 C21 C20 C1 T2 C3 50 Ω R12 C33 C32 L6 L3 C13 C14 R3 R4 C15 R8 R9 L4 Multi-use VHF power LDMOS transistor C25 C26 C7 C8 C9 R10 C27 + VG2(test) + VD2(test) 001aae535 BLF369 11 of 17 Fig 14. Class-AB common-source 225 MHz test circuit; VD1(test), VD2(test), VG1(test) and VG2(test) are drain and gate test voltages xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Preliminary data sheet Rev. 03 — 29 January 2008 © NXP B.V. 2008. All rights reserved. BLF369_3 NXP Semiconductors 80 mm Multi-use VHF power LDMOS transistor 95 mm 95 mm 001aae536 BLF369 12 of 17 Fig 15. Printed-Circuit Board (PCB) for class-AB 225 MHz test circuit xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Preliminary data sheet Rev. 03 — 29 January 2008 © NXP B.V. 2008. All rights reserved. BLF369_3 C24 + R7 C23 C22 + C4 C5 C6 NXP Semiconductors + VG1(test) R5 C30 T3 R11 C28 C29 C21 C20 BLF 369 C31 C32 L3 R12 C14 B2 C33 T4 L6 R8 R9 T2 R3 L4 C13 R4 C15 C3 C1 L1 L5 T1 R6 L2 + VD1(test) R1 R2 C10 C12 B1 C11 C2 + VD2(test) + VG2(test) + C26 C27 R10 Multi-use VHF power LDMOS transistor C7 C8 C9 + C25 001aae537 BLF369 C1 mounted on top of transformers T1 and T2; C20 mounted on top of transformers T3 and T4. 13 of 17 Fig 16. Component layout for class-AB 225 MHz test circuit NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 9. Package outline Flanged LDMOST ceramic package; 2 mounting holes; 4 leads SOT800-2 D A F y D1 U1 q B C c w1 M A M 1 2 B M H U2 P E1 E 5 L A 3 4 b e w2 M C M Q 0 5 scale 10 mm DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT mm inches A 6.3 5.9 b 10.55 10.45 c 0.15 0.10 D 30.5 29.9 D1 31.1 30.9 E 14.6 14.4 E1 15.3 15.1 e 12.7 0.5 F 2.26 2.00 H 22.8 21.8 L 3.7 3.3 p 3.56 3.49 Q 3.1 2.8 q 38.5 U1 44.5 44.2 U2 15.4 15.0 w1 0.25 0.01 w2 0.25 0.01 y 0.05 0.002 0.248 0.415 0.006 1.201 1.224 0.575 0.602 0.232 0.411 0.004 1.177 1.216 0.567 0.594 0.089 0.898 0.146 0.140 0.122 1.752 0.606 1.516 0.079 0.858 0.130 0.137 0.110 1.740 0.591 EUROPEAN PROJECTION OUTLINE VERSION SOT800-2 REFERENCES IEC JEDEC JEITA ISSUE DATE 05-06-02 05-06-07 Fig 17. Package outline SOT800-2 BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 14 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 10. Abbreviations Table 9. Acronym CW DC GSM HF LDMOS LDMOST PEP RF TTF UHF VHF VSWR Abbreviations Description Continuous Wave Direct Current Global System for Mobile communications High Frequency Laterally Diffused Metal Oxide Semiconductor Laterally Diffused Metal-Oxide Semiconductor Transistor Peak Envelope Power Radio Frequency Time To Failure Ultra High Frequency Very High Frequency Voltage Standing Wave Ratio 11. Revision history Table 10. BLF369_3 Modifications: BLF369_2 BLF369_1 Revision history Release date 20080129 Data sheet status Preliminary data sheet Objective data sheet Objective data sheet Change notice Supersedes BLF369_2 BLF369_1 Document ID • Information for pulsed conditions has been added. 20061208 20060413 BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 15 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 12. Legal information 12.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 12.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 13. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com BLF369_3 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 03 — 29 January 2008 16 of 17 NXP Semiconductors BLF369 Multi-use VHF power LDMOS transistor 14. Contents 1 1.1 1.2 1.3 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 8 9 10 11 12 12.1 12.2 12.3 12.4 13 14 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application information. . . . . . . . . . . . . . . . . . . 5 CW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2-Tone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pulsed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Maximum heatsink temperature . . . . . . . . . . . . 7 Ruggedness in class-AB operation. . . . . . . . . . 8 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 January 2008 Document identifier: BLF369_3
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