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Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
FEATURES
BSH205
SYMBOL
• Very low threshold voltage
• Fast switching
• Logic level compatible
• Subminiature surface mount
package
QUICK REFERENCE DATA
VDS = -12 V
s
ID = -0.75 A
g
RDS(ON) ≤ 0.5 Ω (VGS = -2.5 V)
VGS(TO) ≥ 0.4 V
d
GENERAL DESCRIPTION
P-channel, enhancement mode,
logic level, field-effect power
transistor. This device has low
threshold voltage and extremely
fast switching making it ideal for
battery powered applications and
high speed digital interfacing.
PINNING
SOT23
PIN
DESCRIPTION
1
gate
2
source
3
drain
3
Top view
The BSH205 is supplied in the
SOT23
subminiature
surface
mounting package.
1
2
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
VDS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
RGS = 20 kΩ
IDM
Ptot
Drain current (pulse peak value)
Total power dissipation
Tstg, Tj
Storage & operating temperature
Ta = 25 ˚C
Ta = 100 ˚C
Ta = 25 ˚C
Ta = 25 ˚C
Ta = 100 ˚C
MIN.
MAX.
UNIT
- 55
-12
-12
±8
-0.75
-0.47
-3
0.417
0.17
150
V
V
V
A
A
A
W
W
˚C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Rth j-a
Thermal resistance junction to
ambient
FR4 board, minimum
footprint
300
-
K/W
August 1998
1
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
BSH205
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
CONDITIONS
MIN.
VGS = 0 V; ID = -10 μA
-12
VDS = VGS; ID = -1 mA
-0.4
-0.1
0.5
-
Tj = 150˚C
RDS(ON)
gfs
IGSS
IDSS
TYP. MAX. UNIT
Drain-source on-state
resistance
VGS = -4.5 V; ID = -430 mA
VGS = -2.5 V; ID = -430 mA
VGS = -1.8 V; ID = -210 mA
VGS = -2.5 V; ID = -430 mA; Tj = 150˚C
Forward transconductance
VDS = -9.6 V; ID = -430 mA
Gate source leakage current VGS = ±8 V; VDS = 0 V
Zero gate voltage drain
VDS = -9.6 V; VGS = 0 V;
current
Tj = 150˚C
-
-
V
-0.68
0.18
0.4
0.32
0.5
0.42
0.6
0.48 0.75
1.6
±10 ±100
-50
-100
-11
-100
V
V
Ω
Ω
Ω
Ω
S
nA
nA
μA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = -0.5 A; VDD = -10 V; VGS = -4.5 V
-
3.8
0.4
1.0
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = -10 V; ID = -0.5 A;
VGS = -8 V; RG = 6 Ω
Resistive load
-
2
4.5
45
20
-
ns
ns
ns
ns
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = -9.6 V; f = 1 MHz
-
200
95
41
-
pF
pF
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
August 1998
MIN.
TYP.
MAX.
UNIT
Ta = 25 ˚C
-
-
-0.75
A
IF = -0.38 A; VGS = 0 V
-
-0.72
-3
-1.3
A
V
IF = -0.5 A; -dIF/dt = 100 A/μs;
VGS = 0 V; VR = -9.6 V
-
75
69
-
ns
nC
2
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
BSH205
Normalised Power Dissipation, PD (%)
BSH105
Peak Pulsed Drain Current, IDM (A)
120
1000
100
D = 0.5
100
0.2
80
0.1
60
0.05
10
0.02
40
P
D
D = tp/T
tp
single pulse
1
20
T
0
0
25
50
75
100
125
0.1
1E-06
150
1E-05
1E-04
Ambient Temperature, Ta (C)
1E-03
1E-02
1E-01
1E+00 1E+01
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Ta)
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
Normalised Drain Current, ID (%)
BSH205
Drain current, ID (A)
120
-1.4
100
-1.2
4.5 V
-2.5 V
-1.8 V
Tj = 25 C
VGS = -1.4 V
-1
80
-1.3 V
-0.8
60
-1.2 V
-0.6
40
-1.1 V
-0.4
-1 V
-0.9 V
20
-0.2
0
0
25
50
75
100
125
0
150
0
Ambient Temperature, Ta (C)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Ta); conditions: VGS ≤ -10 V
-0.5
-1
-1.5
Drain-Source Voltage, VDS (V)
-2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
BSH205
Drain-Source On Resistance, RDS(on) (Ohms)
100
10
RDS(on) = VDS/ ID
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
BSH205
Peak Pulsed Drain Current, IDM (A)
tp = 100 us
1 ms
1
10 ms
100 ms
0.1
d.c.
0.01
0.1
1
10
Drain-Source Voltage, VDS (V)
100
August 1998
-1.2 V
-1.1 V
Tj = 25 C
-1.3 V
-1.4 V
-2.5 V
-1.8 V
VGS = -4.5V
0
Fig.3. Safe operating area. Ta = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
-1V
-0.9 V
-0.2
-0.4
-0.6
-0.8
Drain Current, ID (A)
-1
-1.2
-1.4
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
3
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
Drain Current, ID (A)
BSH205
BSH205
Threshold Voltage, VGS(to), (V)
-3
0.7
VDS > ID X RDS(on)
-2.5
0.6
Tj = 25 C
150 C
typical
0.5
-2
0.4
-1.5
minimum
0.3
-1
0.2
-0.5
0.1
0
0
0
0
-0.5
-1
-1.5
-2
Gate-Source Voltage, VGS (V)
-2.5
50
75
100
125
150
Junction Temperature, Tj (C)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Transconductance, gfs (S)
25
-3
BSH205
BSH205
Drain Current, ID (A)
1E-01
3.5
VDS > ID X RDS(on)
3
VDS = -5 V
Tj = 25 C
1E-02
Tj = 25 C
150 C
2.5
1E-03
2
1E-04
1.5
1
1E-05
0.5
1E-06
0
0
1E-07
-0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6
-1
Drain Current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
RDS(ON) @ Tj
RDS(ON) @ 25C
0
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C
BSH205
Capacitances, Ciss, Coss, Crss (pF)
Normalised Drain-Source On Resistance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
Gate-Source Voltage, VGS (V)
1000
-2.5 V
VGS = -4.5 V
Ciss
-1.8 V
100
Coss
Crss
0
25
50
75
100
125
10
-0.1
150
Junction Temperature, Tj (C)
-100.0
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.9. Normalised drain-source on-state resistance.
RDS(ON)/RDS(ON)25 ˚C = f(Tj)
August 1998
-1.0
-10.0
Drain-Source Voltage, VDS (V)
4
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
Gate-source voltage, VGS (V)
BSH205
BSH205
-6
-5
-4
-3
-2
-1
0
150 C
0
0
1
2
3
Gate charge, (nC)
4
5
0.2
0.4
0.6
Tj = 25 C
0.8
1
1.2
1.4
Drain-Source Voltage, VSDS (V)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
August 1998
BSH205
Source-Drain Diode Current, IF (A)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
VDD = 10 V
RD = 20 Ohms
Tj = 25 C
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
5
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
BSH205
MECHANICAL DATA
Plastic surface mounted package; 3 leads
SOT23
D
E
B
A
X
HE
v M A
3
Q
A
A1
1
2
e1
bp
c
w M B
Lp
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
mm
1.1
0.9
OUTLINE
VERSION
A1
max.
bp
c
D
E
0.1
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
e
1.9
e1
HE
Lp
Q
v
w
0.95
2.5
2.1
0.45
0.15
0.55
0.45
0.2
0.1
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
SOT23
Fig.15. SOT23 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
August 1998
6
Rev 1.000
