BUK101-50GL

Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DESCRIPTION Monolithic temperature and overload protected logic level power MOSFET in a 3 pin plastic envelope, intended as a general purpose switch for automotive systems and other applications. BUK101-50GL QUICK REFERENCE DATA SYMBOL VDS ID PD Tj RDS(ON) PARAMETER Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance VIS = 5 V MAX. 50 26 75 150 60 UNIT V A W ˚C mΩ APPLICATIONS General controller for driving lamps motors solenoids heaters FEATURES Vertical power DMOS output stage Low on-state resistance Overload protection against over temperature Overload protection against short circuit load Latched overload protection reset by input 5 V logic compatible input level Control of power MOSFET and supply of overload protection circuits derived from input Low operating input current ESD protection on input pin Overvoltage clamping for turn off of inductive loads FUNCTIONAL BLOCK DIAGRAM DRAIN O/V CLAMP INPUT RIG POWER MOSFET LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - TO220AB PIN 1 2 3 tab input drain source drain DESCRIPTION PIN CONFIGURATION tab SYMBOL D TOPFET I P 1 23 S January 1993 1 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDSS VIS ID ID IDRM PD Tstg Tj Tsold PARAMETER Continuous off-state drain source voltage Continuous input voltage Continuous drain current Continuous drain current Repetitive peak on-state drain current Total power dissipation Storage temperature Continuous junction temperature1 Lead temperature CONDITIONS VIS = 0 V Tmb ≤ 25 ˚C; VIS = 5 V Tmb ≤ 100 ˚C; VIS = 5 V Tmb ≤ 25 ˚C; VIS = 5 V Tmb ≤ 25 ˚C normal operation during soldering MIN. 0 -55 - BUK101-50GL MAX. 50 6 26 16 100 75 150 150 250 UNIT V V A A A W ˚C ˚C ˚C OVERLOAD PROTECTION LIMITING VALUES With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload. SYMBOL VISP VDDP(T) VDDP(P) PDSM PARAMETER Protection supply voltage 2 CONDITIONS for valid protection MIN. 4 MAX. - UNIT V Over temperature protection Protected drain source supply voltage VIS = 5 V Short circuit load protection Protected drain source supply voltage3 VIS = 5 V Instantaneous overload dissipation Tmb = 25 ˚C 50 35 1.3 V V kW OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL IDROM EDSM EDRM PARAMETER Repetitive peak clamping current Non-repetitive clamping energy Repetitive clamping energy CONDITIONS VIS = 0 V Tmb ≤ 25 ˚C; IDM = 26 A; VDD ≤ 20 V; inductive load Tmb ≤ 95 ˚C; IDM = 8 A; VDD ≤ 20 V; f = 250 Hz MIN. MAX. 26 625 40 UNIT A mJ mJ ESD LIMITING VALUE SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model; C = 250 pF; R = 1.5 kΩ MIN. MAX. 2 UNIT kV 1 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 2 The input voltage for which the overload protection circuits are functional. 3 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum. For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS. January 1993 2 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET THERMAL CHARACTERISTICS SYMBOL PARAMETER Thermal resistance Rth j-mb Rth j-a Junction to mounting base Junction to ambient in free air CONDITIONS MIN. BUK101-50GL TYP. MAX. UNIT 1.3 60 1.67 - K/W K/W STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL V(CL)DSS V(CL)DSS IDSS IDSS IDSS RDS(ON) PARAMETER Drain-source clamping voltage Drain-source clamping voltage CONDITIONS VIS = 0 V; ID = 10 mA MIN. 50 TYP. 0.5 1 10 45 MAX. 70 10 20 100 60 UNIT V V µA µA µA mΩ VIS = 0 V; IDM = 2 A; tp ≤ 300 µs; δ ≤ 0.01 Zero input voltage drain current VDS = 12 V; VIS = 0 V Zero input voltage drain current VDS = 50 V; VIS = 0 V Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C Drain-source on-state VIS = 5 V; IDM = 13 A; tp ≤ 300 µs; resistance δ ≤ 0.01 OVERLOAD PROTECTION CHARACTERISTICS TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input. SYMBOL EDS(TO) td sc Tj(TO) PARAMETER Short circuit load protection Overload threshold energy Response time 1 CONDITIONS Tmb = 25 ˚C; L ≤ 10 µH VDD = 13 V; VIS = 5 V VDD = 13 V; VIS = 5 V MIN. 150 TYP. 0.4 0.8 - MAX. - UNIT J ms ˚C Over temperature protection Threshold junction temperature VIS = 5 V; from ID ≥ 1 A2 INPUT CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input. SYMBOL VIS(TO) IIS VISR VISR IISL V(BR)IS RIG PARAMETER Input threshold voltage Input supply current Protection reset voltage3 Protection reset voltage Input supply current Input clamp voltage Input series resistance CONDITIONS VDS = 5 V; ID = 1 mA VIS = 5 V; normal operation Tj = 150 ˚C VIS = 5 V; protection latched II = 10 mA to gate of power MOSFET MIN. 1.0 2.0 1.0 0.5 6 TYP. 1.5 0.2 2.6 1.2 7 4 MAX. 2.0 0.35 3.5 2.0 mA V kΩ UNIT V mA V 1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for PDSM, which is always the case when VDS is less than VDSP maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES. 2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID ensures this condition. 3 The input voltage below which the overload protection circuits will be reset. January 1993 3 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET TRANSFER CHARACTERISTICS Tmb = 25 ˚C SYMBOL gfs ID(SC) PARAMETER Forward transconductance Drain current1 CONDITIONS VDS = 10 V; IDM = 13 A tp ≤ 300 µs; δ ≤ 0.01 VDS = 13 V; VIS = 5 V MIN. 10 - BUK101-50GL TYP. 16 40 MAX. - UNIT S A SWITCHING CHARACTERISTICS Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figures and test circuits. SYMBOL td on tr td off tf td on tr td off tf PARAMETER Turn-on delay time Rise time Turn-off delay time Fall time Turn-on delay time Rise time Turn-off delay time Fall time CONDITIONS VDD = 13 V; VIS = 5 V resistive load RL = 2.1 Ω VDD = 13 V; VIS = 0 V resistive load RL = 2.1 Ω VDD = 10 V; VIS = 5 V inductive load IDM = 6 A VDD = 10 V; VIS = 0 V inductive load IDM = 6 A MIN. TYP. 2.5 15 10 7 2 4 15 1 MAX. UNIT µs µs µs µs µs µs µs µs REVERSE DIODE LIMITING VALUE SYMBOL IS PARAMETER Continuous forward current CONDITIONS Tmb ≤ 25 ˚C MIN. MAX. 26 UNIT A REVERSE DIODE CHARACTERISTICS Tmb = 25 ˚C SYMBOL VSDS trr PARAMETER Forward voltage Reverse recovery time CONDITIONS IS = 26 A; VIS = 0 V; tp = 300 µs not applicable2 MIN. TYP. 1.0 MAX. 1.5 UNIT V - ENVELOPE CHARACTERISTICS SYMBOL Ld Ld Ls PARAMETER Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad MIN. TYP. 3.5 4.5 7.5 MAX. UNIT nH nH nH 1 During overload before short circuit load protection operates. 2 The reverse diode of this type is not intended for applications requiring fast reverse recovery. January 1993 4 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 10 Zth / (K/W) BUK101-50GL D= 1 0.5 0.2 0.1 0.1 0.05 0.02 0 1E-05 1E-03 t/s P D tp D= tp T t 0 20 40 60 80 100 Tmb / C 120 140 0.01 1E-07 T 1E-01 1E+01 Fig.2. Normalised power dissipation. PD% = 100⋅PD/PD(25 ˚C) = f(Tmb) ID% Normalised Current Derating Fig.5. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T ID / A BUK101-50GL 120 110 100 90 80 70 60 50 40 30 20 10 0 80 70 VIS / V = 6 60 50 5 40 30 20 10 3 2 4 0 20 40 60 80 Tmb / C 100 120 140 0 0 4 8 12 16 VDS / V 20 24 28 Fig.3. Normalised continuous drain current. ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V ID & IDM / A Overload protection characteristics not shown BUK101-50GL Fig.6. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc ID / A BUK101-50GL 1000 50 40 100 RD S( ON ) =V /I DS D VIS = 6 V VIS = 5 V tp = 10 us 100 us 30 VIS = 4 V 20 10 1 ms DC 10 ms 100 ms 1 1 10 VDS / V 100 0 0 1 2 VDS / V 3 4 5 10 Fig.4. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.7. Typical on-state characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VIS; tp = 250 µs January 1993 5 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL 0.20 RDS(ON) / ohm (3V) BUK101-50GL a Normalised RDS(ON) = f(Tj) 1.5 0.15 VIS = 4 V 5V 6V 1.0 0.10 0.05 0.5 0 0 20 40 ID / A 60 80 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.8. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VIS; tp = 250 µs ID / A BUK101-50GL Fig.11. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 13 A; VIS = 5 V td sc / ms BUK101-50GL 50 100 40 NORMAL 30 10 20 PDSM 1 10 OVERLOAD RESET PROTECTION LATCHED 0 0 1 2 VIS / V 3 4 5 0.1 0.1 1 PDS / kW 10 Fig.9. Typical transfer characteristics, Tj = 25 ˚C. ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs gfs / S Fig.12. Typical overload protection characteristics. td sc = f(PDS); conditions: VIS ≥ 4 V; Tj = 25 ˚C. PDSM% 120 100 80 60 40 20 0 26 24 22 20 18 16 14 12 10 8 6 4 2 0 BUK101-50GL 0 10 20 30 ID / A 40 50 60 -60 -40 -20 0 20 40 60 Tmb / C 80 100 120 140 Fig.10. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 10 V; tp = 250 µs Fig.13. Normalised limiting overload dissipation. PDSM% =100⋅PDSM/PDSM(25 ˚C) = f(Tmb) January 1993 6 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL 1 Energy & Time BUK101-50GL 500 II / uA BUK101-50GL 400 Time / ms 300 Tj = 25 C 0.5 200 150 C Energy / J 100 Tj(TO) 0 -60 -20 20 60 100 Tmb / C 140 180 220 0 0 2 4 VIS / V 6 8 10 Fig.14. Typical overload protection characteristics. Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ ID / A BUK101-50GL Fig.17. Typical DC input characteristics. II = f(VIS); normal operation; parameter: Tj IISL / mA BUK101-50GL 30 3 PROTECTION LATCHED 20 typ. 2 RESET 10 1 NORMAL 0 50 60 VIS / V 70 0 0 2 4 VIS / V 6 8 Fig.15. Typical clamping characteristics, 25 ˚C. ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs VIS(TO) / V Fig.18. Typical DC input characteristics, Tj = 25 ˚C. IISL = f(VIS); overload protection operated ⇒ ID = 0 A IS / A BUK101-50GL 100 max. 2 typ. 50 1 min. 0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 0 0 1 VSD / V 2 Fig.16. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V Fig.19. Typical reverse diode current, Tj = 25 ˚C. IS = f(VSDS); conditions: VIS = 0 V January 1993 7 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL VDD VDD = VCL RL t p : adjust for correct ID D LD TOPFET I P TOPFET D.U.T. RI I P D D.U.T. S ID measure 0V 0R1 RI VIS S ID measure 0V 0R1 VIS Fig.20. Test circuit for resistive load switching times. Fig.23. Test circuit for inductive load switching times. 15 RESISTIVE TURN-ON BUK101-50GL 15 INDUCTIVE TURN-ON BUK101-50GL VDS / V 10 td on tr ID / A 90% 5 VIS / V 10% 0 0 10 20 time / us 30 40 50 0 0 10 20 time / us 30 40 50 10% 5 90% VIS / V VDS / V 10 tr td on ID / A Fig.21. Typical switching waveforms, resistive load. VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C. RESISTIVE TURN-OFF BUK101-50GL Fig.24. Typical switching waveforms, inductive load. VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C. INDUCTIVE TURN-OFF BUK101-50GL 15 15 VDS / V 10 td off ID / A 5 VIS / V 0 0 5 10 time / us 15 10% 20 90% tf 90% 5 10 td off VDS / V tf 90% ID / A 10% 0 5 10 time / us 15 20 90% VIS / V 0 Fig.22. Typical switching waveforms, resistive load. VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C. Fig.25. Typical switching waveforms, inductive load. VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C. January 1993 8 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET BUK101-50GL 120 110 100 90 80 70 60 50 40 30 20 10 0 EDSM% Iiso normalised to 25 C 1.5 1 0.5 0 20 40 60 80 Tmb / C 100 120 140 -60 -20 20 60 Tj / C 100 140 180 Fig.26. Normalised clamping energy rating. EDSM% = f(Tmb); conditions: ID = 26 A; VIS = 5 V V(CL)DSS VDS VDD 0 ID 0 VIS 0 D TOPFET I Fig.29. Normalised input current (normal operation). IIS/IIS25 ˚C = f(Tj); VIS = 5 V Iisl normalised to 25 C + L VDS VDD 1.5 -ID/100 D.U.T. 1 P Schottky RIS S R 01 shunt 0.5 -60 -20 20 Fig.27. Clamping energy test circuit, RIS = 50 Ω. 2 EDSM = 0.5 ⋅ LID ⋅ V(CL )DSS /(V(CL )DSS − VDD ) 60 Tj / C 100 140 180 Fig.30. Normalised input current (protection latched). IISL/IISL25 ˚C = f(Tj); VIS = 5 V 1 mA Idss 100 uA 10 uA typ. 1 uA 100 nA 0 20 40 60 80 Tj / C 100 120 140 Fig.28. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V. January 1993 9 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET MECHANICAL DATA Dimensions in mm Net Mass: 2 g BUK101-50GL 4,5 max 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 2,54 2,54 0,9 max (3x) 0,6 2,4 Fig.31. TO220AB; pin 2 connected to mounting base. Notes 1. Refer to mounting instructions for TO220 envelopes. 2. Epoxy meets UL94 V0 at 1/8". January 1993 10 Rev 2.600 Philips Semiconductors Product specification PowerMOS transistor Logic level TOPFET DEFINITIONS Data sheet status Objective specification Product specification Limiting values BUK101-50GL This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. © Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1993 11 Rev 2.600