BUK963R2-40B

BUK95/96/9E3R2-40B TrenchMOS™ logic level FET Rev. 04 — 14 November 2003 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect power transistor in a plastic package using Philips High-Performance Automotive TrenchMOS™ technology. 1.2 Features s Very low on-state resistance s 175 °C rated s Q101 compliant s Logic level compatible. 1.3 Applications s Automotive systems s Motors, lamps and solenoids s 12 V loads s General purpose power switching. 1.4 Quick reference data s EDS(AL)S ≤ 1.2 J s ID ≤ 100 A s RDSon = 2.7 mΩ (typ) s Ptot ≤ 300 W. 2. Pinning information Table 1: Pin 1 2 3 mb Pinning - SOT78, SOT404, and SOT226 simplified outlines and symbol Description gate (g) drain (d) source (s) mounting base, connected to drain (d) 2 1 MBK106 Simplified outline [1] Symbol mb mb d mb g s MBB076 3 MBK116 123 MBK112 123 SOT78 (TO-220AB) [1] SOT404 (D2-PAK) SOT226 (I2-PAK) It is not possible to make connection to pin 2 of the SOT404 package. Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 3. Ordering information Table 2: Ordering information Package Name BUK953R2-40B BUK963R2-40B BUK9E3R2-40B TO-220AB D2-PAK I2-PAK Description Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB Version SOT78 Type number Plastic single-ended surface mounted package (Philips version of D2-PAK); SOT404 3 leads (one lead cropped) Plastic single-ended package (Philips version of I2-PAK); low-profile 3 lead TO-220AB SOT226 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) Tmb = 25 °C; VGS = 5 V; Figure 2 and 3 Tmb = 100 °C; VGS = 5 V; Figure 2 IDM Ptot Tstg Tj IDR IDRM peak drain current total power dissipation storage temperature junction temperature reverse drain current (DC) reverse drain current Tmb = 25 °C Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 100 A; VDS ≤ 40 V; VGS = 5 V; RGS = 50 Ω; starting Tmb = 25 °C [1] [2] [1] [2] [2] Conditions RGS = 20 kΩ Min −55 −55 - Max 40 40 ±15 222 100 100 888 300 +175 +175 222 100 888 1.2 Unit V V V A A A A W °C °C A A A J Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 Source-drain diode Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy [1] [2] Current is limited by power dissipation chip rating. All individual parts of device must be ≤ 175 °C to achieve maximum current rating. 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 2 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 120 Pder (%) 80 03na19 250 ID (A) 200 03nh38 150 100 40 50 Capped at 100 A due to package 0 0 50 100 150 200 Tmb (°C) 0 0 50 100 150 Tmb (˚C) 200 P tot P der = ---------------------- × 100 % P ° tot ( 25 C ) VGS ≥ 5 V Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Continuous drain current as a function of mounting base temperature. 104 ID (A) 103 03nh36 Limit RDSon = VDS / ID tp = 10 µ s 100 µ s 1 ms Capped at 100 A due to package DC 10 ms 100 ms 102 10 1 10-1 1 10 VDS (V) 102 Tmb = 25 °C; IDM single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 3 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 5. Thermal characteristics Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ Max Unit 0.5 K/W thermal resistance from junction to mounting Figure 4 base thermal resistance from junction to ambient SOT78 (TO-220AB) SOT404 (D2-PAK) SOT226 (I2-PAK) vertical in still air minimum footprint; mounted on a printed-circuit board vertical in still air 60 50 60 K/W K/W K/W Symbol Parameter 5.1 Transient thermal impedance 1 Zth(j-mb) (K/W) 03nh37 δ = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 P δ= tp T single shot 10-3 10-6 tp T 10-5 10-4 10-3 10-2 10-1 tp (s) t 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 4 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 6. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 0.25 mA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 175 °C Tj = −55 °C IDSS drain-source leakage current VDS = 40 V; VGS = 0 V Tj = 25 °C Tj = 175 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±15 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 7 and 8 Tj = 25 °C Tj = 175 °C VGS = 4.5 V; ID = 25 A VGS = 10 V; ID = 25 A Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf Ld total gate charge gate-to-source charge gate-to-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time internal drain inductance from drain lead 6 mm from package to center of die from contact screw on mounting base to center of die SOT78 from upper edge of drain mounting base to center of die SOT404/SOT226 Ls internal source inductance from source lead to source bond pad VDD = 30 V; RL = 1.2 Ω; VGS = 5 V; RG = 10 Ω VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 12 VGS = 5 V; VDD = 32 V; ID = 25 A; Figure 14 94 17 37 7877 1397 608 68 268 257 192 4.5 3.5 10502 1676 833 nC nC nC pF pF pF ns ns ns ns nH nH 2.7 2.4 3.2 6 3.5 2.8 mΩ mΩ mΩ mΩ 0.02 2 1 500 100 µA µA nA 1.1 0.5 1.5 2 2.3 V V V 40 36 V V Min Typ Max Unit Static characteristics - 2.5 - nH - 7.5 - nH 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 5 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET Table 5: Characteristics…continued Tj = 25 °C unless otherwise specified. Symbol VSD trr Qr Parameter source-drain (diode forward) voltage reverse recovery time recovered charge Conditions IS = 40 A; VGS = 0 V; Figure 15 IS = 20 A; dIS/dt = −100 A/µs VGS = −10 V; VDS = 20 V Min Typ 0.85 70 127 Max 1.2 Unit V ns nC Source-drain diode 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 6 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 350 ID (A) 280 03nh56 10 5 5 RDSon (mΩ) 4 03nh55 4 3.8 Label is VGS (V) 3.6 3.4 3.2 140 3 70 2.8 2.6 0 0 2 2.4 2.2 4 6 8 10 VDS (V) 2 3 7 11 VGS (V) 15 3 210 Tj = 25 °C; tp = 300 µs Tj = 25 °C; ID = 25 A Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Drain-source on-state resistance as a function of gate-source voltage; typical values. 8 2.8 RDSon (mΩ) 6 3 3.2 03nh57 2 a 1.5 03aa27 Label is VGS (V) 3.4 3.6 3.8 4 1 4 5 10 2 0 70 140 210 280 ID (A) 350 0.5 0 -60 0 60 120 Tj (°C) 180 Tj = 25 °C R DSon a = ---------------------------R DSon ( 25 °C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature. Fig 7. Drain-source on-state resistance as a function of drain current; typical values. 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 7 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 2.5 VGS(th) (V) 2.0 max 03ng52 10-1 ID (A) 10-2 03ng53 1.5 typ -3 10 min typ max 1.0 min 10-4 0.5 10-5 0.0 -60 0 60 120 Tj (°C) 180 10-6 0 0.5 1 1.5 2 2.5 3 VGS (V) ID = 1 mA; VDS = VGS Tj = 25 °C; VDS = VGS Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 200 gfs (S) 150 03nh53 12000 C (pF) 8000 Ciss 03nh58 100 Coss 4000 50 Crss 0 0 20 40 ID (A) 60 0 10-1 1 10 VDS (V) 102 Tj = 25 °C; VDS = 25 V VGS = 0 V; f = 1 MHz Fig 11. Forward transconductance as a function of drain current; typical values. Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 8 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 100 ID (A) 75 03nh54 5 VGS (V) 4 VDD = 14 V 3 03nh52 VDD = 32 V 50 2 25 Tj = 175 °C Tj = 25 °C 0 0 1 2 VGS (V) 3 0 0 25 50 75 QG (nC) 100 1 VDS = 25 V Tj = 25 °C; ID = 25 A Fig 13. Transfer characteristics: drain current as a function of gate-source voltage; typical values. Fig 14. Gate-source voltage as a function of gate charge; typical values. 100 IS (A) 75 03nh51 50 Tj = 175 °C Tj = 25 °C 25 0 0.0 0.2 0.4 0.6 0.8 1.0 VSD (V) VGS = 0 V Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 9 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 7. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 E p A A1 q D1 mounting base D L1(1) L2 Q L b1 1 2 3 b c e e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.39 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.4 5.9 E 10.3 9.7 e 2.54 L 15.0 13.5 L1(1) 3.30 2.79 L2 max. 3.0 p 3.8 3.6 q 3.0 2.7 Q 2.6 2.2 Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC 3-lead TO-220AB EIAJ SC-46 EUROPEAN PROJECTION ISSUE DATE 00-09-07 01-02-16 Fig 16. SOT78 (TO-220AB). 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 10 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A E A1 mounting base D1 D HD 2 Lp 1 3 b c Q e e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20 OUTLINE VERSION SOT404 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-06-25 01-02-12 Fig 17. SOT404 (D2-PAK). 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 11 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET Plastic single-ended package (Philips version of I 2-PAK); low-profile 3 lead TO-220AB SOT226 A D1 E A1 mounting base D L2 b1 L1 Q L 1 2 3 b c e e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT226 REFERENCES IEC JEDEC low-profile 3-lead TO-220AB JEITA EUROPEAN PROJECTION ISSUE DATE 99-09-13 03-10-14 A 4.5 4.1 A1 1.40 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 9.65 8.65 D1 1.5 1.1 E 10.3 9.7 e 2.54 L 15.0 13.5 L1 3.30 2.79 L2 max 3.0 (1) Q 2.6 2.2 Fig 18. SOT226 (I2-PAK). 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 12 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 8. Soldering handbook, full pagewidth 10.85 10.60 10.50 1.50 7.50 7.40 1.70 2.25 2.15 8.15 8.35 8.275 1.50 4.60 0.30 4.85 5.40 8.075 7.95 3.00 0.20 solder lands solder resist occupied area solder paste 5.08 1.20 1.30 1.55 MSD057 Dimensions in mm. Fig 19. Reflow soldering footprint for SOT404. 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 13 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 9. Revision history Table 6: Rev Date 04 20031114 Revision history CPCN Description Product data (9397 750 12049) Modifications: • 03 20030116 - Addition of BUK9E3R2-40B type to data sheet. Product data (9397 750 10844) Modifications: • 02 01 20021014 20020409 - Maximum drain current (DC) changed from 75 A to 100 A in Section 4, Limiting values. Product data (9397 750 10275) Product data (9397 750 09491) 9397 750 12049 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 14 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET 10. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 11. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 13. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 12. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 9397 750 12049 Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 04 — 14 November 2003 15 of 16 Philips Semiconductors BUK95/96/9E3R2-40B TrenchMOS™ logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 5.1 6 7 8 9 10 11 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 © Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 November 2003 Document order number: 9397 750 12049