BUK9E2R4-40C

BUK9E2R4-40C N-channel TrenchMOS logic level FET Rev. 01 — 11 April 2008 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for logic level gate drive sources Q101 compliant Suitable for thermally demanding environments due to 175 °C rating 1.3 Applications 12 V loads General purpose power switching Automotive systems Motors, lamps and solenoids 1.4 Quick reference data Table 1. Symbol VDS ID Ptot EDS(AL)S Quick reference Parameter drain-source voltage drain current total power dissipation non-repetitive drain-source avalanche energy gate-drain charge Conditions Tj ≥ 25 °C; Tj ≤ 175 °C VGS = 5 V; Tj = 25 °C; see Figure 1 and 4 Tmb = 25 °C; see Figure 2 ID = 100 A; Vsup ≤ 40 V; RGS = 50 Ω; VGS = 5 V; Tj(init) = 25 °C; unclamped VGS = 5 V; ID = 25 A; VDS = 32 V; see Figure 14 VGS = 5 V; ID = 25 A; Tj = 25 °C; see Figure 12, 11 and 13 [1][2] Min - Typ - Max 40 100 333 1.2 Unit V A W J Avalanche ruggedness Dynamic characteristics QGD 73 nC Static characteristics RDSon drain-source on-state resistance 2.1 2.4 mΩ [1] [2] Continuous current is limited by package. Refer to document 9397 750 12572 for further information. NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pin 1 2 3 mb Pinning Symbol G D S D Description gate drain source mounting base; connected to drain G mbb076 Simplified outline mb Graphic symbol D S 123 SOT226 (I2-PAK) 3. Ordering information Table 3. Ordering information Package Name BUK9E2R4-40C I2PAK Description plastic single-ended package (I2PAK); low-profile 3-lead TO-220AB Version SOT226 Type number 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID drain-source voltage drain-gate voltage gate-source voltage drain current Tmb = 25 °C; VGS = 5 V; see Figure 1 VGS = 5 V; Tj = 100 °C; see Figure 1 VGS = 5 V; Tj = 25 °C; see Figure 1 and 4 IDM Ptot Tstg Tj peak drain current total power dissipation storage temperature junction temperature ID = 100 A; Vsup ≤ 40 V; RGS = 50 Ω; VGS = 5 V; Tj(init) = 25 °C; unclamped see Figure 3 [4][5] [6] [1] [2][3] [2][3] Conditions Tj ≥ 25 °C; Tj ≤ 175 °C RGS = 20 kΩ Min -15 -55 -55 - Max 40 40 15 270 100 100 1080 333 175 175 1.2 Unit V V V A A A A W °C °C J Tmb = 25 °C; tp ≤ 10 μs; pulsed; see Figure 4 Tmb = 25 °C; see Figure 2 Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy EDS(AL)R repetitive drain-source avalanche energy Source-drain diode IS ISM BUK9E2R4-40C_1 - - J source current peak source current Tmb = 25 °C tp ≤ 10 μs; pulsed; Tmb = 25 °C [2][3] - 100 1080 A A © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 2 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET [1] [2] [3] [4] [5] [6] Current is limited by chip power dissipation rating. Continuous current is limited by package. Refer to document 9397 750 12572 for further information. Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Repetitive avalanche rating limited by an average junction temperature of 170 °C. Refer to application note AN10273 for further information. 300 ID (A) 200 003aac267 120 Pder (%) 80 03na19 100 40 (1) 0 0 50 100 150 Tmb (°C) 200 0 0 50 100 150 Tmb (°C) 200 VGS 5V P der = P tot P tot (25°C ) × 100 % (1) Capped at 100 A due to package. Fig 1. Continuous drain current as a function of mounting base temperature 103 IAL (A) 102 Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aac266 (1) (2) 10 (3) 1 10-1 10-3 10-2 10-1 1 t (ms) 10 AL (1) Single pulse; T j = 25 °C . (2) Single pulse; T j = 150 °C . (3) Repetitive. Fig 3. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 3 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 104 ID (A) 103 Limit RDSon = VDS / ID 003aac271 tp = 10 μs 102 (1) 100 μs 10 DC 1 1 ms 10 ms 100 ms 10-1 10-1 1 10 VDS (V) 102 Tmb = 25 °C ; IDM is single pulse (1) Capped at 100 A due to package. Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 4 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to mounting base Conditions vertical in free air Min Typ 60 Max Unit K/W Rth(j-mb) see Figure 5 - - 0.45 K/W 1 Zth(j-mb) (K/W) δ = 0.5 10−1 0.2 0.1 0.05 0.02 10−2 P 003aab020 δ= tp T single shot tp t T 10−3 10−6 10−5 10−4 10−3 10−2 10−1 tp (s) 1 Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration 6. Characteristics Table 6. Symbol V(BR)DSS Characteristics Parameter drain-source breakdown voltage Conditions ID = 250 μA; VGS = 0 V; Tj = 25 °C ID = 250 μA; VGS = 0 V; Tj = -55 °C VGS(th) gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; voltage see Figure 9 and 10 ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 9 ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 9 IDSS drain leakage current VDS = 40 V; VGS = 0 V; Tj = 175 °C VDS = 40 V; VGS = 0 V; Tj = 25 °C BUK9E2R4-40C_1 Min 40 36 1 0.5 - Typ 1.5 0.02 Max 2 2.3 500 1 Unit V V V V V μA μA Static characteristics © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 5 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET Table 6. Symbol IGSS Characteristics …continued Parameter gate leakage current Conditions VDS = 0 V; VGS = 15 V; Tj = 25 °C VDS = 0 V; VGS = -15 V; Tj = 25 °C Min Typ 2 2 1.8 2.1 Max 100 100 2.7 2.1 4.6 2.4 Unit nA nA mΩ mΩ mΩ mΩ RDSon drain-source on-state resistance VGS = 4.5 V; ID = 25 A; Tj = 25 °C VGS = 10 V; ID = 25 A; Tj = 25 °C VGS = 5 V; ID = 25 A; Tj = 175 °C; see Figure 11 VGS = 5 V; ID = 25 A; Tj = 25 °C; see Figure 12, 11 and 13 Source-drain diode VSD trr Qr QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf LD LS source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 16 VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 15 from drain lead 6 mm from package to centre of die from source lead to source bond pad 0.85 70 60 120 30 73 12487 1323 938 130 310 380 250 4.5 7.5 1.2 16700 1600 1290 V ns nC nC nC nC pF pF pF ns ns ns ns nH nH reverse recovery time IS = 25 A; dIS/dt = 100 A/μs; VGS = 0 V; VDS = 30 V recovered charge total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time internal drain inductance internal source inductance ID = 25 A; VDS = 32 V; VGS = 5 V; see Figure 14 Dynamic characteristics VDS = 30 V; RL = 1.2 Ω; VGS = 5 V; RG(ext) = 10 Ω BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 6 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 240 gfs (S) 180 003aac256 300 ID (A) 200 003aac253 120 Tj = 175 °C 100 60 25 °C 0 0 20 40 ID (A) 60 0 0 2 VGS (V) 4 T j = 25 °C ; VDS = 25 V VDS = 25 V Fig 6. Forward transconductance as a function of drain current; typical values 300 ID (A) 200 VGS (V) = 10 3.8 3.6 3.2 003aac252 Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values 2.5 VGS(th) (V) 2 max 03aa33 1.5 3 typ 1 100 2.8 min 0.5 2.6 2.4 0 0 1 2 3 4 VDS (V) 5 0 -60 0 60 120 Tj (°C) 180 T j = 25 °C ID = 1 m A; VDS = VGS Fig 8. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 9. Gate-source threshold voltage as a function of junction temperature BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 7 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 10-1 ID (A) 10-2 03aa36 2 a 1.5 03aa27 10-3 min 10-4 0.5 10-5 typ max 1 10-6 0 1 2 VGS (V) 3 0 -60 0 60 120 Tj (°C) 180 T j = 25 °C ; VDS = VGS a= R DSon R DSon (25°C ) Fig 10. Sub-threshold drain current as a function of gate-source voltage 6 RDSon (mΩ) 5 VGS (V) = 2.8 3 3.2 003aac265 Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature 10 RDSon (mΩ) 8 003aac257 4 6 3 3.6 3.8 10 4 2 2 1 0 50 100 150 200 ID (A) 250 0 0 5 10 VGS (V) 15 T j = 25 °C T j = 25 °C ; ID = 25 A Fig 12. Drain-source on-state resistance as a function of drain current; typical values Fig 13. Drain-source on-state resistance as a function of gate-source voltage; typical values BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 8 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 10 VGS (V) 8 VDS = 14 V 003aac254 24000 C (pF) 20000 003aac255 Ciss 32 V 16000 6 12000 4 8000 2 Crss Coss 4000 0 0 50 100 150 QG (nC) 200 0 10-1 1 10 VDS (V) 102 T j = 25 °C ; ID = 25 A VGS = 0 V ; f = 1 M H z Fig 14. Gate-source voltage as a function of gate charge; typical values Fig 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aac261 250 IS (A) 200 150 100 Tj = 175 °C 25 °C 50 0 0 0.5 1 1.5 VSD (V) 2 VGS = 0 V Fig 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 9 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended package (I2PAK); low-profile 3-lead TO-220AB SOT226 A D1 E A1 mounting base D L1 Q b1 L 1 2 3 b c e e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.40 1.27 b 0.85 0.60 b1 1.3 1.0 c 0.7 0.4 D max 11 D1 1.6 1.2 E 10.3 9.7 e 2.54 L 15.0 13.5 L1 3.30 2.79 Q 2.6 2.2 OUTLINE VERSION SOT226 REFERENCES IEC JEDEC low-profile 3-lead TO-220AB JEITA EUROPEAN PROJECTION ISSUE DATE 05-06-23 06-02-14 Fig 17. Package outline SOT226 (I2PAK) BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 10 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Release date 20080411 Data sheet status Product data sheet Change notice Supersedes Document ID BUK9E2R4-40C_1 BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 11 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com BUK9E2R4-40C_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 11 April 2008 12 of 13 NXP Semiconductors BUK9E2R4-40C N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 April 2008 Document identifier: BUK9E2R4-40C_1