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CBT16212

CBT16212

  • 厂商:

    NXP(恩智浦)

  • 封装:

  • 描述:

    CBT16212 - 24-bit bus exchange switch with 12-bit output enables - NXP Semiconductors

  • 数据手册
  • 价格&库存
CBT16212 数据手册
CBT16212 24-bit bus exchange switch with 12-bit output enables Rev. 02 — 3 November 2008 Product data sheet 1. General description The CBT16212 provides 24 bits of high-speed TTL-compatible bus switching or exchanging. The low ON resistance of the switch allows connections to be made with minimal propagation delay. The CBT16212 operates either as a 24-bit bus switch or as a 12-bit bus exchanger, providing data exchange between four signal ports using the port select inputs (S0, S1 and S2). The CBT16212 is characterized for operation from –40 °C to +85 °C. 2. Features I 5 Ω switch connection between two ports I TTL compatible input levels I ESD protection: N HBM JESD22-A114E Class 1C exceeds 1500 V N CDM JESD22-C101C exceeds 1000 V I Latch-up performance: N JESD78 exceeds 100 mA 3. Ordering information Table 1. Ordering information Package Temperature range Name CBT16212DGG CBT16212DL −40 °C to 85 °C −40 °C to 85 °C TSSOP56 SSOP56 Description plastic thin shrink small outline package; 56 leads; body width 6.1 mm plastic shrink small outline package; 56 leads; body width 7.5 mm Version SOT364-1 SOT371-1 Type number NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 4. Functional diagram 1B1 2 3 1A1 1A2 1B2 2B1 2A1 2A2 2B2 3B1 3A1 3A2 3B2 4B1 4A1 4A2 4B2 5B1 5A1 5A2 5B2 6B1 6A1 6A2 6B2 7B1 7A1 7A2 7B2 8B1 8A1 8A2 8B2 9B1 9A1 9A2 9B2 10B1 10A1 10A2 10B2 11B1 11A1 11A2 11B2 12B1 12A1 12A2 12B2 S0 S1 S2 001aai356 54 53 52 4 5 51 50 6 7 48 47 9 10 46 45 11 12 44 43 13 14 42 41 15 16 40 39 18 20 37 36 21 22 1A1 35 34 2 1 of 12 channels 54 1B1 23 24 33 32 25 26 31 30 1A2 3 53 1B2 27 28 1 56 55 FLOW CONTROL 29 S0 S1 S2 1 56 55 001aai357 Fig 1. Functional diagram Fig 2. Logic diagram CBT16212_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 2 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 5. Pinning information 5.1 Pinning S0 1A1 1A2 2A1 2A2 3A1 3A2 GND 4A1 1 2 3 4 5 6 7 8 9 56 S1 55 S2 54 1B1 53 1B2 52 2B1 51 2B2 50 3B1 49 GND 48 3B2 47 4B1 46 4B2 45 5B1 44 5B2 43 6B1 42 6B2 41 7B1 40 7B2 39 8B1 38 GND 37 8B2 36 9B1 35 9B2 34 10B1 33 10B2 32 11B1 31 11B2 30 12B1 29 12B2 001aai358 4A2 10 5A1 11 5A2 12 6A1 13 6A2 14 7A1 15 7A2 16 VCC 17 8A1 18 GND 19 8A2 20 9A1 21 9A2 22 10A1 23 10A2 24 11A1 25 11A2 26 12A1 27 12A2 28 CBT16212 Fig 3. Pin configuration SOT364-1 (TSSOP56) and SOT371-1 (SSOP56) 5.2 Pin description Table 2. Symbol S0, S1, S2 1A1 to 12A1 1A2 to 12A2 GND VCC 1B1 to 12B1 1B2 to 12B2 Pin description Pin 1, 56, 55 2, 4, 6, 9, 11, 13, 15, 18, 21, 23, 25, 27 3, 5, 7, 10, 12, 14, 16, 20, 22, 24, 26, 28 8, 19, 38, 49 17 54, 52, 50, 47, 45, 43, 41, 39, 36, 34, 32, 30 53, 51, 48, 46, 44, 42, 40, 37, 35, 33, 31, 29 Description port select input A1 port A2 port ground (0 V) supply voltage B1 port B2 port CBT16212_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 3 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 6. Functional description Table 3. S2 L L L L H H H H [1] Function selection[1] Input/output S1 L L H H L L H H S0 L H L H L H L H nA1 Z nB1 nB2 Z Z Z nB1 nB2 nA2 Z Z Z nB1 nB2 Z nB2 nB1 disconnect nA1 = nB1 nA1 = nB2 nA2 = nB1 nA2 = nB2 disconnect nA1 = nB1 and nA2 = nB2 nA1 = nB2 and nA2 = nB1 Function Port select input H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI IIK VO IO Tstg Ptot Parameter supply voltage input voltage input clamping current output voltage output current storage temperature total power dissipation Tamb = −40 °C to +125 °C SSOP56 package TSSOP56 package [1] [2] [3] [4] [3] [4] [1] Conditions Min −0.5 −0.5 −50 −0.5 −65 - Max +7.0 +7.0 +5.5 128 +150 850 600 Unit V V mA V mA °C mW mW VI < 0 V output at HIGH level or OFF-state output at LOW level The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. Above 55 °C the value of Ptot derates linearly with 11.3 mW/K. Above 55 °C the value of Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Operating conditions All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Symbol VCC VIH VIL Tamb CBT16212_2 Parameter supply voltage HIGH-level input voltage LOW-level input voltage ambient temperature Conditions Min 4.0 2.0 - Max 5.5 0.8 +85 Unit V V V °C 4 of 12 operating in free-air Rev. 02 — 3 November 2008 −40 © NXP B.V. 2008. All rights reserved. Product data sheet NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 9. Static characteristics Table 6. Static characteristics Tamb = −40 °C to +85 °C. Symbol VIK II ICC ∆ICC Parameter input clamping voltage input leakage current supply current additional supply current Conditions VCC = 4.5 V; II = −18 mA VCC = 0 V; VI = 5.5 V VCC = 5.5 V; VI = VCC or GND VCC = 5.5 V; IO = 0 A; VI = VCC or GND per port select input pin; VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND port select input pins; VI = 3 V or 0 V; VCC = 5.0 V; VCC = 4.0 V VI = 2.4 V; II = 15 mA VCC = 4.5 V VI = 0 V; II = 64 mA VI = 0 V; II = 30 mA VI = 2.4 V; II = 15 mA [1] [2] [3] All typical values are measured at Tamb = 25 °C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is determined by the lowest voltage of the two (A or B) terminals. [3] [3] [2] Min - Typ[1] - Max −1.2 10 ±1 3 2.5 Unit V µA µA µA mA CI Cio(off) RON input capacitance - 4.7 11.5 4 4 6 21 7 7 12 pF pF Ω Ω Ω Ω off-state input/output capacitance VO = 3 V or 0 V; VCC = 0 V ON resistance 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = −40 °C to +85 °C; VCC = 4.5 V to 5.5 V; for test circuit see Figure 6. Symbol tpd ten tdis [1] [2] [3] [4] Parameter propagation delay enable time disable time Conditions input A or B to output B or A; see Figure 4 port select input to output A or B; Figure 5 port select input to output A or B; Figure 5 [1][2] [3] [4] Min 2.4 2.4 Max 0.25 8.0 8.0 Unit ns ns ns This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance). tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CBT16212_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 5 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 11. Waveforms VI input GND VOH output VOL VM VM 001aah986 VM tPLH VM tPHL Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Input to output propagation delays VI Sn input GND 3.5 V output OFF to LOW LOW to OFF V OL output OFF to HIGH HIGH to OFF VOH VM GND 001aaj055 VM tPZL VM tPLZ VM VOL + 0.3 V tPZH tPHZ VOH − 0.3 V Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Table 8. VCC Enable and disable times Measurement points Input VM 1.5 V Output VM 1.5 V Supply voltage 4.5 V to 5.5 V CBT16212_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 6 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 6. Table 9. VCC Test circuit Test data Input VI GND to 3.0 V tr = tf ≤ 2.5 ns Load CL 50 pF RL 500 Ω VEXT tPLH, tPHL open tPZH, tPHZ open tPZL, tPLZ 7.0 V Supply voltage 4.5 V to 5.5 V CBT16212_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 7 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 12. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 D E A X c y HE vMA Z 56 29 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp wM 28 detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 7. CBT16212_2 Package outline SOT364-1 (TSSOP56) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 8 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE vM A Z 56 29 Q A2 A1 (A 3) θ Lp 1 bp 28 wM L detail X A pin 1 index e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 18.55 18.30 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 8. CBT16212_2 Package outline SOT371-1 (SSOP56) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 9 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 13. Abbreviations Table 10. Acronym CDM DUT ESD HBM TTL Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 03112008 Data sheet status Product data sheet Change notice Supersedes CBT16212_1 Document ID CBT16212_2 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 7 “Dynamic characteristics”: – Enable time: min value changed from 3.6 into 2.4. – Disable time: min value changed from 4.5 into 2.4. CBT16212_1 20010928 Product data - - CBT16212_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 10 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CBT16212_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 3 November 2008 11 of 12 NXP Semiconductors CBT16212 24-bit bus exchange switch with 12-bit output enables 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 November 2008 Document identifier: CBT16212_2
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