CBT3126

CBT3126 Quad FET bus switch Rev. 03 — 9 December 2008 Product data sheet 1. General description The CBT3126 is a quad FET bus switch with independent line switches. Each switch is disabled when the associated Output Enable (OE) input is LOW. The CBT3126 is characterized for operation from −40 °C to +85 °C. 2. Features I I I I I I I Standard ’126-type pinout Multiple package options 5 Ω switch connection between two ports TTL-compatible input levels Minimal propagation delay through the switch Latch-up protection exceeds 500 mA per JEDEC standard JESD78 class II level A ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Specified from −40 °C to +85 °C 3. Ordering information Table 1. Ordering information Temperature range −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C Package Name CBT3126D CBT3126DB CBT3126PW CBT3126DS SO14 SSOP14 TSSOP14 SSOP16[1] Description plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm Version SOT108-1 SOT337-1 SOT402-1 SOT519-1 Type number [1] Also known as QSOP16. NXP Semiconductors CBT3126 Quad FET bus switch 4. Functional diagram 2 1 5 4 9 10 12 13 001aaj024 1OE 1A 2OE 2A 3OE 3A 4OE 4A 4B 3B 2B 1B 1A 1OE 2A 2OE 3A 3OE 4A 4OE 001aaj023 3 1B 6 2B 8 3B 11 4B Pin numbers are for the 14 pin packages. Fig 1. Logic symbol Fig 2. Logic diagram 5. Pinning information 5.1 Pinning CBT3126 1OE 1A 1B 2OE 2A 2B GND 1 2 3 4 5 6 7 001aaj111 14 VCC 13 4OE 12 4A 11 4B 10 3OE 9 8 3A 3B 1OE 1 1A 2 1B 3 2OE 4 2A 5 2B 6 GND 7 001aaj025 CBT3126 CBT3126 n.c. 14 VCC 13 4OE 12 4A 11 4B 10 3OE 9 3A 8 3B 1OE 1A 1B 2OE 2A 2B GND 1 2 3 4 5 6 7 8 001aaj026 16 VCC 15 4OE 14 4A 13 4B 12 3OE 11 3A 10 3B 9 n.c. Fig 3. Pin configuration SOT108-1 (SO14) Fig 4. Pin configuration SOT337-1 (SSOP14) and SOT402-1 (TSSOP14) Fig 5. Pin configuration SOT519-1 (SSOP16) 5.2 Pin description Table 2. Symbol 1OE to 4OE 1A to 4A, 1B to 4B CBT3126_3 Pin description Pin SOT108-1 SOT337-1 and SOT402-1 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 SOT519-1 2, 5, 12, 15 3, 6, 11, 14 4, 7, 10, 13 output enable input A input/output B output/input © NXP B.V. 2008. All rights reserved. Description Product data sheet Rev. 03 — 9 December 2008 2 of 13 NXP Semiconductors CBT3126 Quad FET bus switch Table 2. Symbol GND VCC n.c. Pin description …continued Pin SOT108-1 SOT337-1 and SOT402-1 7 14 SOT519-1 8 16 1, 9 ground (0 V) positive supply voltage not connected Description 6. Functional description Table 3. Function selection H = HIGH voltage level; L = LOW voltage level. Inputs nOE L H nA to nB disconnected nA to nB connected Switch 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC VI ICC IIK Tstg Ptot supply voltage input voltage supply current input clamping current storage temperature total power dissipation Tamb = −40 °C to +125 °C SO14 package SSOP14 and SSOP16 package TSSOP14 package [1] [2] [3] [4] [2] [3] [4] [4] [1] Conditions Min −0.5 −0.5 −50 −65 - Max +7.0 +7.0 128 +150 500 500 500 Unit V V mA mA °C mW mW mW continuous current through each VCC or GND pin VI < 0 V The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The package thermal impedance is calculated from JESD51-7. For SO14 package; Ptot derates linearly with 8 mW/K above 70 °C. For SSOP14, SSOP16 and TSSOP14 packages; Ptot derates linearly with 5.5 mW/K above 70 °C. 8. Recommended operating conditions Table 5. Operating conditions All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Symbol VCC VIH VIL Tamb CBT3126_3 Parameter supply voltage HIGH-level input voltage LOW-level input voltage ambient temperature Conditions Min 4.5 2.0 - Max 5.5 0.8 +85 Unit V V V °C operating in free-air −40 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 3 of 13 NXP Semiconductors CBT3126 Quad FET bus switch 9. Static characteristics Table 6. Static characteristics Tamb = −40 °C to +85 °C. Symbol VIK Vpass II ICC ∆ICC Parameter input clamping voltage pass voltage input leakage current supply current additional supply current Conditions VCC = 4.5 V; II = −18 mA VI = VCC = 5.0 V; IO = −100 µA VCC = 5.5 V; VI = GND or 5.5 V VCC = 5.5 V; IO = 0 mA; VI = VCC or GND control pins; per input; VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND control pins; VI = 3 V or 0 V VO = 3 V or 0 V; OE = VCC VCC = 4.0 V VI = 2.4 V; II = 15 mA VCC = 4.5 V VI = 0 V; II = 64 mA VI = 0 V; II = 30 mA VI = 2.4 V; II = 15 mA [1] [2] [3] All typical values are measured at VCC = 5 V; Tamb = 25 °C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is determined by the lowest voltage of the two (A or B) terminals. [3] [2] Min - Typ[1] 3.8 - Max −1.2 ±1 3 2.5 Unit V V µA µA mA CI Cio(off) RON input capacitance off-state input/output capacitance ON resistance - 1.7 3.4 16 5 5 10 22 7 7 15 pF pF Ω Ω Ω Ω 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = −40 °C to +85 °C; VCC = 4.5 V to 5.5 V; for test circuit see Figure 8. Symbol tpd ten tdis [1] [2] Parameter propagation delay enable time disable time Conditions nA to nB or nB to nA; see Figure 6 OE to nA or nB; see Figure 7 OE to nA or nB; see Figure 7 [1][2] [2] [2] Min 1.6 1.0 Max 0.25 4.5 5.4 Unit ns ns ns This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance). tPLH and tPHL are the same as tpd; tPZL and tPZH are the same as ten; tPLZ and tPHZ are the same as tdis. CBT3126_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 4 of 13 NXP Semiconductors CBT3126 Quad FET bus switch 11. AC waveforms VI input 0V tPHL VOH output VOL VM VM 001aai367 VM VM tPLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The input (nA, nB) to output (nB, nA) propagation delay times VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND switch enabled switch disabled switch enabled 001aaj027 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. Input VM 1.5 V Enable and disable times Measurement points Output VM 1.5 V VX VOL + 0.3 V VY VOH − 0.3 V CBT3126_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 5 of 13 NXP Semiconductors CBT3126 Quad FET bus switch 12. Test information tW 90 % VM 10 % tf tr VI positive pulse 0V 10 % tW VEXT VCC VI VO RL VI negative pulse 0V VM tr tf 90 % VM VM G RT DUT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 9. VCC Test circuit for measuring switching times Test data Input VI GND to 3.0 V tr, tf ≤ 2.5 ns Load CL 50 pF RL 500 Ω VEXT tPLH, tPHL open tPLZ, tPZL 7.0 V tPHZ, tPZH open Supply voltage 4.5 V to 5.5 V CBT3126_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 6 of 13 NXP Semiconductors CBT3126 Quad FET bus switch 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index θ Lp 1 e bp 7 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. CBT3126_3 Package outline SOT108-1 (SO14) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 7 of 13 NXP Semiconductors CBT3126 Quad FET bus switch SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE vM A Z 14 8 Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT337-1 (SSOP14) CBT3126_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 8 of 13 NXP Semiconductors CBT3126 Quad FET bus switch TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 11. Package outline SOT402-1 (TSSOP14) CBT3126_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 9 of 13 NXP Semiconductors CBT3126 Quad FET bus switch SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm SOT519-1 D E A X c y HE vM A Z 16 9 A2 A1 (A 3) θ Lp L 1 e bp 8 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.73 A1 0.25 0.10 A2 1.55 1.40 A3 0.25 bp 0.31 0.20 c 0.25 0.18 D (1) 5.0 4.8 E (1) 4.0 3.8 e 0.635 HE 6.2 5.8 L 1 Lp 0.89 0.41 v 0.2 w 0.18 y 0.09 Z (1) 0.18 0.05 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT519-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-05-04 03-02-18 Fig 12. Package outline SOT519-1 (SSOP16) CBT3126_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 10 of 13 NXP Semiconductors CBT3126 Quad FET bus switch 14. Abbreviations Table 10. Acronym CDM ESD HBM MM TTL Abbreviations Description Charged Device Model ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Release date 20081209 Data sheet status Product data sheet Change notice Supersedes CBT3126_2 Document ID CBT3126_3 Modifications: • • • • • Section 5 “Pinning information” SOT108-1 pin configuration drawing added. Section 5 “Pinning information” SOT337-4 number changed to SOT337-1 Section 9 “Static characteristics” in Cio(off) conditions OE changed to OE Section 13 “Package outline” SOT109-1, SOT338-1, SOT403-1and SOT763-1 package outline drawings removed. Section 13 “Package outline” SOT108-1, SOT337-1and SOT402-1 package outline drawings added. Product data sheet Product data sheet CBT3126_1 - CBT3126_2 CBT3126_1 20081023 20011212 CBT3126_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 11 of 13 NXP Semiconductors CBT3126 Quad FET bus switch 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CBT3126_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 December 2008 12 of 13 NXP Semiconductors CBT3126 Quad FET bus switch 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 4 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 December 2008 Document identifier: CBT3126_3