CBT3253ADS

CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer Rev. 02 — 8 February 2007 Product data sheet 1. General description The CBT3253A is a dual 1-of-4 high-speed TTL-compatible FET multiplexer/demultiplexer. The low on-resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. 1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data. The CBT3253A is characterized for operation from −40 °C to +85 °C. 2. Features 5 Ω switch connection between two ports TTL-compatible input levels Minimal propagation delay through the switch ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I I I I 3. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C Type number CBT3253AD Topside mark CBT3253AD Package Name SO16 SSOP16 SSOP16[1] Description plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm Version SOT109-1 SOT338-1 SOT519-1 CBT3253ADB C3253A CBT3253ADS CT3253A CBT3253APW CT3253A [1] Also known as QSOP16. TSSOP16 plastic thin shrink small outline package; SOT403-1 16 leads; body width 4.4 mm NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 4. Functional diagram CBT3253A 1A 7 6 5 4 3 9 10 11 12 13 1B1 1B2 1B3 1B4 2B1 2B2 2B3 2B4 2A S0 14 S1 2 1OE 1 2OE 15 002aab828 Fig 1. Logic diagram of CBT3253A (positive logic) CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 2 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 5. Pinning information 5.1 Pinning 1OE S1 1B4 1B3 1B2 1B1 1A GND 1 2 3 4 16 VCC 15 2OE 14 S0 13 2B4 1OE S1 1B4 1B3 1B2 1B1 1 2 3 4 5 6 7 8 002aab825 16 VCC 15 2OE 14 S0 13 2B4 12 2B3 11 2B2 10 2B1 9 2A CBT3253AD 5 6 7 8 002aab824 12 2B3 11 2B2 10 2B1 9 2A CBT3253ADB 1A GND Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for SSOP16 1OE S1 1B4 1B3 1B2 1B1 1A GND 1 2 3 4 5 6 7 8 002aab826 16 VCC 15 2OE 14 S0 13 2B4 12 2B3 11 2B2 10 2B1 9 2A 1OE S1 1B4 1B3 1B2 1B1 1A GND 1 2 3 4 5 6 7 8 002aab827 16 VCC 15 2OE 14 S0 13 2B4 12 2B3 11 2B2 10 2B1 9 2A CBT3253ADS CBT3253APW Fig 4. Pin configuration for SSOP16 (QSOP16) Fig 5. Pin configuration for TSSOP16 5.2 Pin description Table 2. Symbol 1OE S1 1B4, 1B3, 1B2, 1B1 1A GND 2A 2B1, 2B2, 2B3, 2B4 S0 2OE VCC [1] CBT3253A_2 Pin description Pin 1 2 3, 4, 5, 6 7 8 9 10, 11, 12, 13 14 15 16 Description output enable (active LOW) select-control input B outputs[1] A input ground (0 V) A input B outputs select-control input output enable (active LOW) positive supply voltage B outputs are inputs if A inputs are outputs. © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 3 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 6. Functional description Refer to Figure 1 “Logic diagram of CBT3253A (positive logic)” 6.1 Function selection Table 3. Function selection H = HIGH state; L = LOW state; X = Don’t Care Inputs 1OE X H L L L L 2OE H X L L L L S1 X X L L H H S0 X X L H L H disconnect 1A and 2A disconnect 1A and 2A 1A to 1B1 and 2A to 2B1 1A to 1B2 and 2A to 2B2 1A to 1B3 and 2A to 2B3 1A to 1B4 and 2A to 2B4 Function 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI ICCC IIK Tstg [1] Parameter supply voltage input voltage continuous current through each VCC or GND pin input clamping current storage temperature Conditions Min −0.5 −0.5[1] - Max +7.0 +7.0 128 −50 +150 Unit V V mA mA °C VI < 0 V −65 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 8. Recommended operating conditions Table 5. Operating conditions All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Symbol VCC VIH VIL Tamb Parameter supply voltage HIGH-level input voltage LOW-level input voltage ambient temperature operating in free air Conditions Min 4.5 2 −40 Typ Max 5.5 0.8 +85 Unit V V V °C CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 4 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 9. Static characteristics Table 6. Static characteristics Tamb = −40 °C to +85 °C Symbol VIK Vpass ILI ICC ∆ICC Ci Cio(off) Cio(on) Ron Parameter input clamping voltage pass voltage input leakage current quiescent supply current additional quiescent supply current (control inputs) input capacitance (control pins) off-state input/output capacitance on-state input/output capacitance ON-state resistance[3] Conditions VCC = 4.5 V; II = −18 mA VI = VCC = 5.5 V; IO = −100 µA VCC = 5 V; VI = 5.5 V or GND VCC = 5.5 V; IO = 0 mA; VI = VCC or GND VCC = 5.5 V; one input at 3.4 V; other inputs at VCC or GND VI = 3 V or 0 V A port; VO = 3 V or 0 V; OE = VCC B port; VO = 3 V or 0 V; OE = VCC A port and B port VCC = 4.5 V; VI = 0 V; II = 64 mA VCC = 4.5 V; VI = 0 V; II = 30 mA VCC = 4.5 V; VI = 2.4 V; II = −15 mA [1] [2] [3] All typical values are at VCC = 5 V, Tamb = 25 °C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two (A or B) terminals. [2] Min 3.4 - Typ[1] 3.6 4.5 11.4 3.8 18.6 5 5 10 Max −1.2 3.9 ±1 3 2.5 7 7 15 Unit V V µA µA mA pF pF pF pF Ω Ω Ω 10. Dynamic characteristics Table 7. Dynamic characteristics VCC = +5.0 V ± 0.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol tPD ten tdis Parameter propagation delay enable time[2] Conditions from input (nA or nBn) to output (nBn or nA) from input (Sn) to output (nA or nBn) from input (Sn) to output (nA or nBn) from input (nOE) to output (nA or nBn) disable time[3] from input (Sn) to output (nA or nBn) from input (nOE) to output (nA or nBn) [1] [2] [3] [1] Min 1.2 1.3 1.4 1.1 1.0 Typ - Max 0.25 6.2 6.3 6.4 7.2 7 Unit ns ns ns ns ns ns The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Output enable time to HIGH and LOW level. Output disable time from HIGH and LOW level. CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 5 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 10.1 AC waveforms VI = GND to 3.0 V. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. tPLH and tPHL are the same as tPD. 3.0 V input 1.5 V tPLH 1.5 V 0V tPHL VOH output 1.5 V 1.5 V VOL 002aab665 Fig 6. Input to output propagation delay 3V output control (LOW-level enabling) 1.5 V tPZL output waveform 1 S1 at 7 V(1) tPZH output waveform 2 S1 open(2) 1.5 V 0V tPLZ 3.5 V 1.5 V VOL + 0.3 V tPHZ VOL − 0.3 V 002aab666 VOL VOH 0V 1.5 V (1) Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. Fig 7. 3-state output enable and disable times CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 6 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 11. Test information RL S1 from output under test CL 50 pF 500 Ω RL 500 Ω 7V open GND 002aab667 Test data are given in Table 8. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns. The outputs are measured one at a time with one transition per measurement. CL = load capacitance includes jig and probe capacitance. RL = load resistance. Fig 8. Test circuit Table 8. Test tPD tPLZ, tPZL tPHZ, tPZH Test data Load CL 50 pF 50 pF 50 pF RL 500 Ω 500 Ω 500 Ω open 7V open Switch CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 7 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 0.028 0.004 0.012 8 o 0 o ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT109-1 (SO16) CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 8 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT338-1 (SSOP16) CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 9 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm SOT519-1 D E A X c y HE vM A Z 16 9 A2 A1 (A 3) θ Lp L 1 e bp 8 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.73 A1 0.25 0.10 A2 1.55 1.40 A3 0.25 bp 0.31 0.20 c 0.25 0.18 D (1) 5.0 4.8 E (1) 4.0 3.8 e 0.635 HE 6.2 5.8 L 1 Lp 0.89 0.41 v 0.2 w 0.18 y 0.09 Z (1) 0.18 0.05 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT519-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-05-04 03-02-18 Fig 11. Package outline SOT519-1 (SSOP16) CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 10 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 12. Package outline SOT403-1 (TSSOP16) CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 11 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 12 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 10. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 13 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 11. Acronym CDM ESD FET HBM MM PRR RC TTL Abbreviations Description Charged Device Model ElectroStatic Discharge Field-Effect Transistor Human Body Model Machine Model Pulse Rate Repetition Resistor-Capacitor network Transistor-Transistor Logic CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 14 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 15. Revision history Table 12. Revision history Release date 20070208 Data sheet status Product data sheet Change notice Supersedes CBT3253A_1 Document ID CBT3253A_2 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 5 “Operating conditions”: – changed (VIH) “HIGH-state input voltage” to “HIGH-level input voltage” – changed (VIL) “LOW-state input voltage” to “LOW-level input voltage” • Table 6 “Static characteristics”: – Cio(off), A port: changed Typ. value from 23.5 pF to 11.4 pF – Cio(off), B port: changed Typ. value from 6.5 pF to 3.8 pF – added Cio(on) specification CBT3253A_1 (9397 750 12919) 20051024 Product data sheet - - CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 15 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com CBT3253A_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 February 2007 16 of 17 NXP Semiconductors CBT3253A Dual 1-of-4 FET multiplexer/demultiplexer 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 10.1 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function selection. . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Introduction to soldering . . . . . . . . . . . . . . . . . 12 Wave and reflow soldering . . . . . . . . . . . . . . . 12 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 February 2007 Document identifier: CBT3253A_2