CBTD3306GM

CBTD3306 Dual bus switch with level shifting Rev. 5 — 28 April 2011 Product data sheet 1. General description The CBTD3306 dual FET bus switch features independent line switches. Each switch is disabled when the associated output enable (nOE) input is HIGH. The CBTD3306 is characterized for operation from −40 °C to +85 °C. 2. Features and benefits Designed to be used in 5 V to 3.3 V level shifting applications with internal diode 5 Ω switch connection between two ports TTL-compatible input levels Multiple package options Latch-up protection exceeds 100 mA per JESD78B ESD protection: HBM JESD22-A114F exceeds 2000 V CDM JESD22-C101E exceeds 1000 V 3. Ordering information Table 1. Ordering information Package Name CBTD3306D CBTD3306PW CBTD3306GT CBTD3306GM SO8 TSSOP8 XSON8 XQFN8U Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 4.4 mm plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm Version SOT96-1 SOT530-1 SOT833-1 SOT902-1 Type number 4. Marking Table 2. Marking codes Marking code CBTD3306 D306 W06 W06 Type number CBTD3306D CBTD3306PW CBTD3306GT CBTD3306GM NXP Semiconductors CBTD3306 Dual bus switch with level shifting 5. Functional diagram 2 1 5 7 002aab985 1A 1OE 2A 2OE 3 1B 6 2B Fig 1. Logic diagram 6. Pinning information 6.1 Pinning CBTD3306 CBTD3306 1OE 1A 1B GND 1 2 3 4 001aak832 8 7 6 5 VCC 2OE 2B 2A 1OE 1A 1B GND 1 2 3 4 001aak833 8 7 6 5 VCC 2OE 2B 2A Fig 2. Pin configuration for SO8 (SOT96-1) Fig 3. Pin configuration for TSSOP8 (SOT530-1) CBTD3306 CBTD3306 1OE 1 8 VCC terminal 1 index area 1OE 1 VCC 8 7 2OE 1A 2 7 2OE 1A 2 6 2B 1B 3 6 2B 1B 3 4 5 2A GND GND 4 5 2A 001aal405 001aal404 Transparent top view Transparent top view Fig 4. Pin configuration SOT833-1 (XSON8) Fig 5. Pin configuration SOT902-1 (XQFN8U) CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 2 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 6.2 Pin description Table 3. Symbol 1OE, 2OE 1A, 2A 1B, 2B GND VCC Pin description Pin 1, 7 2, 5 3, 6 4 8 Description output enable input data input/output (A port) data input/output (B port) ground (0 V) positive supply voltage 7. Functional description Table 4. Input nOE L H [1] Function selection[1] Input/output nA, nB nA = nB Z H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol VCC VI ISW IIK Tstg [1] Parameter supply voltage input voltage switch current input clamping current storage temperature Conditions [2] Min −0.5 −0.5 −50 −65 Max +7.0 +7.0 128 +150 Unit V V mA mA °C VI/O = 0 V Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 9. is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. [2] 9. Recommended operating conditions Table 6. Operating conditions All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Symbol VCC VIH VIL Tamb Parameter supply voltage HIGH-level input voltage LOW-level input voltage ambient temperature operating in free air Conditions Min 4.5 2.0 −40 Typ Max 5.5 0.8 +85 Unit V V V °C CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 3 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol VIK II ICC Vpass ΔICC Parameter input clamping voltage input leakage current supply current pass voltage additional supply current Conditions VCC = 4.5 V; II = −18 mA VCC = 5.5 V; VI = GND or 5.5 V VCC = 5.5 V; ISW = 0 mA; VI = VCC or GND see Figure 6 to Figure 10 per input pin; VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND control pin; VI = 3 V or 0 V port off; VI = 3 V or 0 V; nOE = VCC VCC = 4.5 V; VI = 0 V; II = 64 mA VCC = 4.5 V; VI = 0 V; II = 30 mA VCC = 4.5 V; VI = 2.4 V; II = 15 mA [1] [2] [3] All typical values are at VCC = 5 V, Tamb = 25 °C. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Measured by the voltage drop between the nA and the nB terminals at the indicated current through the switch. ON resistance is determined by the lowest voltage of the two (nA or nB) terminals. [3] [3] [3] [2] Tamb = −40 °C to +85 °C Min Typ[1] Max −1.2 ±1 1.5 2.5 Unit V μA mA V mA CI Cio(off) RON input capacitance off-state input/output capacitance ON resistance - 3.2 6.5 3.6 3.6 17 5 5 35 pF pF Ω Ω Ω CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 4 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 10.1 Typical pass voltage graphs 3.6 Vpass (V) 3.2 (1) 001aak834 3.6 Vpass (V) (1) 001aak835 3.2 (2) (2) (3) 2.8 (4) 2.8 (3) (4) 2.4 2.4 2.0 4.4 4.8 5.2 VCC (V) 5.6 2.0 4.4 4.8 5.2 VCC (V) 5.6 (1) ISW = 100 μA (2) ISW = 6 mA (3) ISW =12 mA (4) ISW = 24 mA (1) ISW = 100 μA (2) ISW = 6 mA (3) ISW =12 mA (4) ISW = 24 mA Fig 6. Pass voltage versus supply voltage; Tamb = 85 °C (typical) Fig 7. Pass voltage versus supply voltage; Tamb = 70 °C (typical) 3.6 Vpass (V) 3.2 (2) 001aak836 3.6 Vpass (V) 3.2 (1) 001aak837 (1) (2) (3) (3) 2.8 (4) 2.8 (4) 2.4 2.4 2.0 4.4 4.8 5.2 VCC (V) 5.6 2.0 4.4 4.8 5.2 VCC (V) 5.6 (1) ISW = 100 μA (2) ISW = 6 mA (3) ISW =12 mA (4) ISW = 24 mA (1) ISW = 100 μA (2) ISW = 6 mA (3) ISW =12 mA (4) ISW = 24 mA Fig 8. Pass voltage versus supply voltage; Tamb = 25 °C (typical) Fig 9. Pass voltage versus supply voltage; Tamb = 0 °C (typical) CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 5 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 3.6 Vpass (V) 3.2 (1) 001aak838 (2) 2.8 (3) (4) 2.4 2.0 4.4 4.8 5.2 VCC (V) 5.6 (1) ISW = 100 μA (2) ISW = 6 mA (3) ISW =12 mA (4) ISW = 24 mA Fig 10. Pass voltage versus supply voltage; Tamb = −40 °C (typical) CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 6 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol tpd ten tdis Parameter propagation delay enable time disable time Conditions nA, nB to nB, nA; see Figure 11 VCC = 5.0 V ± 0.5 V nOE to nA or nB; see Figure 12 VCC = 5.0 V ± 0.5 V nOE to nA or nB; see Figure 12 VCC = 5.0 V ± 0.5 V [1] [2] The propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [2] [2] [1][2] Tamb = −40 °C to +85 °C Min 1.0 1.0 Typ Max 0.25 5.4 4.9 Unit ns ns ns 12. Waveforms VI nA, nB input GND tPHL VOH nB, nA output VOL VM 001aak305 VM tPLH Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. The data input (nA, nB) to output (nB, nA) propagation delay times CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 7 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting VI nOE input GND tPLZ tPZL VM VM 3.5 V output LOW to OFF OFF to LOW VOL tPHZ VOH output HIGH to OFF OFF to HIGH GND outputs enabled outputs disabled outputs enabled 001aak298 VM VX tPZH VY VM Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. Enable and disable times Table 9. VCC VCC = 5.0 V ± 0.5 V Measurement points Input VI GND to 3.0 V VM 1.5 V Output VM 1.5 V VX VOL + 0.3 V VY VOH − 0.3 V Supply voltage CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 8 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 13. Test information tW 90 % VM 10 % tf tr VI positive pulse 0V 10 % tW VEXT VCC VI VO RL VI negative pulse 0V VM tr tf 90 % VM VM G RT DUT CL RL 001aae331 Test data is given in Table 10. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω. The outputs are measured one at a time with one transition per measurement. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Test circuit for measuring switching times Table 10. Test data Input VI VCC = 5.0 V ± 0.5 V tr, tf GND to 3.0 V ≤ 2.5 ns Load CL 50 pF RL 500 Ω VEXT tPLH, tPHL open tPLZ, tPZL 7.0 V tPHZ, tPZH open Supply voltage CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 9 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 14. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 pin 1 index A1 (A 3) θ Lp L A 1 4 e bp wM detail X 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ 8o o 0 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 14. Package outline SOT96-1 (SO8) CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 10 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting TSSOP8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm SOT530-1 E D A X c y HE Z vMA 8 5 A2 A1 pin 1 index Lp L detail X (A3) A θ 1 e bp 4 wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.13 D(1) 3.1 2.9 E(2) 4.5 4.3 e 0.65 HE 6.5 6.3 L 0.94 Lp 0.7 0.5 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT530-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-24 03-02-18 Fig 15. Package outline SOT530-1 (TSSOP8) CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 11 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 16. Package outline SOT833-1 (XSON8) CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 12 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 17. Package outline SOT902-1 (XQFN8U) CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 13 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 15. Abbreviations Table 11. Acronym CDM ESD FET HBM PRR TTL Abbreviations Description Charged Device Model ElectroStatic Discharge Field Effect Transistor Human Body Model Pulse Rate Repetition Transistor-Transistor Logic 16. Revision history Table 12. Revision history Release date 20110428 Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet Product data Change notice Supersedes CBTD3306 v.4 CBTD3306 v.3 CBTD3306 v.2 CBTD3306 v.1 Document ID CBTD3306 v.5 Modifications: CBTD3306 v.4 CBTD3306 v.3 CBTD3306 v.2 CBTD3306 v.1 • Table 2: Marking code table corrected (errata). 20100325 20100223 20091015 20011108 CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 14 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 15 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product Specification Rev. 5 — 28 April 2011 16 of 17 NXP Semiconductors CBTD3306 Dual bus switch with level shifting 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Typical pass voltage graphs . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 April 2011 Document identifier: CBTD3306