CBTL04083BBS,518

CBTL04083A/CBTL04083B 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 Rev. 4.1 — 27 July 2020 1 Product data sheet General description CBTL04083A/B is a 4 differential channel, 2-to-1 multiplexer/demultiplexer switch for PCI Express Generation 3 (Gen3) applications. The CBTL04083A/B can switch four differential signals to one of two locations. Using a unique design technique, NXP has minimized the impedance of the switch such that the attenuation observed through the switch is negligible, and also minimized the channel-to-channel skew as well as channelto-channel crosstalk, as required by the high-speed serial interface. CBTL04083A/B allows expansion of existing high speed ports for extremely low power. The device's pin out are optimized to match different application layouts. CBTL04083A has input and output pins on the opposite of the package, and is suitable for edge connector(s) with different signal sources on the motherboard. CBTL04083B has outputs on both sides of the package, and the device can be placed between two connectors to multiplex differential signals from a controller. Please refer to Section 8 for layout examples. 2 Features and benefits • • • • • • • • • • • • • 4 differential channel, 2 : 1 multiplexer/demultiplexer High-speed signal switching for 8.0 Gbit/s PCIe Gen3 speed Low intra-pair skew: 5 ps typical Low inter-pair skew: 35 ps maximum High bandwidth: – -3 dB at 8.3 GHz for CBTL04083A – -3 dB at 8.0 GHz for CBTL04083B Low crosstalk: -29 dB at 4 GHz Low insertion loss – -0.5 dB at 100 MHz – -1.3 dB at 4 GHz Low off-state isolation: -20 dB at 4 GHz Low return loss: -14 dB at 4 GHz VDD operating range: 3.3 V ± 10 % Dual shutdown pins for channel 0/1 and 2/3 independently to minimize power consumption ESD tolerance: – 2000 V HBM – 1000 V CDM HVQFN42 package CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 3 Applications • Routing of high-speed differential signals with low signal attenuation – PCIe Gen3 – DisplayPort 1.2 – USB 3.0 – SATA 6 Gbit/s 4 Ordering information Table 1. Ordering information Type number Topside marking Package CBTL04083ABS L04083A HVQFN42 plastic thermal enhanced very thin quad flat package; no [1] leads; 42 terminals; body 3.5 × 9 × 0.85 mm SOT1144-1 CBTL04083BBS L04083B HVQFN42 plastic thermal enhanced very thin quad flat package; no [1] leads; 42 terminals; body 3.5 × 9 × 0.85 mm SOT1144-1 [1] Name Description Version Total height after printed-circuit board mounting = 1.0 mm maximum. 4.1 Ordering options Table 2. Ordering options Type number [1] CBTL04083ABS [2] CBTL04083BBS [1] [2] Orderable part number Package Packing method Minimum order Temperature quantity CBTL04083ABS,518 HVQFN42 REEL 13" Q1/T1 DP 4000 Tamb = -40 °C to +85 °C CBTL04083ABS,558 HVQFN42 REEL 13" Q1/T1 DP 4000 Tamb = -40 °C to +85 °C CBTL04083BBS,518 HVQFN42 REEL 13" Q1/T1 DP 4000 Tamb = -40 °C to +85 °C CBTL04083BBS,558 HVQFN42 REEL 13" Q1/T1 DP 4000 Tamb = -40 °C to +85 °C CBTL04083ABS is available in tape and reel formats with different tape widths — 16 mm and 24 mm: For 16 mm tape width, order CBTL04083ABS 9352 941 24518 ("518" indicates 16 mm wide carrier tape). For 24 mm tape width, order CBTL04083ABS 9352 941 24558 ("558" indicates 24 mm wide carrier tape). Not recommended for new design. CBTL04083BBS is available in tape and reel formats with different tape widths — 16 mm and 24 mm: For 16 mm tape width, order CBTL04083BBS 9352 941 25518 ("518" indicates 16 mm wide carrier tape). For 24 mm tape width, order CBTL04083BBS 9352 941 25558 ("558" indicates 24 mm wide carrier tape). Not recommended for new design. CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 2 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 5 Functional diagram A0_P B0_P A0_N B0_N A1_P B1_P A1_N B1_N C0_P XSD01 C0_N C1_P C1_N A2_P B2_P A2_N B2_N A3_P B3_P A3_N B3_N C2_P XSD23 C2_N C3_P C3_N SEL 002aaf752 Figure 1. Functional diagram of CBTL04083A/B CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 3 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 6 Pinning information 6.1 Pinning 39 VDD 40 XSD01 42 GND 41 VDD CBTL04083BBS 39 GND 40 VDD 41 XSD01 42 VDD CBTL04083ABS GND 1 38 B0_P A0_P 1 38 GND A0_P 2 37 B0_N A0_N 2 37 B0_P A0_N 3 36 B1_P C0_P 3 36 B0_N GND 4 35 B1_N C0_N 4 35 GND VDD 5 34 C0_P A1_P 5 34 VDD A1_P 6 33 C0_N A1_N 6 33 B1_P A1_N 7 32 C1_P C1_P 7 32 B1_N VDD 8 31 C1_N C1_N 8 31 VDD SEL 9 30 VDD VDD 9 30 SEL GND 10 29 B2_P A2_P 10 29 GND A2_P 11 28 B2_N A2_N 11 28 B2_P A2_N 12 27 B3_P C2_P 12 27 B2_N VDD 13 26 B3_N C2_N 13 26 VDD GND 14 25 C2_P A3_P 14 24 C2_N A3_N 15 23 C3_P C3_P 16 22 C3_N C3_N 17 23 B3_N VDD 21 002aaf744 Transparent top view 24 B3_P 22 GND XSD23 20 GND 21 VDD 20 VDD 18 XSD23 19 GND 17 VDD 19 A3_N 16 25 GND GND (exposed thermal pad) GND 18 GND (exposed thermal pad) A3_P 15 002aaf751 Transparent top view a. CBTL04083A b. CBTL04083B Figure 2. Pin configuration for HVQFN42 6.2 Pin description Table 3. Pin description Symbol Pin Type Description channel 0, port A differential signal input/output CBTL04083A CBTL04083B A0_P 2 1 I/O A0_N 3 2 I/O A1_P 6 5 I/O A1_N 7 6 I/O A2_P 11 10 I/O A2_N 12 11 I/O A3_P 15 14 I/O A3_N 16 15 I/O B0_P 38 37 I/O CBTL04083A_CBTL04083B Product data sheet channel 1, port A differential signal input/output channel 2, port A differential signal input/output channel 3, port A differential signal input/output channel 0, port B differential signal input/output All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 4 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 Symbol Pin Type Description CBTL04083A CBTL04083B B0_N 37 36 I/O B1_P 36 33 I/O B1_N 35 32 I/O B2_P 29 28 I/O B2_N 28 27 I/O B3_P 27 24 I/O B3_N 26 23 I/O C0_P 34 3 I/O C0_N 33 4 I/O C1_P 32 7 I/O C1_N 31 8 I/O C2_P 25 12 I/O C2_N 24 13 I/O C3_P 23 16 I/O C3_N 22 17 I/O SEL 9 30 CMOS singleended input operation mode select SEL = LOW: A → B SEL = HIGH: A → C XSD01 41 40 CMOS singleended input Shutdown pin; should be driven LOW or connected to GND for normal operation. When HIGH, channel 0 and channel 1 are switched off (non-conducting highimpedance state), and supply current consumption is minimized. XSD23 19 20 CMOS singleended input Shutdown pin; should be driven LOW or connected to GND for normal operation. When HIGH, channel 2 and channel 3 are switched off (non-conducting highimpedance state), and supply current consumption is minimized. VDD 5, 8, 13, 18, 20, 30, 40, 42 9, 19, 21, 26, 31, 34, 39, 41 power positive supply voltage, 3.3 V ± 10 % 1, 4, 10, 14, 17, 21, 39, center pad 18, 22, 25, ground 29, 35, 38, 42, center pad GND [1] [1] channel 1, port B differential signal input/output channel 2, port B differential signal input/output channel 3, port B differential signal input/output channel 0, port C differential signal input/output channel 1, port C differential signal input/output channel 2, port C differential signal input/output channel 3, port C differential signal input/output supply ground HVQFN32 package die supply ground is connected to both GND pins and exposed center pad. GND pins and the exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 5 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 7 Functional description Refer to Figure 1. 7.1 Function selection Table 4. Function selection X = Don’t care. XSD01 XSD23 SEL Function HIGH - X An, Bn and Cn pins are high-Z, n = 0, 1 LOW - LOW An to Bn, n = 0, 1 LOW - HIGH An to Cn, n = 0, 1 - HIGH X An, Bn and Cn pins are high-Z, n = 2, 3 - LOW LOW An to Bn, n = 2, 3 - LOW HIGH An to Cn, n = 2, 3 7.2 Shutdown function The CBTL04083A/B provides a shutdown function to minimize power consumption when the application is not active, but power to the CBTL04083A/B is provided. Pin XSD01 and XSD23 (active HIGH) puts channel 0/1 and 2/3 (respectively) in high-impedance state (non-conducting) while reducing current consumption to near-zero. Table 5. Shutdown function CBTL04083A_CBTL04083B Product data sheet XSD01 XSD23 Channel 0 Channel 1 Channel 2 Channel 3 HIGH - high-Z high-Z - - LOW - active active - - - HIGH - - high-Z high-Z - LOW - - active active All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 6 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 8 Application design-in information PCIe SLOT PCI EXPRESS CONTROLLER PCIe SLOT CBTL04083A CBTL04083B 002aaf840 Figure 3. A/B pinout difference (layout) CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 7 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 9 Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Tcase case temperature VESD [1] [2] Conditions electrostatic discharge voltage Min Max Unit -0.3 +4.6 V -40 +85 °C HBM [1] - 2000 V CDM [2] - 1000 V Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model - Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model Component level; Electrostatic Discharge Association, Rome, NY, USA. 10 Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter VDD Conditions Min Typ Max Unit supply voltage 3.0 3.3 3.6 V VI input voltage - - VDD V Tamb ambient temperature -40 - +85 °C operating in free air 11 Static characteristics Table 8. Static characteristics VDD = 3.3 V ± 10 %; Tamb = -40 °C to +85 °C; unless otherwise specified. [1] Symbol Parameter Conditions Min Typ Max Unit IDD supply current operating mode (both XSD01 and XSD23 are LOW); VDD = max. - 2.7 5 mA shutdown mode (both XSD01 and XSD23 are HIGH); VDD = max. - - 1 μA VDD = max.; VI = VDD - - ±5 IIH HIGH-level input current [2] μA [2] IIL LOW-level input current VDD = max.; VI = GND - - ±5 μA VIH HIGH-level input voltage SEL, XSD01, XSD23 pins 0.65VDD - - V VIL LOW-level input voltage SEL, XSD01, XSD23 pins -0.5 - 0.35VDD V VI input voltage differential pins - - 2.4 V SEL, XSD01, XSD23 pins - - VDD V 0 - 2 V - - 1.6 V VIC common-mode input voltage VID differential input voltage [1] [2] peak-to-peak Typical values are at VDD = 3.3 V, Tamb = 25 °C, and maximum loading. Input leakage current is ±50 μA if differential pairs are pulled to HIGH and LOW. CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 8 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 12 Dynamic characteristics Table 9. Dynamic characteristics VDD = 3.3 V ± 10 %; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Typ Max Unit f = 4 GHz - -29 - dB f = 100 MHz - -45 - dB f = 4 GHz - -20 - dB f = 100 MHz - -50 - dB f = 4 GHz - -1.3 - dB f = 100 MHz - -0.5 - dB adjacent channels are ON DDNEXT differential near-end crosstalk DDIL [1] Min channel is OFF differential insertion loss channel is ON DDRL f = 4 GHz differential return loss Ron ON-state resistance Cio(on) on-state input/output capacitance B-3dB -3 dB bandwidth tPD propagation delay -14 dB f = 100 MHz - -24 - dB VDD = 3.3 V; VI = 2 V; II = 19 mA - 6 - Ω - 1.5 - pF CBTL04083A - 8.3 - GHz CBTL04083B - 8.0 - GHz from left-side port to right-side port, or vice versa - 60 - ps supply voltage valid or XSD01/XSD23 going LOW to channel specified operating characteristics - - 10 ms Switching characteristics tstartup start-up time tPZH OFF-state to HIGH propagation delay - - 300 ns tPZL OFF-state to LOW propagation delay - - 70 ns tPHZ HIGH to OFF-state propagation delay - - 50 ns tPLZ LOW to OFF-state propagation delay - - 50 ns tsk(dif) differential skew time intra-pair - 5 - ps tsk skew time inter-pair - - 35 ps [1] Typical values are at VDD = 3.3 V; Tamb = 25 °C, and maximum loading. CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 9 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 VDD SEL 0.5VDD tPZL 0V tPLZ 0.85VOH output 1 0.25VOH tPZH output 2 0.5VDD VOH VOL tPHZ VOH 0.85VOH 0.25VOH VOL 002aag013 Output 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Output 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. The outputs are measured one at a time with one transition per measurement. Figure 4. Voltage waveforms for enable and disable times CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 10 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 13 Test information VDD VIC PULSE GENERATOR DUT RL 200 Ω VO CL 50 pF RT 2 × VIC open GND RL 200 Ω 002aag014 CL = load capacitance; includes jig and probe capacitance. RT = termination resistance; should be equal to Zo of the pulse generator. All input pulses are supplied by generators having the following characteristics: PRR ≤ 5 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns. Figure 5. Test circuitry for switching times 4-PORT, 20 GHz NETWORK ANALYZER PORT 2 PORT 3 PORT 1 PORT 4 DUT 002aae655 Figure 6. Test circuit Table 10. Test data Test CBTL04083A_CBTL04083B Product data sheet Load Switch CL RL tPLZ, tPZL (output on B side) 50 pF 200 Ω 2 × VIC tPHZ, tPZH (output on B side) 50 pF 200 Ω GND tPD - 200 Ω open All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 11 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 14 Package outline HVQFN42: plastic thermal enhanced very thin quad flat package; no leads; 42 terminals; body 3.5 x 9 x 0.85 mm D B SOT1144-1 A terminal 1 index area E A A1 c detail X e1 1/2 e e v w b L 18 21 17 C C A B C y1 C y 22 e Eh e2 38 1 terminal 1 index area 42 39 X Dh 0 2.5 Dimensions Unit(1) mm 5 mm scale A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.25 min 0.80 0.00 0.20 c D Dh E Eh e e1 e2 L v 0.2 3.6 3.5 3.4 2.15 2.05 1.95 9.1 9.0 8.9 7.70 7.55 7.40 0.5 1.5 8.0 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT1144-1 --- --- --- sot1144-1_po European projection Issue date 09-08-28 11-08-23 Figure 7. Package outline SOT1144-1 (HVQFN42) CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 12 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 15 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 13 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 8) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and Table 12 Table 11. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 12. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 8. CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 14 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 8. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16 Abbreviations Table 13. Abbreviations CBTL04083A_CBTL04083B Product data sheet Acronym Description CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model I/O Input/Output PCI Peripheral Component Interconnect PCIe PCI express PRR Pulse Repetition Rate SATA Serial Advanced Technology Attachment USB Universal Serial Bus All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 15 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 17 Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes CBTL04083A_CBTL04083B v.4.1 20200727 Product data sheet - CBTL04083A_CBTL04083B v.4 Modifications: • Added Section 4.1 • Table 2: Added "Not recommended for new design" to 24 mm tape width footnotes CBTL04083A_CBTL04083B v.4 20120625 Product data sheet - CBTL04083A_CBTL04083B v.3 CBTL04083A_CBTL04083B v.3 20110824 Product data sheet - CBTL04083A_CBTL04083B v.2 CBTL04083A_CBTL04083B v.2 20110524 Product data sheet - CBTL04083A_CBTL04083B v.1 CBTL04083A_CBTL04083B v.1 20110228 Product data sheet - - CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 16 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 18 Legal information 18.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. 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Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without CBTL04083A_CBTL04083B Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 17 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for CBTL04083A_CBTL04083B Product data sheet such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 18 / 20 CBTL04083A/CBTL04083B NXP Semiconductors 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Ordering information ..........................................2 Ordering options ................................................2 Pin description ...................................................4 Function selection ............................................. 6 Shutdown function .............................................6 Limiting values .................................................. 8 Recommended operating conditions ................. 8 Tab. 8. Tab. 9. Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Static characteristics ......................................... 8 Dynamic characteristics .................................... 9 Test data ......................................................... 11 SnPb eutectic process (from J-STD-020D) ..... 14 Lead-free process (from J-STD-020D) ............ 14 Abbreviations ...................................................15 Revision history ...............................................16 Fig. 5. Fig. 6. Fig. 7. Fig. 8. Test circuitry for switching times ..................... 11 Test circuit .......................................................11 Package outline SOT1144-1 (HVQFN42) ........12 Temperature profiles for large and small components ..................................................... 15 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Functional diagram of CBTL04083A/B .............. 3 Pin configuration for HVQFN42 .........................4 A/B pinout difference (layout) ............................7 Voltage waveforms for enable and disable times ................................................................ 10 CBTL04083A_CBTL04083B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.1 — 27 July 2020 © NXP B.V. 2020. All rights reserved. 19 / 20 NXP Semiconductors CBTL04083A/CBTL04083B 3.3 V, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch for PCI Express Gen3 Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................2 Ordering information .......................................... 2 Ordering options ................................................ 2 Functional diagram ............................................. 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 4 Functional description ........................................6 Function selection ..............................................6 Shutdown function ............................................. 6 Application design-in information ..................... 7 Limiting values .................................................... 8 Recommended operating conditions ................ 8 Static characteristics .......................................... 8 Dynamic characteristics .....................................9 Test information ................................................ 11 Package outline .................................................12 Soldering of SMD packages .............................13 Introduction to soldering ............................. Wave and reflow soldering ......................... Wave soldering ........................................... Reflow soldering ......................................... Abbreviations .................................................... 15 Revision history ................................................ 16 Legal information .............................................. 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2020. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 July 2020 Document identifier: CBTL04083A_CBTL04083B