CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 multiplexer/demultiplexer switch
Rev. 1 — 16 July 2010 Product data sheet
1. General description
CBTU04083 is an 8-to-4 differential channel multiplexer/demultiplexer switch. The CBTU04083 can switch four differential signals to one of two locations. Using a unique design technique, NXP has minimized the impedance of the switch such that the attenuation observed through the switch is negligible, and also minimized the channel-to-channel skew as well as channel-to-channel crosstalk, as required by the high-speed serial interface. CBTU04083 allows expansion of existing high speed ports for extremely low power.
2. Features and benefits
4 differential channel, 2 : 1 multiplexer/demultiplexer High-speed signal switching; 8.0 Gbit/s Low intra-pair skew: 10 ps maximum (between positive and negative bits) Low inter-pair skew: 35 ps maximum Low crosstalk: −30 dB at 4 GHz Low off-state isolation: −30 dB at 4 GHz VDD operating range: 1.8 V ± 10 % ESD tolerance: 6 kV HBM 1 kV CDM HVQFN42 package
3. Applications
Routing of high-speed differential signals with low signal attenuation PCIe Gen3 DisplayPort 1.2 USB 3.0 SATA 6 Gbit/s
NXP Semiconductors
CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
4. Ordering information
Table 1. Ordering information Package Name CBTU04083BS HVQFN42 Description plastic thermal enhanced very thin quad flat package; no leads; 42 terminals; body 3.5 × 9 × 0.85 mm Version SOT1144-1 Type number
5. Functional diagram
A0_P A0_N A1_P A1_N
B0_P B0_N B1_P B1_N C0_P C0_N C1_P C1_N
A2_P A2_N A3_P A3_N
B2_P B2_N B3_P B3_N C2_P C2_N C3_P C3_N
SEL
002aae642
Fig 1.
Functional diagram of CBTU04083
CBTU04083
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1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
6. Pinning information
6.1 Pinning
41 GND 39 GND 38 B0_P 37 B0_N 36 B1_P 35 B1_N 34 C0_P 33 C0_N 32 C1_P 31 C1_N 29 B2_P 28 B2_N 27 B3_P 26 B3_N 25 C2_P GND (exposed thermal pad) VDD 18 GND 19 VDD 20 GND 21 24 C2_N 23 C3_P 22 C3_N
002aaf592
42 VDD
GND A0_P A0_N GND VDD A1_P A1_N VDD SEL
1 2 3 4 5 6 7 8 9
CBTU04083BS 30 VDD
GND 10 A2_P 11 A2_N 12 VDD 13 GND 14 A3_P 15 A3_N 16 GND 17
Transparent top view
Fig 2.
Pin configuration for HVQFN42
6.2 Pin description
Table 2. Symbol A0_P A0_N A1_P A1_N A2_P A2_N A3_P A3_N B0_P B0_N B1_P B1_N Pin description Pin 2 3 6 7 11 12 15 16 38 37 36 35 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O channel 1, port B differential signal input/output channel 0, port B differential signal input/output channel 3, port A differential signal input/output channel 2, port A differential signal input/output channel 1, port A differential signal input/output Description channel 0, port A differential signal input/output
CBTU04083
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40 VDD
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CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
Pin description …continued Pin 29 28 27 26 34 33 32 31 25 24 23 22 9 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CMOS operation mode select single-ended input SEL = LOW: A → B SEL = HIGH: A → C positive supply voltage, 1.8 V to 2.0 V (± 0.1 V) supply ground channel 3, port C differential signal input/output channel 2, port C differential signal input/output channel 1, port C differential signal input/output channel 0, port C differential signal input/output channel 3, port B differential signal input/output Description channel 2, port B differential signal input/output
Table 2. Symbol B2_P B2_N B3_P B3_N C0_P C0_N C1_P C1_N C2_P C2_N C3_P C3_N SEL
VDD GND
5, 8, 13, 18, 20, power 30, 40, 42 1, 4, 10, 14, 17, power 19, 21, 39, 41, center pad
7. Functional description
Refer to Figure 1 “Functional diagram of CBTU04083”.
7.1 Function selection
Table 3. SEL LOW HIGH Function selection Function An to Bn An to Cn
CBTU04083
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CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Tcase VESD Parameter supply voltage case temperature electrostatic discharge voltage HBM CDM
[1] [2]
[1] [2]
Conditions
Min −0.5 −40 -
Max +2.5 +85 6000 1000
Unit V °C V V
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 5. Symbol VDD VI Tamb Recommended operating conditions Parameter supply voltage input voltage ambient temperature operating in free air Conditions Min 1.62 −0.5 −40 Typ 1.8 Max 1.98 VDD +85 Unit V V °C
10. Static characteristics
Table 6. Static characteristics VDD = 1.8 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol IDD IIH IIL VIH VIL VIK
[1] [2]
Parameter supply current HIGH-level input current LOW-level input current HIGH-level input voltage LOW-level input voltage input clamping voltage
Conditions VDD = max.; VI = GND or VDD VDD = max.; VI = VDD VDD = max.; VI = GND SEL pin SEL pin VDD = max.; II = −18 mA
Min 0.65VDD −0.5 -
Typ[1] −0.7
Max 4 ±5[2] ±5[2] 0.15VDD −1.2
Unit mA μA μA V V V
Typical values are at VDD = 1.8 V, Tamb = 25 °C, and maximum loading. Input leakage current is ±50 μA if differential pairs are pulled to HIGH and LOW.
CBTU04083
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CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
11. Dynamic characteristics
Table 7. Dynamic characteristics VDD = 1.8 V ± 10 %; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol αct αiso(off) DDIL B−3dB tPD Parameter crosstalk attenuation off-state isolation differential insertion loss −3 dB bandwidth propagation delay from left-side port to right-side port, or vice versa Conditions f = 4 GHz f = 100 MHz f = 4 GHz f = 100 MHz f = 4 GHz f = 100 MHz Min Typ[1] −30 −70 −30 −60 −2.8 −0.5 4.3 80 Max Unit dB dB dB dB dB dB GHz ps
Switching characteristics tPZH tPZL tPHZ tPLZ tsk(dif) tsk
[1]
OFF-state to HIGH propagation delay OFF-state to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay differential skew time skew time intra-pair inter-pair
-
-
8.0 8.0 8.0 8.0 10 35
ns ns ns ns ps ps
Typical values are at VDD = 1.8 V; Tamb = 25 °C, and maximum loading.
VDD SEL 0.5VDD 0.5VDD 0V tPZL output 1 0.5VDD tPLZ VOH VOL + 0.15 V tPHZ VOH − 0.15 V VOH VOL
tPZH output 2 0.5VDD
VOL 002aae654
Output 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Output 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. The outputs are measured one at a time with one transition per measurement.
Fig 3.
Voltage waveforms for enable and disable times
CBTU04083
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Product data sheet
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CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
12. Test information
2 × VDD open GND
VDD PULSE GENERATOR VI DUT
RT CL 50 pF
VO
RL 200 Ω
RL 200 Ω 002aae653
CL = load capacitance; includes jig and probe capacitance. RT = termination resistance; should be equal to Zo of the pulse generator. All input pulses are supplied by generators having the following characteristics: PRR ≤ MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns.
Fig 4.
Test circuitry for switching times
PORT 1
4-PORT, 20 GHz NETWORK ANALYZER PORT 2 PORT 3
PORT 4
DUT
002aae655
Fig 5. Table 8. Test
Test circuit Test data Load CL RL 200 Ω 200 Ω 200 Ω 2 × VDD GND open 50 pF 50 pF 50 pF Switch
tPLZ, tPZL (output on B side) tPHZ, tPZH (output on B side) tPD
CBTU04083
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CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
13. Package outline
HVQFN42: plastic thermal enhanced very thin quad flat package; no leads; 42 terminals; body 3.5 x 9 x 0.85 mm
D B A
SOT1144-1
terminal 1 index area
E
A
A1 c
detail X
e1 1/2 e e L 18 17 b 21 22 v w CAB C y1 C C y
e Eh e2
1 terminal 1 index area 42 Dh 39
38 X 0 2.5 scale 5 mm
Dimensions Unit(1) mm A A1 b c 0.2 D 3.6 3.5 3.4 Dh 2.30 2.05 1.90 E 9.1 9.0 8.9 Eh 7.70 7.55 7.40 e 0.5
e1 1.5
e2 8.0
L 0.5 0.4 0.3
v 0.1
w
y
y1 0.1
max 1.00 0.05 0.30 nom 0.85 0.02 0.25 min 0.80 0.00 0.20
0.05 0.05
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT1144-1 References IEC --JEDEC --JEITA --European projection
sot1144-1_po
Issue date 09-08-26 09-08-28
Fig 6.
CBTU04083
Package outline SOT1144-1 (HVQFN42)
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CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
• • • • • •
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
• Solder bath specifications, including temperature and impurities
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CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 7) than a SnPb process, thus reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10
Table 9. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 10. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 7.
CBTU04083
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CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 7.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.
15. Abbreviations
Table 11. Acronym CDM DUT ESD HBM I/O LVDS PCI PCIe PRR SATA USB Abbreviations Description Charged-Device Model Device Under Test ElectroStatic Discharge Human Body Model Input/Output Low-Voltage Differential Signalling Peripheral Component Interconnect PCI express Pulse Repetition Rate Serial Advanced Technology Attachment Universal Serial Bus
16. Revision history
Table 12. Revision history Release date 20100716 Data sheet status Product data sheet Change notice Supersedes Document ID CBTU04083 v.1
CBTU04083
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17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
© NXP B.V. 2010. All rights reserved.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
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NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function selection. . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Soldering of SMD packages . . . . . . . . . . . . . . . 9 Introduction to soldering . . . . . . . . . . . . . . . . . . 9 Wave and reflow soldering . . . . . . . . . . . . . . . . 9 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 July 2010 Document identifier: CBTU04083