CBTU4411EE,551

CBTU4411 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Rev. 4 — 18 June 2012 Product data sheet 1. General description This 11-bit bus switch is designed for 1.7 V to 1.9 V VDD operation and SSTL_18 select input levels. Each Host port pin (HPn) is multiplexed to one of four DIMM port pins (xDPn). The selection of the DIMM port to be connected to the Host port is controlled by a decoder driven by three hardware select pins S0, S1 and EN. Driving pin EN HIGH disconnects all DIMM ports from their respective host ports. When EN is driven LOW, pins S0 and S1 select one of four DIMM ports to be connected to their respective host port. When disconnected, any DIMM port is terminated to the externally supplied voltage Vbias by means of an on-chip pull-down resistor of typically 400 Ω. The ON-state connects the Host port to the DIMM port through a 12 Ω nominal series resistance. The design is intended to have only one DIMM port active at any time. The CBTU4411 can also be configured to support a differential strobe signal on channel 10 (TRUE) and channel 9 (complementary Strobe). When its LVCMOS configuration input strobe enable (STREN) is HIGH, channel 10 is pulled up to 3⁄4 of VDD internally by a resistive divider when the DIMM port is idle. When the CBTU4411 is disabled (EN = HIGH in Strobe mode), the pull-down on channel 10 is disabled for current savings, pulling channel 10 to VDD. When strobe enable (STREN) is LOW, channel 10 behaves the same as all other channels. The select inputs (S0, S1) are pseudo-differential type SSTL_18. A reference voltage should be provided to input pin VREF at nominally 0.5VDD. This topology provides accurate control of switching times by reducing dependency on select signal slew rates. S0 and S1 are provided with selectable input termination to 0.5VDD (active when LVCMOS input TERM is HIGH). When the CBTU4411 is disabled (EN = HIGH), both S0 and S1 inputs are pulled LOW. The part incorporates a very low crosstalk design. It has a very low skew between outputs (< 30 ps) and low skew (< 30 ps) for rising and falling edges. The part has optimal performance in DDR2 data bus applications. Each switch has been optimized for connection to 1- or 2-rank DIMMs. The low internal RC time constant of the switch allows data transfer to be made with minimal propagation delay. The CBTU4411 is characterized for operation from 0 °C to +85 °C. CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 2. Features and benefits  Enable (EN) and select signals (S0, S1) are SSTL_18 compatible  Optimized for use in Double Data Rate 2 (DDR2) SDRAM applications  Suitable to be used with 400 Mbit/s to 800 Mbit/s, 200 MHz to 400 MHz DDR2 data bus  Switch ON-resistance is designed to eliminate the need for series resistor to DDR2 SDRAM  12 Ω ON-resistance  Controlled enable/disable times support fast bus turnaround  Pseudo-differential select inputs support accurate and low-skew control of switching times  Selectable built-in termination resistors on the Sn inputs  Internal 400 Ω pull-down resistors on xDPn port  VBIAS input for optimal DIMM-port pull-down when disabled  Configurable to support differential strobe with pull-up to 3⁄4 of VDD on channel 10 when idle  Low differential skew  Matched rise/fall slew rate  Low crosstalk data-data/data-DQM  Simplified 1 : 4 switch position control by 2-bit encoded input  Single input pin puts all bus switches in OFF (high-impedance) position  Latch-up protection exceeds 500 mA per JESD78  ESD protection exceeds 1500 V HBM per JESD22-A114 and 750 V CDM per JESD22-C101 3. Ordering information Table 1. Ordering information Tamb = 0 °C to +85 °C. Type number CBTU4411EE CBTU4411 Product data sheet Package Name Description Version LFBGA72 plastic low profile fine-pitch ball grid array package; 72 balls; body 7 × 7 × 1.05 mm SOT856-1 All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 2 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 4. Functional diagram SWITCH HP0 0DP0 SWITCH 1DP0 SWITCH 2DP0 SWITCH 3DP0 SWITCH HP10 0DP10 SWITCH VREF 1DP10 SWITCH 2DP10 VDD SWITCH RT × 2(1) 3DP10 RT × 2(1) S0 S1 RT × 2(1) RT × 2(1) SWITCH CONTROL EN TERM STREN 002aae850 (1) Selectable. Fig 1. Functional diagram (positive logic) VDD HPn A RON SWITCH xDPn B from switch control RPU HP10 Rpd 400 Ω from switch control from switch control VBIAS 002aae848 CBTU4411 Product data sheet xDP10 Rpd VBIAS Fig 2. SWITCH Simplified schematic, channel 0 to channel 9 002aae849 Fig 3. All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 Simplified schematic, channel 10 © NXP B.V. 2012. All rights reserved. 3 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 5. Pinning information 5.1 Pinning ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L CBTU4411EE 002aae837 Transparent top view Fig 4. Pin configuration 1 2 3 4 5 6 7 8 9 10 11 A S1 STREN VDD 0DP0 1DP0 2DP0 1DP1 2DP1 3DP1 0DP2 1DP2 B TERM S0 VDD GND HP0 3DP0 0DP1 HP1 GND HP2 2DP2 C VREF EN 0DP3 3DP2 D VBIAS GND HP3 1DP3 E 2DP10 3DP10 2DP3 3DP3 F 1DP10 HP10 GND 0DP4 G 0DP10 GND HP4 1DP4 H 3DP9 2DP9 2DP4 3DP4 J 1DP9 HP9 1DP5 0DP5 K 0DP9 GND HP8 0DP8 HP7 0DP7 GND HP6 0DP6 HP5 2DP5 L 3DP8 2DP8 1DP8 3DP7 2DP7 1DP7 3DP6 2DP6 1DP6 VDD 3DP5 002aae838 Blank cell indicates no ball at that location. Fig 5. CBTU4411 Product data sheet Ball mapping (transparent top view) All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 4 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 5.2 Pin description CBTU4411 Product data sheet Table 2. Pin description Symbol Pin HP0 to HP10 B5, B8, B10, D10, Host ports G10, K10, K8, K5, K3, J2, F2 EN C2 LVCMOS level enable input (active LOW). When connected HIGH, all DIMM ports will be disconnected (show a high-impedance path) from the Host ports. STREN A2 Strobe enable. LVCMOS level strobe enable input (active HIGH). When tied LOW, channel 10 (HP10 and its DP ports) functions identically to all other channels. When tied HIGH, channel 10 is designated as the Strobe channel (see Section 6.1 “Function selection”, Figure 2 and Figure 3). S0 B2 S1 A1 Select inputs; type SSTL_18. See Section 6.1 “Function selection”. VREF C1 Reference voltage for the pseudo-differential SSTL_18 select inputs (S0, S1). VBIAS D1 Voltage bias for the DIMM port pull-down resistor (Rpd). TERM B1 LVCMOS level input pin activates termination resistance on Sn inputs when HIGH; high-impedance when LOW. 0DP0, 1DP0, 2DP0, 3DP0 A4, A5, A6, B6 DIMM port 0 0DP1, 1DP1, 2DP1, 3DP1 B7, A7, A8, A9 DIMM port 1 0DP2, 1DP2, 2DP2, 3DP2 A10, A11, B11, C11 DIMM port 2 0DP3, 1DP3, 2DP3, 3DP3 C10, D11, E10, E11 DIMM port 3 0DP4, 1DP4, 2DP4, 3DP4 F11, G11, H10, H11 DIMM port 4 0DP5, 1DP5, 2DP5, 3DP5 J11, J10, K11, L11 DIMM port 5 0DP6, 1DP6, 2DP6, 3DP6 K9, L9, L8, L7 DIMM port 6 0DP7, 1DP7, 2DP7, 3DP7 K6, L6, L5, L4 DIMM port 7 0DP8, 1DP8, 2DP8, 3DP8 K4, L3, L2, L1 DIMM port 8 0DP9, 1DP9, 2DP9, 3DP9 K1, J1, H2, H1 DIMM port 9 Description 0DP10, 1DP10, G1, F1, 2DP10, 3DP10 E1, E2 DIMM port 10 GND B4, B9, D2, F10, G2, K2, K7 Ground VDD A3, B3, L10 Positive supply voltage All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 5 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 6. Functional description Refer to Figure 1 “Functional diagram (positive logic)”. 6.1 Function selection Table 3. Function selection, channel 0 to channel 9 H = HIGH voltage level; L = LOW voltage level; high-Z = high-impedance; X = Don’t care. Inputs Function 0DPn EN S1 S0 1DPn 2DPn 3DPn HPn VBIAS HPn VBIAS HPn VBIAS HPn VBIAS high-Z Rpd high-Z Rpd high-Z Rpd L L L RON high-Z L L H high-Z Rpd RON high-Z high-Z Rpd high-Z Rpd L H L high-Z Rpd high-Z Rpd RON high-Z high-Z Rpd L H H high-Z Rpd high-Z Rpd high-Z Rpd RON high-Z Rpd high-Z Rpd high-Z Rpd high-Z Rpd H X CBTU4411 Product data sheet X high-Z All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 6 of 21 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors CBTU4411 Product data sheet Table 4. Function selection, channel 10 H = HIGH voltage level; L = LOW voltage level; high-Z = high-impedance; X = Don’t care. Inputs Function 0DP10 1DP10 2DP10 3DP10 EN S1 S0 STREN HP10 VBIAS VDD HP10 VBIAS VDD HP10 VBIAS VDD HP10 VBIAS VDD L L L L RON high-Z high-Z high-Z Rpd high-Z high-Z Rpd high-Z high-Z Rpd high-Z L L L H RON high-Z high-Z high-Z Rpd RPU high-Z Rpd RPU high-Z Rpd RPU L L H L high-Z Rpd high-Z RON high-Z high-Z high-Z Rpd high-Z high-Z Rpd high-Z L L H H high-Z Rpd RPU RON high-Z high-Z high-Z Rpd RPU high-Z Rpd RPU L H L L high-Z Rpd high-Z high-Z Rpd high-Z RON high-Z high-Z high-Z Rpd high-Z H L H high-Z Rpd RPU high-Z Rpd RPU RON high-Z high-Z high-Z Rpd RPU L H H L high-Z Rpd high-Z high-Z Rpd high-Z high-Z Rpd high-Z RON high-Z high-Z L H H H high-Z Rpd RPU high-Z Rpd RPU high-Z Rpd RPU RON high-Z high-Z H X X L high-Z Rpd high-Z high-Z Rpd high-Z high-Z Rpd high-Z high-Z Rpd high-Z H X X H high-Z high-Z RPU high-Z high-Z RPU high-Z high-Z RPU high-Z high-Z RPU Table 5. S0, S1 input termination H = HIGH voltage level; L = LOW voltage level; X = Don’t care. EN TERM Sn input termination L L Termination resistors on S0, S1 inputs disconnected (high-impedance). L H Termination resistors on S0, S1 inputs active. H X Pull-down to GND via RT × 2. Also disables the S0, S1 input receivers for power savings. CBTU4411 7 of 21 © NXP B.V. 2012. All rights reserved. 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Rev. 4 — 18 June 2012 All information provided in this document is subject to legal disclaimers. L CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 7. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). The package thermal impedance is calculated in accordance with JESD 51. Symbol Parameter VDD supply voltage IIK input clamping current input voltage VI Min Max Unit −0.5 +2.5 V - −50 mA S0, S1 pins only [1] - VDD + 0.3 V except S0, S1 pins [1] −0.5 +2.5 V −65 +150 °C VI/O < 0 V storage temperature Tstg [1] Conditions The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed. 8. Recommended operating conditions Table 7. Operating conditions All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 1.7 - 1.9 V Vref reference voltage 0.49 × VDD 0.50 × VDD 0.51 × VDD V Vbias bias voltage 0 0.30 × VDD 0.33 × VDD V VT termination voltage Vref − 0.04 Vref Vref + 0.04 V pull-down resistor input [1] Vi input voltage 0 - VDD V VIH(AC) AC HIGH-level input voltage S0, S1 inputs Vref + 0.250 - - V VIL(AC) AC LOW-level input voltage S0, S1 inputs - - Vref − 0.250 V VIH(DC) DC HIGH-level input voltage S0, S1 inputs Vref + 0.125 - - V VIL(DC) DC LOW-level input voltage S0, S1 inputs - - Vref − 0.125 V VIH HIGH-level input voltage EN, STREN, TERM pins 0.65 × VDD - - V VIL LOW-level input voltage EN, STREN, TERM pins - - 0.35 × VDD V Tamb ambient temperature operating in free air 0 - +85 °C [1] Vbias > 0.5 × VDD is reserved for test purposes only. CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 8 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 9. Static characteristics Table 8. Static characteristics Tamb = 0 °C to +85 °C Symbol Parameter Conditions Min Typ[1] Max Unit VIK input clamping voltage VDD = 1.7 V; II = −18 mA - - −1.2 V VT termination voltage on S0, S1 inputs when Sn = open circuit and TERM = HIGH 0.5VDD − 0.04 0.5VDD 0.5VDD + 0.04 V Vpu pull-up voltage channel 10 DIMM port; EN = LOW; Vbias = 0.54 V; VDD = 1.8 V; STREN = HIGH; unselected DIMM port 0.5VDD + 0.25 0.75VDD 0.75VDD + 0.25 V ILI input leakage current VDD = 1.8 V; VI = VDD or GND; Sn = VDD; Vbias = VDD; TERM = LOW S0, S1 - - ±100 μA host port - - ±100 μA DIMM port - - ±100 μA EN = LOW - 6 9 mA EN = HIGH - 5 100 μA - 3 - pF supply current IDD VDD = 1.8 V; IO = 0 A; VI = VDD or GND Cin input capacitance S0, S1 pins; VI = 1.8 V or 0 V Csw switch capacitance switch ON; VI = 0.9 V RON ON resistance pull-down resistance Rpd - 4 6 pF VDD = 1.8 V; VHPn = Vref; VxDPn = Vref ± 250 mV [2] 10 12 17 Ω VDD = 1.8 V; VHPn = Vref; VxDPn = Vref ± 500 mV [2] 10 12 17 Ω 280 400 520 Ω channel 10; STREN = LOW 280 400 520 Ω channel 10; STREN = HIGH 780 1120 1460 Ω EN = HIGH; Vbias = 0.54 V; VDD = 1.8 V RPU pull-up resistance EN = HIGH; Vbias = 0.54 V; VDD = 1.8 V; channel 10; STREN = HIGH 430 622 810 Ω RT termination resistance Sn input; Thevenin equivalent (see Figure 1); input voltage sweep 0 < VI (Sn) < VDD; TERM = HIGH 55 80 105 Ω [1] All typical values are at VDD = 1.8 V, Tamb = 25 °C. [2] Measured by the current between the host and the DIMM terminals at the indicated voltages on each side of the switch. CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 9 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 002aae863 450 RPD (Ω) 425 400 375 350 0 Fig 6. 0.2 0.4 0.6 0.8 VDIMM − Vbias (V) Pull-down resistance versus voltage 10. Dynamic characteristics Table 9. Dynamic characteristics VDD = 1.8 V ± 0.1 V. Symbol Parameter Conditions tPD propagation delay from HPn or xDPn to xDPn or HPn; Figure 9, Figure 13 Min Typ Max Unit - 50 100 ps tPZH driver enable delay to HIGH level from Sn to HPn or xDPn 0.75 - 1.75 ns tPZL driver enable delay to LOW level tPHZ from Sn to HPn or xDPn 0.75 - 1.75 ns driver disable delay from HIGH level from Sn to HPn or xDPn 0.75 - 1.75 ns tPLZ driver disable delay from LOW level from Sn to HPn or xDPn tsk(o) output skew time from any output to any output; Figure 12 tsk(edge) edge skew time Figure 11 [1] [1] 0.75 - 1.75 ns [2] - 25 30 ps [2][3] - 25 30 ps This parameter is not production tested. [2] Skew is not production tested. [3] Difference of rising edge propagation delay to falling edge propagation delay. CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 10 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 11. HPn to xDPn AC waveforms and test circuit 1.8 V input 0.9 V 0.9 V 0V tPLH tPHL VOH output 0.9 V 0.9 V VOL 002aae864 Fig 7. Input to output propagation delays 1.8 V EN, Sn(1) Vref Vref tPZH tPHZ 0V output waveform 1(2) VOH VOH − 100 mV 0.9 V 002aae865 Vbias (1) See Section 6.1 “Function selection”. (2) Waveform 1 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. Fig 8. 3-state output enable and disable times Zo = 40 Ω HPn DUT xDPn 10.16 cm (4") SSTL_18 driver Zo = 40 Ω 2.54 cm (1") CL 6 pF 75 Ω VT = Vref 002aae866 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; slew rate = 2.5 V/ns. The outputs are measured one at a time with one transition per measurement. Fig 9. CBTU4411 Product data sheet Test circuit (HPn to xDPn) All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 11 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 12. xDPn to HPn AC waveforms and test circuit 1.8 V EN, Sn(1) Vref Vref tPZL tPLZ 0V 1.8 V output waveform 1(2) 0.9 V VOL + 100 mV tPZH output waveform 2(3) tPHZ VOL VOH VOH − 100 mV 0.9 V VOL 002aae867 (1) See Section 6.1 “Function selection”. (2) Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. (3) Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. Fig 10. 3-state output enable and disable times 1.8 V input 0.9 V 0.9 V rising tsk(edge) falling tsk(edge) 0V VOH output 0.9 V 0.9 V VOL 002aae868 Fig 11. Rising and falling edge skew any two outputs tsk(o) 002aac820 Fig 12. Skew between any two outputs CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 12 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Zo = 40 Ω HPn DUT 2.54 cm (1") Zo = 40 Ω xDPn 10.16 cm (4") SSTL_18 driver CL 6 pF 75 Ω VT = Vref 002aae869 All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; slew rate = 2.5 V/ns. The outputs are measured one at a time with one transition per measurement. Fig 13. Test circuit (xDPn to HPn) 13. Test information Table 10. CBTU4411 Product data sheet IDD test mode Condition Description Vbias = VDD All DIMM ports are disconnected (high-impedance) from their host ports, and disconnected (high-impedance) from VBIAS and RPU. Used for production testing only. Vbias < 0.5VDD Normal operation. See Section 6.1 “Function selection”. All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 13 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 14. Package outline LFBGA72: plastic low profile fine-pitch ball grid array package; 72 balls; body 7 x 7 x 1.05 mm D SOT856-1 B A ball A1 index area E A2 A A1 C e1 e ∅v ∅w b L K J H G F E D C B A M M y y1 C C A B C e e2 ball A1 index area 1 2 3 4 5 6 7 8 9 10 11 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.3 0.2 1.20 0.95 0.35 0.25 7.2 6.8 7.2 6.8 0.5 5 5 0.15 0.05 0.08 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-04-27 04-05-12 SOT856-1 Fig 14. Package outline SOT856-1 (LFBGA72) CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 14 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 15 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Table 11. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 12. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15. CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 16 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 15. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 13. CBTU4411 Product data sheet Abbreviations Acronym Description CDM Charged-Device Model DDR2 Double Data Rate 2 DIMM Dual In-Line Memory Module DQM Data Queue Mask ESD ElectroStatic Discharge HBM Human Body Model LVCMOS Low Voltage Complementary Metal-Oxide Semiconductor MUX Multiplexer PRR Pulse Repetition Rate RC Resistor-Capacitor network SDRAM Synchronous Dynamic Random Access Memory SSTL_18 Stub Series Terminated Logic for 1.8 V All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 17 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 17. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes CBTU4411 v.4 20120618 Product data sheet - CBTU4411 v.3 Modifications: • Section 2 “Features and benefits”, 18th bullet item: removed phrase “200 V MM per JESD22-A115” • Table 8 “Static characteristics”: – Symbol/Parameter “Con, switch on capacitance” changed to “Csw, switch capacitance” (and placed “switch ON” under Conditions) – RON Min value for Condition “VxDPn = Vref ± 250 mV” changed from “7 Ω” to “10 Ω” – RON Min value for Condition “VxDPn = Vref ± 500 mV” changed from “7 Ω” to “10 Ω” – deleted ΔRON row • Table 13 “Abbreviations”: removed “MM” from list of acronyms CBTU4411 v.3 20091012 Product data sheet - CBTU4411 v.2 CBTU4411 v.2 20060922 Product data sheet - CBTU4411 v.1 CBTU4411 v.1 (9397 750 12977) 20050107 Product data sheet - - CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 18 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. CBTU4411 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 19 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com CBTU4411 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 18 June 2012 © NXP B.V. 2012. All rights reserved. 20 of 21 CBTU4411 NXP Semiconductors 11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance 20. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function selection. . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 HPn to xDPn AC waveforms and test circuit. 11 xDPn to HPn AC waveforms and test circuit. 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering of SMD packages . . . . . . . . . . . . . . 15 Introduction to soldering . . . . . . . . . . . . . . . . . 15 Wave and reflow soldering . . . . . . . . . . . . . . . 15 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 June 2012 Document identifier: CBTU4411