DSP56303VF100B1

Freescale Semiconductor Technical Data DSP56303 Rev. 11, 2/2005 DSP56303 24-Bit Digital Signal Processor 16 6 6 3 Memory Expansion Area Peripheral Expansion Area PrograM RAM 4096 × 24 bits (default) Address Generation Unit Six-Channel DMA Unit X Data RAM 2048 × 24 bits (default) YAB XAB PAB DAB Y Data RAM 2048 × 24 bits (default) YM_EB SCI XM_EB ESSI PM_EB HI08 PIO_EB Triple Timer 18 External Address Bus Address Switch External Bus 13 Interface and Inst. Cache Control Control 24-Bit Bootstrap ROM DSP56300 Core DDB YDB XDB PDB GDB Internal Data Bus Switch External Data Bus Switch EXTAL XTAL Clock Generator PLL Program Interrupt Controller Program Decode Controller Program Address Generator The DSP56303 is intended for use in telecommunication applications, such as multiline voice/data/ fax processing, video conferencing, audio applications, control, and general digital signal processing. Data ALU 24 × 24 + 56 →56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter Power Management 24 What’s New? Data 5 Rev. 11 includes the following changes: • Adds lead-free packaging and part numbers. JTAG OnCE™ DE 2 RESET PINIT/NMI MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1. DSP56303 Block Diagram The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable wireless, telecommunications, and multimedia products. © Freescale Semiconductor, Inc., 1996, 2005. All rights reserved. Table of Contents Data Sheet Conventions .......................................................................................................................................ii Features...............................................................................................................................................................iii Target Applications ............................................................................................................................................. iv Product Documentation ......................................................................................................................................iv Chapter 1 Signals/Connections 1.1 1.2 1.3 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 Chapter 2 Specifications 2.1 2.3 2.4 2.5 Chapter 3 TQFP Package Description...............................................................................................................................3-2 TQFP Package Mechanical Drawing................................................................................................................3-9 MAP-BGA Package Description ....................................................................................................................3-10 MAP-BGA Package Mechanical Drawing .....................................................................................................3-18 Design Considerations 4.1 4.2 4.3 4.4 4.5 Appendix A Maximum Ratings.............................................................................................................................................2-1 Thermal Characteristics ....................................................................................................................................2-2 DC Electrical Characteristics............................................................................................................................2-2 AC Electrical Characteristics............................................................................................................................2-3 Packaging 3.1 3.2 3.3 3.4 Chapter 4 Power ................................................................................................................................................................1-3 Ground ..............................................................................................................................................................1-3 Clock.................................................................................................................................................................1-4 External Memory Expansion Port (Port A) ......................................................................................................1-4 Interrupt and Mode Control ..............................................................................................................................1-7 Host Interface (HI08)........................................................................................................................................1-8 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12 Serial Communication Interface (SCI) ...........................................................................................................1-14 Timers .............................................................................................................................................................1-15 JTAG and OnCE Interface ..............................................................................................................................1-16 Thermal Design Considerations........................................................................................................................4-1 Electrical Design Considerations......................................................................................................................4-2 Power Consumption Considerations.................................................................................................................4-3 PLL Performance Issues ...................................................................................................................................4-4 Input (EXTAL) Jitter Requirements .................................................................................................................4-5 Power Consumption Benchmark Data Sheet Conventions OVERBAR “asserted” “deasserted” Examples: Indicates a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol Logic State Signal State PIN True Asserted PIN False Deasserted PIN True Asserted PIN False Deasserted Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. Voltage VIL/VOL VIH /VOH VIH /VOH VIL/VOL DSP56303 Technical Data, Rev. 11 ii Freescale Semiconductor Features Table 1 lists the features of the DSP56303 device. Table 1. DSP56303 Features Feature Description High-Performance DSP56300 Core • 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal • Object code compatible with the DSP56000 core with highly parallel instruction set • Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control • Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable hardware stack, nested hardware DO loops, and fast auto-return interrupts • Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals • Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock with skew elimination • Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG) test access port (TAP) Internal Peripherals • Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs • Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) • Serial communications interface (SCI) with baud rate generator • Triple timer module • Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled • 192 × 24-bit bootstrap ROM • 8 K × 24-bit RAM total • Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable: Internal Memories External Memory Expansion Power Dissipation Packaging Program RAM Size Instruction Cache Size X Data RAM Size Y Data RAM Size Instruction Cache Switch Mode 4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit disabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit enabled disabled 2048 × 24-bit 0 3072 × 24-bit 3072 × 24-bit disabled enabled 1024 × 24-bit 1024 × 24-bit 3072 × 24-bit 3072 × 24-bit enabled enabled • Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address lines • Program memory expansion to one 256 K × 24-bit words memory space using the standard external address lines • External memory expansion port • Chip select logic for glueless interface to static random access memory (SRAMs) • Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs) • • • • Very low-power CMOS design Wait and Stop low-power standby modes Fully static design specified to operate down to 0 Hz (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, and modedependent) • 144-pin TQFP package in lead-free or lead-bearing versions • 196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions DSP56303 Technical Data, Rev. 11 Freescale Semiconductor iii Target Applications Examples include: • • • • Multi-line voice/data/fax processing Video conferencing Audio applications Control Product Documentation The documents listed in Table 2 are required for a complete description of the DSP56303 device and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation updates, visit the Freescale DSP website. See the contact information on the back cover of this document. Table 2. DSP56303 Documentation Name DSP56303 User’s Manual Description Detailed functional description of the DSP56303 memory configuration, operation, and register programming Order Number DSP56303UM DSP56300 Family Detailed description of the DSP56300 family processor core and instruction set Manual DSP56300FM Application Notes See the DSP56303 product website Documents describing specific applications or optimized device operation including code examples DSP56303 Technical Data, Rev. 11 iv Freescale Semiconductor 1 Signals/Connections The DSP56303 input and output signals are organized into functional groups as shown in Table 1-1. Figure 1-1 diagrams the DSP56303 signals by functional group. The remainder of this chapter describes the signal pins in each functional group. Table 1-1. DSP56303 Functional Signal Groupings Number of Signals Functional Group TQFP MAP-BGA Power (VCC) 18 18 Ground (GND) 19 66 Clock 2 2 PLL 3 3 Address bus 18 18 24 24 13 13 Port A1 Data bus Bus control Interrupt and mode control 5 5 Port B2 16 16 Ports C and D 3 12 12 3 3 Timer 3 3 OnCE/JTAG Port 6 6 Host interface (HI08) Enhanced synchronous serial interface (ESSI) 4 Serial communication interface (SCI) Notes: 1. 2. 3. 4. 5. Port E Port A signals define the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the HI08 port signals multiplexed with the GPIO signals. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. Port E signals are the SCI port signals multiplexed with the GPIO signals. There are 2 signal connections in the TQFP package and 7 signal connections in the MAP-BGA package that are not used. These are designated as no connect (NC) in the package description (see Chapter 3). Note: This chapter refers to a number of configuration registers used to select individual multiplexed signal functionality. Refer to the DSP56303 User’s Manual for details on these configuration registers. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 1-1 Signals/Connections DSP56303 VCCP VCCQ VCCA VCCD VCCC VCCH VCCS GNDP GNDP1 GNDQ GNDA GNDD GNDC GNDH GNDS 4 4 4 2 2 Grounds4: PLL PLL Internal Logic Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer 4 4 2 2 EXTAL XTAL During Reset PINIT Power Inputs: PLL Internal Logic Address Bus Data Bus Bus Control HI08 ESSI/SCI/Timer Clock CLKOUT PCAP After Reset NMI Interrupt/ Mode Control 8 Host Interface (HI08) Port1 Enhanced Synchronous Serial Interface Port 0 (ESSI0) 2 3 Enhanced Synchronous Serial Interface Port 1 (ESSI1) 2 3 During Reset MODA MODB MODC MODD RESET After Reset IRQA IRQB IRQC IRQD RESET Non-Multiplexed Bus H[0–7] HA0 HA1 HA2 HCS/HCS Single DS HRW HDS/HDS Single HR HREQ/HREQ HACK/HACK Multiplexed Bus HAD[0–7] HAS/HAS HA8 HA9 HA10 Double DS HRD/HRD HWR/HWR Double HR HTRQ/HTRQ HRRQ/HRRQ SC0[0–2] SCK0 SRD0 STD0 Port C GPIO PC[0–2] PC3 PC4 PC5 SC1[0–2] SCK1 SRD1 STD1 Port D GPIO PD[0–2] PD3 PD4 PD5 RXD TXD SCLK Port E GPIO PE0 PE1 PE2 PLL Port B GPIO PB[0–7] PB8 PB9 PB10 PB13 PB11 PB12 PB14 PB15 Port A A[0–17] D[0–23] AA0/RAS0– AA3/RAS3 RD WR TA BR BG BB CAS BCLK BCLK Notes: 1. 2. 3. 4. 18 24 4 External Address Bus Serial Communications Interface (SCI) Port2 External Data Bus External Bus Control Timers3 OnCE/ JTAG Port TIO0 TIO1 TIO2 Timer GPIO TIO0 TIO1 TIO2 TCK TDI TDO TMS TRST DE The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or double Host Request (HR) configurations. Since each of these modes is configured independently, any combination of these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]). Signals with dual designations (for example, HAS/HAS) have configurable polarity. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals (PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively. TIO[0–2] can be configured as GPIO signals. Ground connections shown in this figure are for the TQFP package. In the MAP-BGA package, in addition to the GNDP and GNDP1 connections, there are 64 GND connections to a common internal package ground plane. Figure 1-1. Signals Identified by Functional Group DSP56303 Technical Data, Rev. 11 1-2 Freescale Semiconductor Power 1.1 Power Table 1-2. Power Name Power Inputs Description VCCP PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCCQ Quiet Power—An isolated power for the core processing logic. This input must be isolated externally from all other chip power inputs. VCCA Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQ. VCCD Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQ. VCCC Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQ. VCCH Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQ. VCCS ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied externally to all other chip power inputs, except VCCQ. Note: The user must provide adequate external decoupling capacitors for all power connections. 1.2 Ground Table 1-3. Ground Name Grounds1 Description GNDP PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GND P by a 0.47 µF capacitor located as close as possible to the chip package. GNDP1 PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. GNDQ2 Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling capacitors. GNDA2 Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections, except GND P and GND P1. The user must provide adequate external decoupling capacitors. GNDD2 Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling capacitors. GNDC2 Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling capacitors. GNDH2 Host Ground—An isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other chip ground connections, except GND P and GND P1. The user must provide adequate external decoupling capacitors. GNDS2 ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground connections, except GND P and GND P1. The user must provide adequate external decoupling capacitors. GND3 Notes: Ground—Connected to an internal device ground plane. 1. 2. 3. The user must provide adequate external decoupling capacitors for all GND connections. These connections are only used on the TQFP package. These connections are common grounds used on the MAP-BGA package. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 1-3 Signals/Connections 1.3 Clock Table 1-4. Signal Name Type State During Reset Clock Signals Signal Description EXTAL Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator input to an external crystal or an external clock. XTAL Output Chip-driven Crystal Output—Connects the internal crystal oscillator output to an external crystal. If an external clock is used, leave XTAL unconnected. 1.4 PLL Table 1-5. Signal Name CLKOUT Type Output Phase-Locked Loop Signals State During Reset Signal Description Chip-driven Clock Output—Provides an output clock synchronized to the internal core clock phase. If the PLL is enabled and both the multiplication and division factors equal one, then CLKOUT is also synchronized to EXTAL. If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL. PCAP Input Input PLL Capacitor—An input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP can be tied to VCC, GND, or left floating. PINIT Input NMI Input Input PLL Initial—During assertion of RESET, the value of PINIT is written into the PLL enable (PEN) bit of the PLL control (PCTL) register, determining whether the PLL is enabled or disabled. Nonmaskable Interrupt—After RESET deassertion and during normal instruction processing, this Schmitt-trigger input is the negative-edge-triggered NMI request internally synchronized to CLKOUT. Note: PINIT/NMI can tolerate 5 V. 1.5 External Memory Expansion Port (Port A) Note: When the DSP56303 enters a low-power standby mode (stop or wait), it releases bus mastership and tristates the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS. 1.5.1 External Address Bus Table 1-6. Signal Name A[0–17] Type Output State During Reset, Stop, or Wait Tri-stated External Address Bus Signals Signal Description Address Bus—When the DSP is the bus master, A[0–17] are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A[0–17] do not change state when external memory spaces are not being accessed. DSP56303 Technical Data, Rev. 11 1-4 Freescale Semiconductor External Memory Expansion Port (Port A) 1.5.2 External Data Bus Table 1-7. Signal Name D[0–23] 1.5.3 State During Stop or Wait State During Reset Type Input/ Output Ignored Input Last state: Input: Ignored Output: Tri-stated Signal Description Data Bus—When the DSP is the bus master, D[0–23] are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D[0–23] are tri-stated. External Bus Control Table 1-8. Signal Name External Data Bus Signals Type State During Reset, Stop, or Wait Tri-stated External Bus Control Signals Signal Description AA[0–3] Output Address Attribute—When defined as AA, these signals can be used as chip selects or additional address lines. The default use defines a priority scheme under which only one AA signal can be asserted at a time. Setting the AA priority disable (APD) bit (Bit 14) of the Operating Mode Register, the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals. RAS[0–3] Output RD Output Tri-stated Read Enable—When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is tristated. WR Output Tri-stated Write Enable—When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D[0–23]). Otherwise, the signals are tri-stated. TA Input Ignored Input Transfer Acknowledge—If the DSP56303 is the bus master and there is no external bus activity, or the DSP56303 is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the wait states inserted by the bus control register (BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to CLKOUT. The number of wait states is determined by the TA input or by the BCR, whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. Row Address Strobe—When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. To use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion; otherwise, improper operation may result. TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the Operating Mode Register. TA functionality cannot be used during DRAM type accesses; otherwise improper operation may result. BR Output Reset: Output (deasserted) State during Stop/Wait depends on BRH bit setting: • BRH = 0: Output, deasserted • BRH = 1: Maintains last state (that is, if asserted, remains asserted) Bus Request—Asserted when the DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independently of whether the DSP56303 is a bus master or a bus slave. Bus “parking” allows BR to be deasserted even though the DSP56303 is the bus master. (See the description of bus “parking” in the BB signal description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is affected only by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 1-5 Signals/Connections Table 1-8. Signal Name BG Type Input External Bus Control Signals (Continued) State During Reset, Stop, or Wait Ignored Input Signal Description Bus Grant—Asserted by an external bus arbitration circuit when the DSP56303 becomes the next bus master. When BG is asserted, the DSP56303 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. The default operation of this bit requires a setup and hold time as specified in Table 214. An alternate mode can be invoked: set the asynchronous bus arbitration enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set, BG and BB are synchronized internally. This eliminates the respective setup and hold time requirements but adds a required delay between the deassertion of an initial BG input and the assertion of a subsequent BG input. BB Input/ Output Ignored Input Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. Called “bus parking,” this allows the current bus master to reuse the bus without rearbitration until another device requires the bus. BB is deasserted by an “active pull-up” method (that is, BB is driven high and then released and held high by an external pull-up resistor). The default operation of this signal requires a setup and hold time as specified in Table 2-14. An alternative mode can be invoked by setting the ABE bit (Bit 13) in the Operating Mode Register. When this bit is set, BG and BB are synchronized internally. See BG for additional information. Note: BB requires an external pull-up resistor. CAS Output Tri-stated Column Address Strobe—When the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. BCLK Output Tri-stated Bus Clock When the DSP is the bus master, BCLK is active when the Operating Mode Register Address Trace Enable bit is set. When BCLK is active and synchronized to CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. BCLK Output Tri-stated Bus Clock Not When the DSP is the bus master, BCLK is the inverse of the BCLK signal. Otherwise, the signal is tri-stated. DSP56303 Technical Data, Rev. 11 1-6 Freescale Semiconductor Interrupt and Mode Control 1.6 Interrupt and Mode Control The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines. Table 1-9. Signal Name Type State During Reset Interrupt and Mode Control Signal Description RESET Input Schmitt-trigger Input Reset—Places the chip in the Reset state and resets the internal phase generator. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted after powerup. MODA Input Schmitt-trigger Input Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. IRQA Input MODB Input IRQB Input MODC Input IRQC MODD IRQD External Interrupt Request A—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the STOP or WAIT standby state and IRQA is asserted, the processor exits the STOP or WAIT state. Schmitt-trigger Input External Interrupt Request B—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQB is asserted, the processor exits the WAIT state. Schmitt-trigger Input Input Input Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. External Interrupt Request C—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQC is asserted, the processor exits the WAIT state. Schmitt-trigger Input Input Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the Operating Mode Register when the RESET signal is deasserted. External Interrupt Request D—After reset, this input becomes a levelsensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. If the processor is in the WAIT standby state and IRQD is asserted, the processor exits the WAIT state. Note: These signals are all 5 V tolerant. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 1-7 Signals/Connections 1.7 Host Interface (HI08) The HI08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. The HI08 supports a variety of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, DSPs, and DMA hardware. 1.7.1 Host Port Usage Considerations Careful synchronization is required when the system reads multiple-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected (as they are in the Host port). The considerations for proper operation are discussed in Table 1-10. Table 1-10. Host Port Usage Considerations Action Description Asynchronous read of receive byte registers When reading the receive byte registers, Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL), the host interface programmer should use interrupts or poll the Receive register Data Full (RXDF) flag that indicates data is available. This assures that the data in the receive byte registers is valid. Asynchronous write to transmit byte registers The host interface programmer should not write to the transmit byte registers, Transmit register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL), unless the Transmit register Data Empty (TXDE) bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers transfer valid data to the Host Receive (HRX) register. Asynchronous write to host vector The host interface programmer must change the Host Vector (HV) register only when the Host Command bit (HC) is clear. This practice guarantees that the DSP interrupt control logic receives a stable vector. 1.7.2 Host Port Configuration HI08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits in the HI08 Port Control Register. Table 1-11. Host Interface Type State During Reset1,2 H[0–7] Input/Output Ignored Input HAD[0–7] Input/Output Host Address—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, these signals are lines 0–7 of the bidirectional multiplexed Address/Data bus. Input or Output Port B 0–7—When the HI08 is configured as GPIO through the HI08 Port Control Register, these signals are individually programmed as inputs or outputs through the HI08 Data Direction Register. Signal Name PB[0–7] Signal Description Host Data—When the HI08 is programmed to interface with a non-multiplexed host bus and the HI function is selected, these signals are lines 0–7 of the bidirectional Data bus. DSP56303 Technical Data, Rev. 11 1-8 Freescale Semiconductor Host Interface (HI08) Table 1-11. Host Interface (Continued) Type State During Reset1,2 HA0 Input Ignored Input HAS/HAS Input Host Address Strobe—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable but is configured active-low (HAS) following reset. PB8 Input or Output Port B 8—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. HA1 Input HA8 Input Host Address 8—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus. PB9 Input or Output Port B 9—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. HA2 Input HA9 Input Host Address 9—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. PB10 Input or Output Port B 10—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. Signal Name Ignored Input Ignored Input Signal Description Host Address Input 0—When the HI08 is programmed to interface with a nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address Input 1—When the HI08 is programmed to interface with a nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address Input 2—When the HI08 is programmed to interface with a nonmultiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. HCS/HCS Input HA10 Input Host Address 10—When the HI08 is programmed to interface with a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. PB13 Input or Output Port B 13—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. HRW Input HRD/HRD Input Host Read Data—When the HI08 is programmed to interface with a doubledata-strobe host bus and the HI function is selected, this signal is the HRD strobe Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HRD) after reset. Input or Output Port B 11—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. PB11 Ignored Input Ignored Input Host Chip Select—When the HI08 is programmed to interface with a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable but is configured active-low (HCS) after reset. Host Read/Write—When the HI08 is programmed to interface with a singledata-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 1-9 Signals/Connections Table 1-11. Host Interface (Continued) Type State During Reset1,2 HDS/HDS Input Ignored Input HWR/HWR Input Host Write Data—When the HI08 is programmed to interface with a doubledata-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HWR) following reset. Input or Output Port B 12—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. Signal Name PB12 Signal Description Host Data Strobe—When the HI08 is programmed to interface with a singledata-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable but is configured as active-low (HDS) following reset. HREQ/HREQ Output HTRQ/HTRQ Output Transmit Host Request—When the HI08 is programmed to interface with a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable but is configured as active-low (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. Input or Output Port B 14—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. PB14 HACK/HACK Input HRRQ/HRRQ Output PB15 Notes: Input or Output 1. 2. 3. Ignored Input Ignored Input Host Request—When the HI08 is programmed to interface with a single host request host bus and the HI function is selected, this signal is the host request (HREQ) output. The polarity of the host request is programmable but is configured as active-low (HREQ) following reset. The host request may be programmed as a driven or open-drain output. Host Acknowledge—When the HI08 is programmed to interface with a single host request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable but is configured as active-low (HACK) after reset. Receive Host Request—When the HI08 is programmed to interface with a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable but is configured as active-low (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. Port B 15—When the HI08 is configured as GPIO through the HI08 Port Control Register, this signal is individually programmed as an input or output through the HI08 Data Direction Register. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, the signal is tri-stated. The Wait processing state does not affect the signal state. All inputs are 5 V tolerant. DSP56303 Technical Data, Rev. 11 1-10 Freescale Semiconductor Enhanced Synchronous Serial Interface 0 (ESSI0) 1.8 Enhanced Synchronous Serial Interface 0 (ESSI0) Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the serial peripheral interface (SPI). Table 1-12. Signal Name Type SC00 Input or Output PC0 Input or Output SC01 Input/Output PC1 Input or Output SC02 Input/Output PC2 Input or Output SCK0 Input/Output Enhanced Synchronous Serial Interface 0 State During Reset1,2 Ignored Input Signal Description Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port C 0—The default configuration following reset is GPIO input PC0. When configured as PC0, signal direction is controlled through the Port C Direction Register. The signal can be configured as ESSI signal SC00 through the Port C Control Register. Ignored Input Serial Control 1—For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for transmitter 2 output or for serial I/O flag 1. Port C 1—The default configuration following reset is GPIO input PC1. When configured as PC1, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SC01 through the Port C Control Register. Ignored Input Serial Control Signal 2—The frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port C 2—The default configuration following reset is GPIO input PC2. When configured as PC2, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SC02 through the Port C Control Register. Ignored Input Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK0 is a clock input or output, used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. PC3 Input or Output SRD0 Input PC4 Input or Output Port C 3—The default configuration following reset is GPIO input PC3. When configured as PC3, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SCK0 through the Port C Control Register. Ignored Input Serial Receive Data—Receives serial data and transfers the data to the ESSI Receive Shift Register. SRD0 is an input when data is received. Port C 4—The default configuration following reset is GPIO input PC4. When configured as PC4, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal SRD0 through the Port C Control Register. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 1-11 Signals/Connections Table 1-12. Signal Name State During Reset1,2 Type STD0 Output PC5 Input or Output Notes: 1. 2. 3. Enhanced Synchronous Serial Interface 0 (Continued) Ignored Input Signal Description Serial Transmit Data—Transmits data from the Serial Transmit Shift Register. STD0 is an output when data is transmitted. Port C 5—The default configuration following reset is GPIO input PC5. When configured as PC5, signal direction is controlled through the Port C Direction Register. The signal can be configured as an ESSI signal STD0 through the Port C Control Register. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, the signal is tri-stated. The Wait processing state does not affect the signal state. All inputs are 5 V tolerant. 1.9 Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-13. Signal Name Type SC10 Input or Output PD0 Input or Output SC11 Input/Output PD1 Input or Output SC12 Input/Output PD2 Input or Output Enhanced Serial Synchronous Interface 1 State During Reset1,2 Ignored Input Signal Description Serial Control 0—For asynchronous mode, this signal is used for the receive clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used either for transmitter 1 output or for serial I/O flag 0. Port D 0—The default configuration following reset is GPIO input PD0. When configured as PD0, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC10 through the Port D Control Register. Ignored Input Serial Control 1—For asynchronous mode, this signal is the receiver frame sync I/O. For synchronous mode, this signal is used either for Transmitter 2 output or for Serial I/O Flag 1. Port D 1—The default configuration following reset is GPIO input PD1. When configured as PD1, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC11 through the Port D Control Register. Ignored Input Serial Control Signal 2—The frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port D 2—The default configuration following reset is GPIO input PD2. When configured as PD2, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SC12 through the Port D Control Register. DSP56303 Technical Data, Rev. 11 1-12 Freescale Semiconductor Enhanced Synchronous Serial Interface 1 (ESSI1) Table 1-13. Signal Name SCK1 Type Input/Output Enhanced Serial Synchronous Interface 1 (Continued) State During Reset1,2 Ignored Input Signal Description Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. Although an external serial clock can be independent of and asynchronous to the DSP system clock, it must exceed the minimum clock cycle time of 6T (that is, the system clock frequency must be at least three times the external ESSI clock frequency). The ESSI needs at least three DSP phases inside each half of the serial clock. PD3 Input or Output SRD1 Input PD4 Input or Output STD1 Output PD5 Input or Output Notes: 1. 2. 3. Port D 3—The default configuration following reset is GPIO input PD3. When configured as PD3, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SCK1 through the Port D Control Register. Ignored Input Serial Receive Data—Receives serial data and transfers the data to the ESSI Receive Shift Register. SRD1 is an input when data is being received. Port D 4—The default configuration following reset is GPIO input PD4. When configured as PD4, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal SRD1 through the Port D Control Register. Ignored Input Serial Transmit Data—Transmits data from the Serial Transmit Shift Register. STD1 is an output when data is being transmitted. Port D 5—The default configuration following reset is GPIO input PD5. When configured as PD5, signal direction is controlled through the Port D Direction Register. The signal can be configured as an ESSI signal STD1 through the Port D Control Register. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, the signal is tri-stated. The Wait processing state does not affect the signal state. All inputs are 5 V tolerant. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 1-13 Signals/Connections 1.10 Serial Communication Interface (SCI) The SCI provides a full duplex port for serial communication with other DSPs, microprocessors, or peripherals such as modems. Table 1-14. Signal Name Type RXD Input PE0 Input or Output TXD Output PE1 Input or Output SCLK Input/Output PE2 Input or Output Notes: 1. 2. 3. Serial Communication Interface State During Reset1,2 Ignored Input Signal Description Serial Receive Data—Receives byte-oriented serial data and transfers it to the SCI Receive Shift Register. Port E 0—The default configuration following reset is GPIO input PE0. When configured as PE0, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal RXD through the Port E Control Register. Ignored Input Serial Transmit Data—Transmits data from the SCI Transmit Data Register. Port E 1—The default configuration following reset is GPIO input PE1. When configured as PE1, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal TXD through the Port E Control Register. Ignored Input Serial Clock—Provides the input or output clock used by the transmitter and/or the receiver. Port E 2—The default configuration following reset is GPIO input PE2. When configured as PE2, signal direction is controlled through the Port E Direction Register. The signal can be configured as an SCI signal SCLK through the Port E Control Register. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, the signal is tri-stated. The Wait processing state does not affect the signal state. All inputs are 5 V tolerant. DSP56303 Technical Data, Rev. 11 1-14 Freescale Semiconductor Timers 1.11 Timers The DSP56303 has three identical and independent timers. Each timer can use internal or external clocking and can either interrupt the DSP56303 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events. Table 1-15. Signal Name TIO0 Type Input or Output Triple Timer Signals State During Signal Description Reset1,2 Ignored Input Timer 0 Schmitt-Trigger Input/Output— When Timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When Timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. TIO0 can be changed to output or configured as a timer I/O through the Timer 0 Control/Status Register (TCSR0). TIO1 Input or Output Ignored Input Timer 1 Schmitt-Trigger Input/Output— When Timer 1 functions as an external event counter or in measurement mode, TIO1 is used as input. When Timer 1 functions in watchdog, timer, or pulse modulation mode, TIO1 is used as output. The default mode after reset is GPIO input. TIO1 can be changed to output or configured as a timer I/O through the Timer 1 Control/Status Register (TCSR1). TIO2 Input or Output Ignored Input Timer 2 Schmitt-Trigger Input/Output— When Timer 2 functions as an external event counter or in measurement mode, TIO2 is used as input. When Timer 2 functions in watchdog, timer, or pulse modulation mode, TIO2 is used as output. The default mode after reset is GPIO input. TIO2 can be changed to output or configured as a timer I/O through the Timer 2 Control/Status Register (TCSR2). Notes: 1. 2. 3. In the Stop state, the signal maintains the last state as follows: • If the last state is input, the signal is an ignored input. • If the last state is output, the signal is tri-stated. The Wait processing state does not affect the signal state. All inputs are 5 V tolerant. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 1-15 Signals/Connections 1.12 JTAG and OnCE Interface The DSP56300 family and in particular the DSP56303 support circuit-board test strategies based on the IEEE® Std. 1149.1™ test access port and boundary scan architecture, the industry standard developed under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The OnCE module provides a means to interface nonintrusively with the DSP56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals. Functions of the OnCE module are provided through the JTAG TAP signals. For programming models, see the chapter on debugging support in the DSP56300 Family Manual. Table 1-16. Signal Name JTAG/OnCE Interface Type State During Reset TCK Input Input Test Clock—A test clock input signal to synchronize the JTAG test logic. TDI Input Input Test Data Input—A test data serial input signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. TDO Output Tri-stated Test Data Output—A test data serial output signal for test instructions and data. TDO is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. TMS Input Input Test Mode Select—Sequences the test controller’s state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. TRST Input Input Test Reset—Initializes the test controller asynchronously. TRST has an internal pull-up resistor. TRST must be asserted after powerup. Input/ Output (open-drain) Input Debug Event—As an input, initiates Debug mode from an external command controller, and, as an open-drain output, acknowledges that the chip has entered Debug mode. As an input, DE causes the DSP56300 core to finish executing the current instruction, save the instruction pipeline information, enter Debug mode, and wait for commands to be entered from the debug serial input line. This signal is asserted as an output for three clock cycles when the chip enters Debug mode as a result of a debug request or as a result of meeting a breakpoint condition. The DE has an internal pull-up resistor. DE Signal Description This signal is not a standard part of the JTAG TAP controller. The signal connects directly to the OnCE module to initiate debug mode directly or to provide a direct external indication that the chip has entered Debug mode. All other interface with the OnCE module must occur through the JTAG port. Note: All inputs are 5 V tolerant. DSP56303 Technical Data, Rev. 11 1-16 Freescale Semiconductor 2 Specifications The DSP56303 is fabricated in high-density CMOS with transistor-transistor logic (TTL) compatible inputs and outputs. 2.1 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. 2.2 Absolute Maximum Ratings Table 2-1. Rating Absolute Maximum Ratings1 Symbol Supply Voltage VCC All input voltages excluding “5 V tolerant” inputs VIN All “5 V tolerant” input voltages2 VIN5 Current drain per pin excluding VCC and GND Operating temperature range Storage temperature Notes: 1. 2. I TJ TSTG Value Unit −0.3 to +4.0 V GND −0.3 to 5.5 V 10 mA GND − 0.3 to VCC + 0.3 −40 to +100 −55 to +150 V °C °C Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip VCC never exceeds 3.5 V. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-1 Specifications 2.3 Thermal Characteristics Table 2-2. Thermal Characteristics Symbol TQFP Value MAP-BGA3 Value MAP-BGA4 Value Unit Junction-to-ambient thermal resistance1 RθJA or θJA 56 57 28 °C/W Junction-to-case thermal resistance2 RθJC or θJC 11 15 — °C/W Thermal characterization parameter ΨJT 7 8 — °C/W Characteristic Notes: 1. 2. 3. 4. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per JEDEC Specification JESD51-3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. These are simulated values. See note 1 for test board conditions. These are simulated values. The test board has two 2-ounce signal layers and two 1-ounce solid ground planes internal to the test board. 2.4 DC Electrical Characteristics Table 2-3. Characteristics DC Electrical Characteristics6 Symbol Min Typ Max Unit VCC 3.0 3.3 3.6 V VIH VIHP 2.0 2.0 — — VCC 5.25 V V VIHX 0.8 × VCC — VCC V VIL VILP VILX –0.3 –0.3 –0.3 — — — 0.8 0.8 0.2 × VCC V V V Input leakage current IIN –10 — 10 µA High impedance (off-state) input current (@ 2.4 V / 0.4 V) ITSI –10 — 10 µA Output high voltage • TTL (IOH = –0.4 mA)5,7 • CMOS (IOH = –10 µA)5 VOH 2.4 VCC – 0.01 — — — — V V Output low voltage • TTL (IOL = 1.6 mA, open-drain pins IOL = 6.7 mA)5,7 • CMOS (IOL = 10 µA) 5 VOL — — — — 0.4 0.01 V V — — — 127 7.5 100 — — — mA mA µA — 1 2.5 mA — — 10 pF Supply voltage Input high voltage • D[0–23], BG, BB, TA • MOD1/IRQ1, RESET, PINIT/NMI and all JTAG/ESSI/SCI/Timer/HI08 pins • EXTAL8 Input low voltage • D[0–23], BG, BB, TA, MOD1/IRQ1, RESET, PINIT • All JTAG/ESSI/SCI/Timer/HI08 pins • EXTAL8 Internal supply current2: • In Normal mode • In Wait mode3 • In Stop mode4 ICCI ICCW ICCS PLL supply current Input capacitance5 CIN DSP56303 Technical Data, Rev. 11 2-2 Freescale Semiconductor AC Electrical Characteristics Table 2-3. DC Electrical Characteristics6 (Continued) Characteristics Notes: 1. 2. 3. 4. 5. 6. 7. 8. Symbol Min Typ Max Unit Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins. Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3 V at TJ = 100°C. In order to obtain these results, all inputs must be terminated (that is, not allowed to float). In order to obtain these results, all inputs that are not disconnected at Stop mode must be terminated (that is, not allowed to float). PLL and XTAL signals are disabled during Stop state. Periodically sampled and not 100 percent tested. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF This characteristic does not apply to XTAL and PCAP. Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize power consumption, the minimum VIHX should be no lower than 0.9 × VCC and the maximum VILX should be no higher than 0.1 × VCC . 2.5 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal transition. DSP56303 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. Note: Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed. 2.5.1 Internal Clocks Table 2-4. Internal Clocks, CLKOUT Expression1, 2 Characteristics Symbol Min Typ Max Internal operation frequency and CLKOUT with PLL enabled f — (Ef × MF)/ (PDF × DF) — Internal operation frequency and CLKOUT with PLL disabled f — Ef/2 — TH — 0.49 × ETC × PDF × DF/MF 0.47 × ETC × PDF × DF/MF ETC — — 0.51 × ETC × PDF × DF/MF 0.53 × ETC × PDF × DF/MF — 0.49 × ETC × PDF × DF/MF 0.47 × ETC × PDF × DF/MF ETC — — ETC × PDF × DF/MF Internal clock and CLKOUT high period • With PLL disabled • With PLL enabled and MF ≤4 • With PLL enabled and MF > 4 Internal clock and CLKOUT low period • With PLL disabled • With PLL enabled and MF ≤4 • TL With PLL enabled and MF > 4 Internal clock and CLKOUT cycle time with PLL enabled TC — — — 0.51 × ETC × PDF × DF/MF 0.53 × ETC × PDF × DF/MF — DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-3 Specifications Table 2-4. Internal Clocks, CLKOUT (Continued) Expression1, 2 Characteristics Symbol Internal clock and CLKOUT cycle time with PLL disabled Instruction cycle time Notes: 1. Typ Max TC — 2 × ETC — ICYC — TC — DF = Division Factor; Ef = External frequency; ETC = External clock cycle; MF = Multiplication Factor; PDF = Predivision Factor; TC = internal clock cycle See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL. 2. 2.5.2 Min External Clock Operation The DSP56303 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; examples are shown in Figure 2-1. EXTAL XTAL R C XTAL1 C Note: Make sure that in the PCTL Register: • XTLD (bit 16) = 0 • If fOSC > 200 kHz, XTLR (bit 15) = 0 Fundamental Frequency Crystal Oscillator Figure 2-1. Suggested Component Values: fOSC = 4 MHz fOSC = 20 MHz R = 680 kΩ ± 10% R = 680 kΩ ± 10% C = 56 pF ± 20% C = 22 pF ± 20% Calculations were done for a 4/20 MHz crystal with the following parameters: • CLof 30/20 pF, • C0 of 7/6 pF, • series resistance of 100/20 Ω, and • drive level of 2 mW. Crystal Oscillator Circuits If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit during bootup by setting XTLD (PCTL Register bit 16 = 1—see the DSP56303 User’s Manual). The external square wave source connects to EXTAL; XTAL is not physically connected to the board or socket. Figure 2-2 shows the relationship between the EXTAL input and the internal clock and CLKOUT. Midpoint EXTAL VILX ETH ETL 2 Note: 3 4 5 ETC VIHX The midpoint is 0.5 (VIHX + VILX). 5 CLKOUT with PLL disabled 7 CLKOUT with PLL enabled 6a 6b Figure 2-2. 7 External Clock Timing DSP56303 Technical Data, Rev. 11 2-4 Freescale Semiconductor AC Electrical Characteristics Table 2-5. Clock Operation 100 MHz No. Characteristics Symbol Min Max Ef 0 100.0 1 Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 3 ns maximum. 2 EXTAL input high1, 2 • With PLL disabled (46.7%–53.3% duty cycle6) • With PLL enabled (42.5%–57.5% duty cycle6) ETH 4.67 ns 4.25 ns ∞ 157.0 µs EXTAL input low 1, 2 • With PLL disabled (46.7%–53.3% duty cycle6) • With PLL enabled (42.5%–57.5% duty cycle6) ETL 4.67 ns 4.25 ns ∞ 157.0 µs EXTAL cycle time2 • With PLL disabled • With PLL enabled ETC 10.00 ns 10.00 ns ∞ 273.1 µs 3 4 5 Internal clock change from EXTAL fall with PLL disabled 4.3 ns 11.0 ns 6 a.Internal clock rising edge from EXTAL rising edge with PLL enabled (MF = 1 or 2 or 4, PDF = 1, Ef > 15 MHz) 3,5 0.0 ns 1.8 ns b. Internal clock falling edge from EXTAL falling edge with PLL enabled (MF ≤4, PDF ≠ 1, Ef / PDF > 15 MHz)3,5 0.0 ns 1.8 ns 20.0 ns 10.00 ns ∞ 8.53 µs 7 Instruction cycle time = ICYC = TC 4 (see Table 2-4) (46.7%–53.3% duty cycle) • With PLL disabled • With PLL enabled Notes: 2.5.3 1. 2. 3. 4. 5. 6. ICYC Measured at 50 percent of the input transition. The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-4) and maximum MF. Periodically sampled and not 100 percent tested. The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF. The skew is not guaranteed for any other MF value. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. Phase Lock Loop (PLL) Characteristics Table 2-6. PLL Characteristics 100 MHz Characteristics Unit Min Max 30 200 MHz (580 × MF) − 100 830 × MF (780 × MF) − 140 1470 × MF pF pF Voltage Controlled Oscillator (VCO) frequency when PLL enabled (MF × Ef × 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP1) • @ MF ≤4 • @ MF > 4 Note: C PCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP) computed using the appropriate expression listed above. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-5 Specifications 2.5.4 Reset, Stop, Mode Select, and Interrupt Timing Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 100 MHz No. 8 9 10 11 12 Characteristics Expression Unit Min Max — — 26.0 ns 50 × ETC 1000 × ETC 75000 × ETC 75000 × ETC 2.5 × TC 2.5 × TC 500.0 10.0 0.75 0.75 25.0 25.0 — — — — — — ns µs ms ms ns ns 3.25 × TC + 2.0 20.25 × TC + 10 34.5 — — 212.5 ns ns TC 5.9 — — 10.0 ns ns 3.25 × TC + 1.0 20.25 × TC + 1.0 33.5 — — 203.5 ns ns Delay from RESET assertion to all pins at reset value3 duration4 Required RESET • Power on, external clock generator, PLL disabled • Power on, external clock generator, PLL enabled • Power on, internal oscillator • During STOP, XTAL disabled (PCTL Bit 16 = 0) • During STOP, XTAL enabled (PCTL Bit 16 = 1) • During normal operation Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 • Minimum • Maximum Synchronous reset set-up time from RESET deassertion to CLKOUT Transition 1 • Minimum • Maximum Synchronous reset deasserted, delay time from the CLKOUT Transition 1 to the first external address output • Minimum • Maximum 13 Mode select setup time 30.0 — ns 14 Mode select hold time 0.0 — ns 15 Minimum edge-triggered interrupt request assertion width 6.6 — ns 16 Minimum edge-triggered interrupt request deassertion width 6.6 — ns 17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid • Caused by first interrupt instruction fetch • Caused by first interrupt instruction execution 4.25 × TC + 2.0 7.25 × TC + 2.0 44.5 74.5 — — ns ns 10 × TC + 5.0 105.0 — ns 18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to generalpurpose transfer output valid caused by first interrupt instruction execution 19 Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts1, 7, 8 (WS + 3.75) × TC – 10.94 — Note 8 ns 20 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts1, 7, 8 (WS + 3.25) × TC – 10.94 — Note 8 ns 21 Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts1, 7, 8 • DRAM for all WS • SRAM WS = 1 • SRAM WS = 2, 3 • SRAM WS ≥ 4 (WS + 3.5) × TC – 10.94 (WS + 3.5) × TC – 10.94 (WS + 3) × TC – 10.94 (WS + 2.5) × TC – 10.94 — — — — Note 8 Note 8 Note 8 Note 8 ns ns ns ns 5.9 TC ns 83.5 — — 252.5 ns ns 22 Synchronous interrupt set-up time from IRQA, IRQB, IRQC, IRQD, NMI assertion to the CLKOUT Transition 2 23 Synchronous interrupt delay time from the CLKOUT Transition 2 to the first external address output valid caused by the first instruction fetch after coming out of Wait Processing state • Minimum • Maximum 8.25 × TC + 1.0 24.75 × TC + 5.0 DSP56303 Technical Data, Rev. 11 2-6 Freescale Semiconductor AC Electrical Characteristics Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 100 MHz No. Characteristics Expression Unit Min Max 5.9 — 24 Duration for IRQA assertion to recover from Stop state 25 Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 3 • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) • PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) PLC × ETC × PDF + (128 K − 1.3 9.1 PLC/2) × TC PLC × ETC × PDF + (23.75 ± 232.5 ns 12.3 ms 0.5) × TC (8.25 ± 0.5) × TC 87.5 97.5 ms Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 3 • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (Operating Mode Register Bit 6 = 0) • PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (Operating Mode Register Bit 6 = 1) • PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) PLC × ETC × PDF + (128K − PLC/2) × TC PLC × ETC × PDF + (20.5 ± 0.5) × TC 5.5 × TC 26 27 28 29 ns ns 13.6 — ms 12.3 — ms 55.0 — ns Interrupt Requests Rate • HI08, ESSI, SCI, Timer • DMA • IRQ, NMI (edge trigger) • IRQ, NMI (level trigger) Maximum: 12 × TC 8 × TC 8 × TC 12 × TC — — — — 120.0 80.0 80.0 120.0 ns ns ns ns DMA Requests Rate • Data read from HI08, ESSI, SCI • Data write to HI08, ESSI, SCI • Timer • IRQ, NMI (edge trigger) Maximum: 6 × TC 7 × TC 2 × TC 3 × TC — — — — 60.0 70.0 20.0 30.0 ns ns ns ns Minimum: 4.25 × TC + 2.0 30.3 — ns Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-7 Specifications Table 2-7. Reset, Stop, Mode Select, and Interrupt Timing6 (Continued) 100 MHz No. Characteristics Expression Unit Min Notes: 1. 2. 3. 4. 5. 6. 7. 8. Max When fast interrupts are used and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when fast interrupts are used. Long interrupts are recommended for Level-sensitive mode. This timing depends on several settings: • For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. Resetting the Stop delay (Operating Mode Register Bit 6 = 0) provides the proper delay. While Operating Mode Register Bit 6 = 1 can be set, it is not recommended, and these specifications do not guarantee timings for that case. • For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit 17=1), no stabilization delay is required and recovery is minimal (Operating Mode Register Bit 6 setting is ignored). • For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time is defined by the PCTL Bit 17 and Operating Mode Register Bit 6 settings. • For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery ends when the last of these two events occurs. The stop delay counter completes count or PLL lock procedure completion. • PLC value for PLL disable is 0. • The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (that is, for 66 MHz it is 4096/66 MHz = 62 µs). During the stabilization period, TC, TH, and TL is not constant, and their width may vary, so timing may vary as well. Periodically sampled and not 100 percent tested. Value depends on clock source: • For an external clock generator, RESET duration is measured while RESET is asserted, VCC is valid, and the EXTAL input is active and valid. • For an internal oscillator, RESET duration is measured while RESET is asserted and VCC is valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. • When the VCC is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock. V CC = 3.3 V ± 0.3 V; TJ = –40°C to +100°C, CL = 50 pF. WS = number of wait states (measured in clock cycles, number of TC). Use the expression to compute a maximum value. VIH RESET 9 10 8 All Pins Reset Value First Fetch A[0–17] Figure 2-3. Reset Timing DSP56303 Technical Data, Rev. 11 2-8 Freescale Semiconductor AC Electrical Characteristics CLKOUT 11 RESET 12 A[0–17] Figure 2-4. Synchronous Reset Timing First Interrupt Instruction Execution/Fetch A[0–17] RD 20 WR 21 IRQA, IRQB, IRQC, IRQD, NMI 17 19 a) First Interrupt Instruction Execution General Purpose I/O 18 IRQA, IRQB, IRQC, IRQD, NMI b) General-Purpose I/O Figure 2-5. External Fast Interrupt Timing DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-9 Specifications IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI 16 Figure 2-6. External Interrupt Timing (Negative Edge-Triggered) CLKOUT IRQA, IRQB, IRQC, IRQD, NMI 22 23 A[0–17] Figure 2-7. Synchronous Interrupt from Wait State Timing VIH RESET 13 14 VIH MODA, MODB, MODC, MODD, PINIT VIH IRQA, IRQB, IRQC, IRQD, NMI VIL Figure 2-8. VIL Operating Mode Select Timing DSP56303 Technical Data, Rev. 11 2-10 Freescale Semiconductor AC Electrical Characteristics 24 IRQA 25 First Instruction Fetch A[0–17] Figure 2-9. Recovery from Stop State Using IRQA 26 IRQA 25 First IRQA Interrupt Instruction Fetch A[0–17] Figure 2-10. Recovery from Stop State Using IRQA Interrupt Service DMA Source Address A[0–17] RD WR 29 IRQA, IRQB, IRQC, IRQD, NMI Figure 2-11. First Interrupt Instruction Execution External Memory Access (DMA Source) Timing DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-11 Specifications 2.5.5 External Memory Expansion Port (Port A) 2.5.5.1 SRAM Timing Table 2-8. No. 100 101 102 103 Characteristics SRAM Read and Write Accesses Symbol Address valid and AA assertion pulse width2 Address and AA valid to WR assertion tRC , tWC tAS WR assertion pulse width tWP WR deassertion to address not valid tWR Expression1 100 MHz Unit Min Max 16.0 — ns 56.0 — ns 106.0 — ns 0.5 — ns 5.5 — ns 10.5 — ns 1.5 × TC −4.0 [WS = 1] WS × TC −4.0 [2 ≤WS ≤3] (WS − 0.5) × TC − 4.0 [WS ≥ 4] 11.0 — ns 16.0 — ns 31.0 — ns 0.25 × TC − 2.0 [1 ≤WS ≤3] 1.25 × TC − 4.0 [4 ≤WS ≤7] 2.25 × TC − 4.0 [WS ≥ 8] 0.5 — ns 8.5 — ns 18.5 — ns (WS + 1) × TC −4.0 [1 ≤WS ≤3] (WS + 2) × TC −4.0 [4 ≤WS ≤7] (WS + 3) × TC −4.0 [WS ≥ 8] 0.25 × TC − 2.0 [WS = 1] 0.75 × TC − 2.0 [2 ≤WS ≤3] 1.25 × TC − 2.0 [WS ≥ 4] tAA, tAC (WS + 0.75) × TC − 5.0 [WS ≥ 1] — 12.5 ns RD assertion to input data valid tOE (WS + 0.25) × TC – 5.0 [WS ≥ 1] — 7.5 ns 106 RD deassertion to data not valid (data hold time) tOHZ 0.0 — ns 107 Address valid to WR deassertion2 tAW (WS + 0.75) × TC − 4.0 [WS ≥ 1] 13.5 — ns 108 Data valid to WR deassertion (data setup time) tDS (tDW ) (WS −0.25) × TC − 3.0 [WS ≥ 1] 4.5 — ns 109 Data hold time from WR deassertion tDH 0.25 × TC − 2.0 [1 ≤WS ≤3] 1.25 × TC − 2.0 [4 ≤WS ≤7] 2.25 × TC − 2.0 [WS ≥ 8] 0.5 — ns 10.5 — ns 20.5 — ns 3.8 — ns –1.2 — ns –6.2 — ns 104 Address and AA valid to input data valid 105 110 WR assertion to data active — 0.75 × TC −3.7 [WS = 1] 0.25 × TC – 3.7 [2 ≤WS ≤3] –0.25 × TC −3.7 [WS ≥ 4] DSP56303 Technical Data, Rev. 11 2-12 Freescale Semiconductor AC Electrical Characteristics Table 2-8. No. 111 112 113 114 SRAM Read and Write Accesses (Continued) Characteristics Symbol WR deassertion to data high impedance — Previous RD deassertion to data active (write) RD deassertion time WR deassertion time — — — Expression1 100 MHz Unit Min Max 0.25 × TC + 0.2 [1 ≤WS ≤3] 1.25 × TC + 0.2 [4 ≤WS ≤7] 2.25 × TC + 0.2 [WS > 8] — 2.7 ns — 12.7 ns — 22.7 ns 1.25 × TC – 4.0 [1 ≤WS ≤3] 2.25 × TC – 4.0 [4 ≤WS ≤7] 3.25 × TC – 4.0 [WS > 8] 8.5 — ns 18.5 — ns 28.5 — ns 3.5 — ns 13.5 — ns 23.5 — ns 1.0 — ns 6.0 — ns 21.0 — ns 31.0 — ns 1.0 — ns 0.75 × TC − 4.0 [1 ≤WS ≤3] 1.75 × TC − 4.0 [4 ≤WS ≤7] 2.75 × TC − 4.0 [WS ≥ 8] 0.5 × TC −4.0 [WS = 1] TC −4.0 [2 ≤WS ≤3] 2.5 × TC −4.0 [4 ≤WS ≤7] 3.5 × TC −4.0 [WS ≥ 8] 115 Address valid to RD assertion — 0.5 × TC −4.0 116 RD assertion pulse width — (WS + 0.25) × TC −4.0 8.5 — ns 117 RD deassertion to address not valid — 0.25 × TC −2.0 [1 ≤WS ≤3] 1.25 × TC − 2.0 [4 ≤WS ≤7] 2.25 × TC − 2.0 [WS ≥ 8] 0.5 — ns 10.5 — ns 20.5 — ns 118 TA setup before RD or WR deassertion4 — 0.25 × TC + 2.0 4.5 — ns 119 TA hold after RD or WR deassertion — — 0 — ns Notes: 1. 2. 3. 4. 5. WS is the number of wait states specified in the BCR. An expression is used to compute the number listed as the minimum or maximum value, as appropriate. Timings 100, 107 are guaranteed by design, not tested. All timings for 100 MHz are measured from 0.5 × Vcc to 0.5 × Vcc. Timing 118 is relative to the deassertion edge of RD or WR even if TA remains asserted. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100°C, CL = 50 pF DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-13 Specifications 100 A[0–17] AA[0–3] 113 117 116 RD 105 106 WR 104 118 119 TA Data In D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-12. SRAM Read Access 100 A[0–17] AA[0–3] 107 101 102 103 WR 114 RD 119 118 TA 108 109 Data Out D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-13. SRAM Write Access DSP56303 Technical Data, Rev. 11 2-14 Freescale Semiconductor AC Electrical Characteristics 2.5.5.2 DRAM Timing The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should be based on the timing in the following tables. For example, the selection guide suggests that four wait states must be used for 100 MHz operation with Page Mode DRAM. However, consulting the appropriate table, a designer can evaluate whether fewer wait states might suffice by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (for example, 95 MHz), using faster DRAM (if it becomes available), and manipulating control factors such as capacitive and resistive load to improve overall system performance. Note: DRAM type (tRAC ns) This figure should be used for primary selection. For exact and detailed timings, see the following tables. 100 80 70 60 Chip frequency 50 40 66 80 120 100 (MHz) 1 Wait states 3 Wait states 2 Wait states 4 Wait states Figure 2-14. DRAM Page Mode Wait State Selection Guide DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-15 Specifications Table 2-9. No. 131 DRAM Page Mode Timings, Three Wait States1,2,3 Characteristics Symbol Page mode cycle time for two consecutive accesses of the same direction Expression4 100 MHz Unit Min Max 4 × TC 40.0 — ns Page mode cycle time for mixed (read and write) accesses tPC 3.5 × TC 35.0 — ns 132 CAS assertion to data valid (read) tCAC 2 × TC − 5.7 — 14.3 ns 133 Column address valid to data valid (read) tAA 3 × TC − 5.7 — 24.3 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 2.5 × TC − 4.0 21.0 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 4.5 × TC − 4.0 41.0 — ns 137 CAS assertion pulse width tCAS 2 × TC − 4.0 16.0 — ns — 4.75 × TC − 6.0 6.75 × TC − 6.0 — 41.5 61.5 — — — — ns ns 5 Last CAS deassertion to RAS assertion • BRW[1–0] = 00, 01—not applicable • BRW[1–0] = 10 • BRW[1–0] = 11 tCRP 139 CAS deassertion pulse width tCP 1.5 × TC − 4.0 11.0 — ns 140 Column address valid to CAS assertion tASC TC −4.0 6.0 — ns 141 CAS assertion to column address not valid tCAH 2.5 × TC − 4.0 21.0 — ns 142 Last column address valid to RAS deassertion tRAL 4 × TC − 4.0 36.0 — ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC − 4.0 8.5 — ns 144 CAS deassertion to WR assertion tRCH 0.75 × TC − 4.0 3.5 — ns 145 CAS assertion to WR deassertion tWCH 2.25 × TC − 4.2 18.3 — ns 146 WR assertion pulse width tWP 3.5 × TC − 4.5 30.5 — ns 147 Last WR assertion to RAS deassertion tRWL 3.75 × TC − 4.3 33.2 — ns 148 WR assertion to CAS deassertion tCWL 3.25 × TC − 4.3 28.2 — ns 149 Data valid to CAS assertion (write) tDS 0.5 × TC – 4.5 0.5 — ns 150 CAS assertion to data not valid (write) tDH 2.5 × TC − 4.0 21.0 — ns 151 WR assertion to CAS assertion tWCS 1.25 × TC − 4.3 8.2 — ns 152 Last RD assertion to RAS deassertion tROH 3.5 × TC − 4.0 31.0 — ns 153 RD assertion to data valid tGA 2.5 × TC − 5.7 — 19.3 ns 0.0 — ns 0.75 × TC – 1.5 6.0 — ns 0.25 × TC — 2.5 ns 138 valid6 154 RD deassertion to data not 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6. tGZ The number of wait states for Page mode access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. The asynchronous delays specified in the expressions are valid for the DSP56303. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 4 × TC for read-after-read or write-after-write sequences). An expression is used to compute the number listed as the minimum or maximum value listed, as appropriate. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of pageaccess. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ . DSP56303 Technical Data, Rev. 11 2-16 Freescale Semiconductor AC Electrical Characteristics DRAM Page Mode Timings, Four Wait States1,2,3 Table 2-10. No. 131 Characteristics Symbol Page mode cycle time for two consecutive accesses of the same direction Expression4 100 MHz Unit Min Max 5 × TC 50.0 — ns Page mode cycle time for mixed (read and write) accesses tPC 4.5 × TC 45.0 — ns 132 CAS assertion to data valid (read) tCAC 2.75 × TC − 5.7 — 21.8 ns 133 Column address valid to data valid (read) tAA 3.75 × TC − 5.7 — 31.8 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 3.5 × TC − 4.0 31.0 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 6 × TC − 4.0 56.0 — ns 137 CAS assertion pulse width tCAS 2.5 × TC − 4.0 21.0 — ns — 5.25 × TC − 6.0 7.25 × TC − 6.0 — 46.5 66.5 — — — — ns ns 5 Last CAS deassertion to RAS assertion • BRW[1–0] = 00, 01—Not applicable • BRW[1–0] = 10 • BRW[1–0] = 11 tCRP 139 CAS deassertion pulse width tCP 2 × TC − 4.0 16.0 — ns 140 Column address valid to CAS assertion tASC TC −4.0 6.0 — ns 141 CAS assertion to column address not valid tCAH 3.5 × TC − 4.0 31.0 — ns 142 Last column address valid to RAS deassertion tRAL 5 × TC − 4.0 46.0 — ns 143 WR deassertion to CAS assertion tRCS 1.25 × TC − 4.0 8.5 — ns 144 CAS deassertion to WR assertion tRCH 1.25 × TC – 3.7 8.8 — ns 145 CAS assertion to WR deassertion tWCH 3.25 × TC − 4.2 28.3 — ns 146 WR assertion pulse width tWP 4.5 × TC − 4.5 40.5 — ns 147 Last WR assertion to RAS deassertion tRWL 4.75 × TC −4.3 43.2 — ns 148 WR assertion to CAS deassertion tCWL 3.75 × TC − 4.3 33.2 — ns 149 Data valid to CAS assertion (write) tDS 0.5 × TC – 4.5 0.5 — ns 150 CAS assertion to data not valid (write) tDH 3.5 × TC − 4.0 31.0 — ns 151 WR assertion to CAS assertion tWCS 1.25 × TC − 4.3 8.2 — ns 152 Last RD assertion to RAS deassertion tROH 4.5 × TC − 4.0 41.0 — ns 153 RD assertion to data valid tGA 3.25 × TC − 5.7 — 26.8 ns 0.0 — ns 0.75 × TC – 1.5 6.0 — ns 0.25 × TC — 2.5 ns 138 valid6 154 RD deassertion to data not 155 WR assertion to data active 156 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. 6. tGZ The number of wait states for Page mode access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. The asynchronous delays specified in the expressions are valid for the DSP56303. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 3 × TC for read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum value listed, as appropriate. BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ . DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-17 Specifications RAS 136 131 135 CAS 137 139 138 140 141 A[0–17] Column Address Column Address Row Add 142 151 Last Column Address 144 145 147 WR 146 RD 148 155 156 150 149 D[0–23] Data Out Figure 2-15. Data Out Data Out DRAM Page Mode Write Accesses RAS 136 131 135 CAS 137 139 140 A[0–17] Row Add Column Address 138 141 142 Last Column Address Column Address 143 WR 132 133 152 153 RD 134 154 D[0–23] Data In Figure 2-16. Data In Data In DRAM Page Mode Read Accesses DSP56303 Technical Data, Rev. 11 2-18 Freescale Semiconductor AC Electrical Characteristics DRAM Type (tRAC ns) Note: This figure should be used for primary selection. For exact and detailed timings, see the following tables. 100 80 70 60 50 66 40 No. 100 120 4 Wait States 11 Wait States 8 Wait States 15 Wait States Figure 2-17. Table 2-11. 80 Chip Frequency (MHz) DRAM Out-of-Page Wait State Selection Guide DRAM Out-of-Page and Refresh Timings, Eleven Wait States1,2 Characteristics Symbol Expression3 100 MHz Unit Min Max 157 Random read or write cycle time tRC 12 × TC 120.0 — ns 158 RAS assertion to data valid (read) tRAC 6.25 × TC − 7.0 — 55.5 ns 159 CAS assertion to data valid (read) tCAC 3.75 × TC − 7.0 — 30.5 ns 160 Column address valid to data valid (read) tAA 4.5 × TC − 7.0 — 38.0 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 162 RAS deassertion to RAS assertion tRP 4.25 × TC − 4.0 38.5 — ns 163 RAS assertion pulse width tRAS 7.75 × TC − 4.0 73.5 — ns 164 CAS assertion to RAS deassertion tRSH 5.25 × TC − 4.0 48.5 — ns 165 RAS assertion to CAS deassertion tCSH 6.25 × TC − 4.0 58.5 — ns 166 CAS assertion pulse width tCAS 3.75 × TC − 4.0 33.5 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × TC ± 4.0 21.0 29.0 ns 168 RAS assertion to column address valid tRAD 1.75 × TC ± 4.0 13.5 21.5 ns 169 CAS deassertion to RAS assertion tCRP 5.75 × TC − 4.0 53.5 — ns 170 CAS deassertion pulse width tCP 4.25 × TC – 6.0 36.5 — ns 171 Row address valid to RAS assertion tASR 4.25 × TC − 4.0 38.5 — ns DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-19 Specifications Table 2-11. No. DRAM Out-of-Page and Refresh Timings, Eleven Wait States1,2 (Continued) Characteristics Symbol Expression3 100 MHz Unit Min Max 172 RAS assertion to row address not valid tRAH 1.75 × TC − 4.0 13.5 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 3.5 — ns 174 CAS assertion to column address not valid tCAH 5.25 × TC − 4.0 48.5 — ns 175 RAS assertion to column address not valid tAR 7.75 × TC − 4.0 73.5 — ns 176 Column address valid to RAS deassertion tRAL 6 × TC − 4.0 56.0 — ns 177 WR deassertion to CAS assertion tRCS 3.0 × TC − 4.0 26.0 — ns tRCH 1.75 × TC – 3.7 13.8 — ns tRRH 0.25 × TC − 2.0 0.5 — ns 178 4 CAS deassertion to WR assertion WR4 179 RAS deassertion to assertion 180 CAS assertion to WR deassertion tWCH 5 × TC − 4.2 45.8 — ns 181 RAS assertion to WR deassertion tWCR 7.5 × TC − 4.2 70.8 — ns 182 WR assertion pulse width tWP 11.5 × TC − 4.5 110.5 — ns 183 WR assertion to RAS deassertion tRWL 11.75 × TC −4.3 113.2 — ns 184 WR assertion to CAS deassertion tCWL 10.25 × TC −4.3 98.2 — ns 185 Data valid to CAS assertion (write) tDS 5.75 × TC − 4.0 53.5 — ns 186 CAS assertion to data not valid (write) tDH 5.25 × TC − 4.0 48.5 — ns 187 RAS assertion to data not valid (write) tDHR 7.75 × TC − 4.0 73.5 — ns 188 WR assertion to CAS assertion tWCS 6.5 × TC − 4.3 60.7 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × TC − 4.0 11.0 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 2.75 × TC − 4.0 23.5 — ns 191 RD assertion to RAS deassertion tROH 11.5 × TC − 4.0 111.0 — ns 192 RD assertion to data valid tGA 10 × TC −7.0 — 93.0 ns 0.0 — ns 0.75 × TC – 1.5 6.0 — ns 0.25 × TC — 2.5 ns 5 193 RD deassertion to data not valid 194 WR assertion to data active 195 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. tGZ The number of wait states for an out-of-page access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±) . Either tRCH or tRRH must be satisfied for read cycles. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ . DSP56303 Technical Data, Rev. 11 2-20 Freescale Semiconductor AC Electrical Characteristics Table 2-12. No. DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1,2 Characteristics Symbol Expression3 100 MHz Unit Min Max 157 Random read or write cycle time tRC 16 × TC 160.0 — ns 158 RAS assertion to data valid (read) tRAC 8.25 × TC − 5.7 — 76.8 ns 159 CAS assertion to data valid (read) tCAC 4.75 × TC − 5.7 — 41.8 ns 160 Column address valid to data valid (read) tAA 5.5 × TC − 5.7 — 49.3 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 0.0 — ns 162 RAS deassertion to RAS assertion tRP 6.25 × TC − 4.0 58.5 — ns 163 RAS assertion pulse width tRAS 9.75 × TC − 4.0 93.5 — ns 164 CAS assertion to RAS deassertion tRSH 6.25 × TC − 4.0 58.5 — ns 165 RAS assertion to CAS deassertion tCSH 8.25 × TC − 4.0 78.5 — ns 166 CAS assertion pulse width tCAS 4.75 × TC − 4.0 43.5 — ns 167 RAS assertion to CAS assertion tRCD 3.5 × TC ± 2 33.0 37.0 ns 168 RAS assertion to column address valid tRAD 2.75 × TC ± 2 25.5 29.5 ns 169 CAS deassertion to RAS assertion tCRP 7.75 × TC − 4.0 73.5 — ns 170 CAS deassertion pulse width tCP 6.25 × TC – 6.0 56.5 — ns 171 Row address valid to RAS assertion tASR 6.25 × TC − 4.0 58.5 — ns 172 RAS assertion to row address not valid tRAH 2.75 × TC − 4.0 23.5 — ns 173 Column address valid to CAS assertion tASC 0.75 × TC − 4.0 3.5 — ns 174 CAS assertion to column address not valid tCAH 6.25 × TC − 4.0 58.5 — ns 175 RAS assertion to column address not valid tAR 9.75 × TC − 4.0 93.5 — ns 176 Column address valid to RAS deassertion tRAL 7 × TC − 4.0 66.0 — ns 177 WR deassertion to CAS assertion tRCS 5 × TC − 3.8 46.2 — ns 178 CAS deassertion to WR4 assertion tRCH 1.75 × TC – 3.7 13.8 — ns 4 179 RAS deassertion to WR assertion tRRH 0.25 × TC − 2.0 0.5 — ns 180 CAS assertion to WR deassertion tWCH 6 × TC − 4.2 55.8 — ns 181 RAS assertion to WR deassertion tWCR 9.5 × TC − 4.2 90.8 — ns 182 WR assertion pulse width tWP 15.5 × TC − 4.5 150.5 — ns 183 WR assertion to RAS deassertion tRWL 15.75 × TC −4.3 153.2 — ns 184 WR assertion to CAS deassertion tCWL 14.25 × TC −4.3 138.2 — ns 185 Data valid to CAS assertion (write) tDS 8.75 × TC − 4.0 83.5 — ns 186 CAS assertion to data not valid (write) tDH 6.25 × TC − 4.0 58.5 — ns 187 RAS assertion to data not valid (write) tDHR 9.75 × TC − 4.0 93.5 — ns 188 WR assertion to CAS assertion tWCS 9.5 × TC − 4.3 90.7 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × TC − 4.0 11.0 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 4.75 × TC − 4.0 43.5 — ns 191 RD assertion to RAS deassertion tROH 15.5 × TC − 4.0 151.0 — ns 192 RD assertion to data valid tGA 14 × TC −5.7 — 134.3 ns 0.0 — ns 0.75 × TC – 1.5 6.0 — ns 0.25 × TC — 2.5 ns valid5 193 RD deassertion to data not 194 WR assertion to data active 195 WR deassertion to data high impedance Notes: 1. 2. 3. 4. 5. tGZ The number of wait states for an out-of-page access is specified in the DRAM Control Register. The refresh period is specified in the DRAM Control Register. Use the expression to compute the maximum or minimum value listed (or both if the expression includes ±) . Either tRCH or tRRH must be satisfied for read cycles. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ . DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-21 Specifications 157 163 162 162 165 RAS 167 164 169 168 170 166 CAS 171 173 174 175 A[0–17] Row Address Column Address 172 176 177 179 191 WR 178 160 159 RD 193 158 192 161 Data In D[0–23] Figure 2-18. DRAM Out-of-Page Read Access DSP56303 Technical Data, Rev. 11 2-22 Freescale Semiconductor AC Electrical Characteristics 157 162 163 162 165 RAS 167 169 164 168 170 166 CAS 173 171 174 172 176 Row Address A[0–17] Column Address 181 175 188 180 182 WR 184 183 RD 187 186 185 195 194 D[0–23] Data Out Figure 2-19. DRAM Out-of-Page Write Access 157 162 162 163 RAS 190 170 165 189 CAS 177 WR Figure 2-20. DRAM Refresh Access DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-23 Specifications 2.5.5.3 Synchronous Timings Table 2-13. No. 198 199 External Bus Synchronous Timings1,2 Expression3,4,5 Characteristics CLKOUT high to address, and AA valid6 CLKOUT high to address, and AA invalid 6 100 MHz Unit Min Max 0.25 × TC + 4.0 — 6.5 ns 0.25 × TC 2.5 — ns 200 TA valid to CLKOUT high (set-up time) 4.0 — ns 201 CLKOUT high to TA invalid (hold time) 0.0 — ns 202 CLKOUT high to data out active 0.25 × TC 2.5 — ns 203 CLKOUT high to data out valid 0.25 × TC + 4.0 — 6.5 ns 204 CLKOUT high to data out invalid 0.25 × TC 2.5 — ns 205 CLKOUT high to data out high impedance 0.25 × TC — 2.5 ns 206 Data in valid to CLKOUT high (set-up) 4.0 — ns 207 CLKOUT high to data in invalid (hold) 0.0 — ns 6.7 10.0 ns 0.0 4.0 ns 5.0 9.3 ns 0.0 4.3 ns 0.0 3.8 ns 208 CLKOUT high to RD assertion 209 CLKOUT high to RD deassertion 210 CLKOUT high to WR assertion2 211 Notes: maximum: 0.75 × TC + 2.5 maximum: 0.5 × TC + 4.3 for WS = 1 or WS ≥ 4 for 2 ≤WS ≤3 CLKOUT high to WR deassertion 1. 2. 3. 4. 5. 6. Use external bus synchronous timings only for reference to the clock and not for relative timings. Synchronous Bus Arbitration is not recommended. Use Asynchronous mode whenever possible. WS is the number of wait states specified in the BCR. If WS > 1, WR assertion refers to the next rising edge of CLKOUT. Use the expression to compute the maximum or minimum value listed, as appropriate. For timing 210, the minimum is an absolute value. T198 and T199 are valid for Address Trace mode if the ATE bit in the Operating Mode Register is set. when this mode is enabled, use the status of BR (See T212) to determine whether the access referenced by A[0–17] is internal or external. DSP56303 Technical Data, Rev. 11 2-24 Freescale Semiconductor AC Electrical Characteristics 198 CLKOUT A[0–17] AA[0–3] 199 201 200 TA 211 WR 210 205 203 204 D[0–23] Data Out 208 202 209 RD 207 206 D[0–23] Data In Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-21. Synchronous Bus Timings 1 WS (BCR Controlled) CLKOUT A[0–17] AA[0–3] 199 198 201 201 200 TA 200 211 WR 210 205 203 204 Data Out D[0–23] 202 208 209 RD 207 206 Data In D[0–23] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-22. Synchronous Bus Timings 2 WS (TA Controlled) DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-25 Specifications 2.5.5.4 Arbitration Timings Table 2-14. No. Arbitration Bus Timings1 Expression2 Characteristics 100 MHz Unit Min Max 212 CLKOUT high to BR assertion/deassertion3 0.0 4.0 ns 213 BG asserted/deasserted to CLKOUT high (setup) 4.0 — ns 214 CLKOUT high to BG deasserted/asserted (hold) 0.0 — ns 215 BB deassertion to CLKOUT high (input set-up) 4.0 — ns 216 CLKOUT high to BB assertion (input hold) 0.0 — ns 217 CLKOUT high to BB assertion (output) 0.0 4.0 ns 218 CLKOUT high to BB deassertion (output) 0.0 4.0 ns 219 BB high to BB high impedance (output) — 4.5 ns 220 CLKOUT high to address and controls active 0.25 × TC 2.5 — ns 221 CLKOUT high to address and controls high impedance 0.75 × TC — 7.5 ns 222 CLKOUT high to AA active 0.25 × TC 2.5 — ns 223 CLKOUT high to AA deassertion maximum: 0.25 × TC + 4.0 2.0 6.5 ns 224 CLKOUT high to AA high impedance 0.75 × TC — 7.5 ns Notes: 1. 2. 3. Synchronous bus arbitration is not recommended. Use Asynchronous mode whenever possible. An expression is used to compute the maximum or minimum value listed, as appropriate. For timing 223, the minimum is an absolute value. T212 is valid for Address Trace mode when the ATE bit in the Operating Mode Register is set. BR is deasserted for internal accesses and asserted for external accesses. DSP56303 Technical Data, Rev. 11 2-26 Freescale Semiconductor AC Electrical Characteristics CLKOUT BR 214 212 213 BG 216 215 217 BB 220 A[0–17] RD, WR 222 AA[0–3] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-23. Bus Acquisition Timings CLKOUT BR 214 212 213 BG 219 218 BB 221 A[0–17] RD, WR 224 223 AA[0–3] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-24. Bus Release Timings Case 1 (BRT Bit in Operating Mode Register Cleared) DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-27 Specifications CLKOUT 212 BR 214 213 BG 219 218 BB 221 A[0–17] RD, WR 224 223 AA[0–3] Note: Address lines A[0–17] hold their state after a read or write operation. AA[0–3] do not hold their state after a read or write operation. Figure 2-25. Bus Release Timings Case 2 (BRT Bit in Operating Mode Register Set) DSP56303 Technical Data, Rev. 11 2-28 Freescale Semiconductor AC Electrical Characteristics 2.5.5.5 Asynchronous Bus Arbitration Timings Asynchronous Bus Timings1, 2 Table 2-15. No. 250 251 Notes: Expression3 Characteristics BB assertion window from BG input deassertion5 Delay from BB assertion to BG assertion 1. 2. 3. 4. 5. 5 100 MHz4 Unit Min Max 2.5 × Tc + 5 — 30 ns 2 × Tc + 5 25 — ns Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode. If Asynchronous Arbitration mode is active, none of the timings in Table 2-14 is required. An expression is used to compute the maximum or minimum value listed, as appropriate. Asynchronous Arbitration mode is recommended for operation at 100 MHz. In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in the non-overlap manner shown in Figure 2-26. BG1 BB 250 BG2 251 250+251 Figure 2-26. Asynchronous Bus Arbitration Timing The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this delay, a DSP56300 part may assume mastership and assert BB, for some time after BG is deasserted. This is the reason for timing 250. Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other DSP56300 components that are potential masters on the same bus. If BG input is asserted before that time, and BG is asserted and BB is deasserted, another DSP56300 component may assume mastership at the same time. Therefore, some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that overlaps are avoided. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-29 Specifications 2.5.6 Host Interface Timing Table 2-16. Host Interface Timings1,2,12 Characteristic10 No. 317 Read data strobe assertion width5 HACK assertion width 318 Read data strobe deassertion width5 HACK deassertion width 319 Read data strobe deassertion width5 after “Last Data Register” reads8,11, or between two consecutive CVR, ICR, or ISR reads3 HACK deassertion width after “Last Data Register” reads8,11 320 Write data strobe assertion width6 321 Write data strobe deassertion width8 HACK write deassertion width • after ICR, CVR and “Last Data Register” writes • 100 MHz Expression TC + 9.9 2.5 × TC + 6.6 2.5 × TC + 6.6 after IVR writes, or after TXH:TXM:TXL writes (with HLEND= 0), or after TXL:TXM:TXH writes (with HLEND = 1) Unit Min Max 19.9 — ns 9.9 — ns 31.6 — ns 13.2 — ns 31.8 — ns 16.5 — ns 322 HAS assertion width 9.9 — ns 323 HAS deassertion to data strobe assertion4 0.0 — ns 324 Host data input setup time before write data strobe deassertion6 9.9 — ns 325 Host data input hold time after write data strobe deassertion6 3.3 — ns 326 Read data strobe assertion to output data active from high impedance5 HACK assertion to output data active from high impedance 3.3 — ns 327 Read data strobe assertion to output data valid5 HACK assertion to output data valid — 24.5 ns 328 Read data strobe deassertion to output data high impedance5 HACK deassertion to output data high impedance — 9.9 ns 329 Output data hold time after read data strobe deassertion5 Output data hold time after HACK deassertion 3.3 — ns 330 HCS assertion to read data strobe deassertion5 19.9 — ns 331 HCS assertion to write data strobe deassertion6 9.9 — ns 332 HCS assertion to output data valid — 19.3 ns 333 HCS hold time after data strobe deassertion4 0.0 — ns 334 Address (HAD[0–7]) setup time before HAS deassertion (HMUX=1) 4.6 — ns 335 Address (HAD[0–7]) hold time after HAS deassertion (HMUX=1) 3.3 — ns 336 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W setup time before data strobe assertion4 • Read • Write 0 4.6 — — ns ns 3.3 — ns TC + 9.9 337 HA[8–10] (HMUX=1), HA[0–2] (HMUX=0), HR/W hold time after data strobe deassertion4 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read5, 7, 8 TC + 5.3 15.3 — ns 339 Delay from write data strobe deassertion to host request assertion for “Last Data Register” write6, 7, 8 1.5 × TC + 5.3 20.3 — ns DSP56303 Technical Data, Rev. 11 2-30 Freescale Semiconductor AC Electrical Characteristics Table 2-16. Host Interface Timings1,2,12 (Continued) 100 MHz Characteristic10 No. Expression Unit Min Max 340 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD=0) 4, 7, 8 — 19.3 ns 341 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD=1, open drain host request)4, 7, 8, 9 — 300.0 ns Notes: See the Programmer’s Model section in the chapter on the HI08 in the DSP56303 User’s Manual. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. This timing is applicable only if two consecutive reads from one of these registers are executed. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the Single Data Strobe mode. 5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. 6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode. 7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode. 8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the Little Endian mode (HLEND = 1). 9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode. 10. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF 11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal. 12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3 × Tc). 1. 2. 3. 4. 317 318 HACK 328 327 326 329 H[0–7] HREQ Note: The IVR is read only by an MC680xx host processor in non-multiplexed mode. Figure 2-27. Host Interrupt Vector Register (IVR) Read Timing Diagram DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-31 Specifications HA[2–0] 336 337 333 330 HCS 336 337 HRW 317 HDS 318 328 332 319 327 329 326 H[7–0] 338 340 341 HREQ (single host request) HRRQ (double host request) Figure 2-28. Read Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] 336 337 333 330 HCS 317 HRD 318 328 332 319 327 329 326 H[7–0] 340 338 341 HREQ (single host request) HRRQ (double host request) Figure 2-29. Read Timing Diagram, Non-Multiplexed Bus, Double Data Strobe DSP56303 Technical Data, Rev. 11 2-32 Freescale Semiconductor AC Electrical Characteristics HA[2–0] 336 337 333 331 HCS 336 337 HRW 320 HDS 321 324 325 H[7–0] 339 340 341 HREQ (single host request) HTRQ (double host request) Figure 2-30. Write Timing Diagram, Non-Multiplexed Bus, Single Data Strobe HA[2–0] 336 337 333 331 HCS 320 HWR 321 324 325 H[7–0] 340 339 341 HREQ (single host request) HTRQ (double host request) Figure 2-31. Write Timing Diagram, Non-Multiplexed Bus, Double Data Strobe DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-33 Specifications , HA[10–8] 336 322 HAS 337 323 336 337 HRW 317 HDS 334 318 335 319 327 328 329 HAD[7–0] Address Data 326 338 340 341 HREQ (single host request) HRRQ (double host request) Figure 2-32. Read Timing Diagram, Multiplexed Bus, Single Data Strobe HA[10–8] 336 322 HAS 337 323 317 HRD 334 318 335 319 327 328 329 HAD[7–0] Address Data 326 340 HREQ (single host request) HRRQ (double host request) Figure 2-33. 338 341 Read Timing Diagram, Multiplexed Bus, Double Data Strobe DSP56303 Technical Data, Rev. 11 2-34 Freescale Semiconductor AC Electrical Characteristics HA[10–8] 336 322 HAS 337 323 336 337 HRW 320 HDS 334 324 321 335 HAD[7–0] 325 Data Address 340 339 341 HREQ (single host request) HTRQ (double host request) Figure 2-34. Write Timing Diagram, Multiplexed Bus, Single Data Strobe , HA[10–8] 336 322 HAS 337 323 320 HWR 334 324 321 335 HAD[7–0] 325 Data Address 340 339 341 HREQ (single host request) HTRQ (double host request) Figure 2-35. Write Timing Diagram, Multiplexed Bus, Double Data Strobe DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-35 Specifications 2.5.7 SCI Timing Table 2-17. 100 MHz Characteristics1 No. SCI Timings Symbol tSCC2 Expression Unit Min Max 8 × TC 53.3 — ns 400 Synchronous clock cycle 401 Clock low period tSCC/2 − 10.0 16.7 — ns 402 Clock high period tSCC/2 − 10.0 16.7 — ns 403 Output data setup to clock falling edge (internal clock) tSCC /4 + 0.5 × TC −17.0 8.0 — ns 404 Output data hold after clock rising edge (internal clock) tSCC/4 −0.5 × TC 15.0 — ns 405 Input data setup time before clock rising edge (internal clock) tSCC/4 + 0.5 × TC + 25.0 50.0 — ns 406 Input data not valid before clock rising edge (internal clock) tSCC/4 + 0.5 × TC −5.5 — 19.5 ns 407 Clock falling edge to output data valid (external clock) — 32.0 ns 408 Output data hold after clock rising edge (external clock) 18.0 — ns 409 Input data setup time before clock rising edge (external clock) 0.0 — ns 410 Input data hold time after clock rising edge (external clock) 9.0 — ns 411 Asynchronous clock cycle 64 × TC 640.0 — ns 412 Clock low period tACC/2 − 10.0 310.0 — ns 413 Clock high period tACC/2 − 10.0 310.0 — ns 414 Output data setup to clock rising edge (internal clock) tACC/2 − 30.0 290.0 — ns 415 Output data hold after clock rising edge (internal clock) tACC/2 − 30.0 290.0 — ns Notes: 1. 2. 3. 4. TC + 8.0 tACC 3 V CC = 3.3 V ± 0.3 V; TJ = −40°C to +100 °C, CL = 50 pF. tSCC = synchronous clock cycle time (for internal clock, tSCC is determined by the SCI clock control register and TC ). tACC = asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, tACC is determined by the SCI clock control register and TC). An expression is used to compute the number listed as the minimum or maximum value as appropriate. DSP56303 Technical Data, Rev. 11 2-36 Freescale Semiconductor AC Electrical Characteristics 400 402 401 SCLK (Output) 403 404 Data Valid TXD 405 406 Data Valid RXD a) Internal Clock 400 402 401 SCLK (Input) 407 408 TXD Data Valid 409 410 RXD Data Valid b) External Clock Figure 2-36. SCI Synchronous Mode Timing 411 413 412 1X SCLK (Output) 414 TXD 415 Data Valid Figure 2-37. SCI Asynchronous Mode Timing DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-37 Specifications 2.5.8 ESSI0/ESSI1 Timing Table 2-18. Characteristics4, 5, 7 No. ESSI Timings Symbol Expression9 100 MHz Min Max 3 × TC 4 × TC 30.0 40.0 — — Condition5 Unit 430 Clock cycle1 431 Clock high period • For internal clock • For external clock 2 × TC - 10.0 1.5 × TC 10.0 15.0 — — ns ns Clock low period • For internal clock • For external clock 2 × TC −10.0 1.5 × TC 10.0 15.0 — — ns ns 432 tSSICC x ck i ck ns 433 RXC rising edge to FSR out (bit-length) high — — 37.0 22.0 x ck i ck a ns 434 RXC rising edge to FSR out (bit-length) low — — 37.0 22.0 x ck i ck a ns 435 RXC rising edge to FSR out (word-length-relative) high2 — — 39.0 37.0 x ck i ck a ns 436 RXC rising edge to FSR out (word-length-relative) low 2 — — 39.0 37.0 x ck i ck a ns 437 RXC rising edge to FSR out (word-length) high — — 36.0 21.0 x ck i ck a ns 438 RXC rising edge to FSR out (word-length) low — — 37.0 22.0 x ck i ck a ns 439 Data in set-up time before RXC (SCK in Synchronous mode) falling edge 10.0 19.0 — — x ck i ck ns 440 Data in hold time after RXC falling edge 5.0 3.0 — — x ck i ck ns 441 FSR input (bl, wr) 7 high before RXC falling edge2 1.0 23.0 — — x ck i ck a ns 442 FSR input (wl)7 high before RXC falling edge 3.5 23.0 — — x ck i ck a ns 443 FSR input hold time after RXC falling edge 3.0 0.0 — — x ck i ck a ns 444 Flags input set-up before RXC falling edge 5.5 19.0 — — x ck i ck s ns 445 Flags input hold time after RXC falling edge 6.0 0.0 — — x ck i ck s ns 446 TXC rising edge to FST out (bit-length) high — — 29.0 15.0 x ck i ck ns 447 TXC rising edge to FST out (bit-length) low — — 31.0 17.0 x ck i ck ns 448 TXC rising edge to FST out (word-length-relative) high2 — — 31.0 17.0 x ck i ck ns 449 TXC rising edge to FST out (word-length-relative) low2 — — 33.0 19.0 x ck i ck ns 450 TXC rising edge to FST out (word-length) high — — 30.0 16.0 x ck i ck ns 451 TXC rising edge to FST out (word-length) low — — 31.0 17.0 x ck i ck ns 452 TXC rising edge to data out enable from high impedance — — 31.0 17.0 x ck i ck ns DSP56303 Technical Data, Rev. 11 2-38 Freescale Semiconductor AC Electrical Characteristics Table 2-18. ESSI Timings (Continued) Characteristics4, 5, 7 No. Symbol Expression9 100 MHz Min Max Condition5 Unit 453 TXC rising edge to transmitter 0 drive enable assertion — — 34.0 20.0 x ck i ck ns 454 TXC rising edge to data out valid — — 20.08 10.0 x ck i ck ns 455 TXC rising edge to data out high impedance3 — — 31.0 16.0 x ck i ck ns 456 TXC rising edge to Transmitter 0 drive enable deassertion3 — — 34.0 20.0 x ck i ck ns 457 FST input (bl, wr) set-up time before TXC falling edge2 2.0 21.0 — — x ck i ck ns 458 FST input (wl) to data out enable from high impedance — 27.0 — ns 459 FST input (wl) to Transmitter 0 drive enable assertion — 31.0 — ns 460 FST input (wl) set-up time before TXC falling edge 2.5 21.0 — — x ck i ck ns 461 FST input hold time after TXC falling edge 4.0 0.0 — — x ck i ck ns 462 Flag output valid after TXC rising edge — — 32.0 18.0 x ck i ck ns Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. For the internal clock, the external clock cycle is defined by Icyc (see Timing 7) and the ESSI Control Register. The word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform, but spreads from one serial clock before the first bit clock (same as the Bit Length Frame Sync signal) until the one before last bit clock of the first word in the frame. Periodically sampled and not 100 percent tested V CC = 3.3 V ± 0.3 V; TJ = −40°C to +100 °C, CL = 50 pF TXC (SCK Pin) = transmit clock RXC (SC0 or SCK pin) = receive clock FST (SC2 pin) = transmit frame sync FSR (SC1 or SC2 pin) receive frame sync i ck = internal clock x ck = external clock i ck a = internal clock, Asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous mode (synchronous implies that TXC and RXC are the same clock) bl = bit length; wl = word length; wr = word length relative. If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5 × TC). An expression is used to compute the number listed as the minimum or maximum value as appropriate. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-39 Specifications 430 TXC (Input/ Output) 431 432 446 447 FST (Bit) Out 450 451 FST (Word) Out 454 454 452 455 Data Out First Last 459 Transmitter 0 Drive Enable 457 453 456 461 FST (Bit) In 458 461 460 FST (Word) In 462 See Note Flags Out Note: In Network mode, output flag transitions can occur at the start of each time slot within the frame. In Normal mode, the output flag state is asserted for the entire frame period. Figure 2-38. ESSI Transmitter Timing DSP56303 Technical Data, Rev. 11 2-40 Freescale Semiconductor AC Electrical Characteristics 430 431 RXC (Input/ Output) 432 433 434 FSR (Bit) Out 437 438 FSR (Word) Out 440 439 Data In First Bit Last Bit 443 441 FSR (Bit) In 442 443 FSR (Word) In 444 445 Flags In Figure 2-39. ESSI Receiver Timing DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-41 Specifications 2.5.9 Timer Timing Table 2-19. No. Timer Timing1 100 MHz Expression2 Characteristics Unit Min Max 480 TIO Low 2 × TC + 2.0 22.0 — ns 481 TIO High 2 × TC + 2.0 22.0 — ns 482 Timer set-up time from TIO (Input) assertion to CLKOUT rising edge 9.0 10.0 ns 483 Synchronous timer delay time from CLKOUT rising edge to the external memory access address out valid caused by first interrupt instruction execution 10.25 × TC + 1.0 103.5 — ns 484 CLKOUT rising edge to TIO (Output) assertion • Minimum • Maximum 0.5 × TC + 0.5 0.5 × TC + 19.8 5.5 — — 24.8 ns ns CLKOUT rising edge to TIO (Output) deassertion • Minimum • Maximum 0.5 × TC + 0.5 0.5 × TC + 19.8 5.5 — — 24.8 ns ns 485 Notes: 1. 2. VCC = 3.3 V ± 0.3 V; TJ = −40°C to +100 °C, CL = 50 pF. An expression is used to compute the number listed as the minimum or maximum value as appropriate. 480 TIO 481 Figure 2-40. TIO Timer Event Input Restrictions CLKOUT TIO (Input) 482 Address 483 First Interrupt Instruction Execution Figure 2-41. Timer Interrupt Generation CLKOUT TIO (Output) 484 Figure 2-42. 485 External Pulse Generation DSP56303 Technical Data, Rev. 11 2-42 Freescale Semiconductor AC Electrical Characteristics 2.5.10 GPIO Timing Table 2-20. GPIO Timing 100 MHz No. Characteristics Expression Unit Min Max 490 CLKOUT edge to GPIO out valid (GPIO out delay time) — 8.5 ns 491 CLKOUT edge to GPIO out not valid (GPIO out hold time) 0.0 — ns 492 GPIO In valid to CLKOUT edge (GPIO in set-up time) 8.5 — ns 493 CLKOUT edge to GPIO in not valid (GPIO in hold time) 0.0 — ns 494 Fetch to CLKOUT edge before GPIO change 67.5 — ns Note: Minimum: 6.75 × TC VCC = 3.3 V ± 0.3 V; TJ = −40°C to +100 °C, CL = 50 pF CLKOUT (Output) 490 491 GPIO (Output) 492 GPIO (Input) 493 Valid A[0–17] 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of the GPIO data register. Figure 2-43. GPIO Timing DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-43 Specifications 2.5.11 JTAG Timing Table 2-21. JTAG Timing All frequencies No. Characteristics Unit Min Max 500 TCK frequency of operation (1/(TC × 3); maximum 22 MHz) 0.0 22.0 MHz 501 TCK cycle time in Crystal mode 45.0 — ns 502 TCK clock pulse width measured at 1.5 V 20.0 — ns 503 TCK rise and fall times 0.0 3.0 ns 504 Boundary scan input data setup time 5.0 — ns 505 Boundary scan input data hold time 24.0 — ns 506 TCK low to output data valid 0.0 40.0 ns 507 TCK low to output high impedance 0.0 40.0 ns 508 TMS, TDI data setup time 5.0 — ns 509 TMS, TDI data hold time 25.0 — ns 510 TCK low to TDO data valid 0.0 44.0 ns 511 TCK low to TDO high impedance 0.0 44.0 ns 512 TRST assert time 100.0 — ns 513 TRST setup time to TCK low 40.0 — ns Notes: 1. 2. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. 501 502 502 TCK (Input) VIH VM VIL 503 503 Figure 2-44. Test Clock Input Timing Diagram DSP56303 Technical Data, Rev. 11 2-44 Freescale Semiconductor AC Electrical Characteristics TCK (Input) VIH VIL 504 Data Inputs 505 Input Data Valid 506 Data Outputs Output Data Valid 507 Data Outputs 506 Data Outputs Output Data Valid Figure 2-45. TCK (Input) Boundary Scan (JTAG) Timing Diagram VIH VIL 508 TDI TMS (Input) 509 Input Data Valid 510 TDO (Output) Output Data Valid 511 TDO (Output) 510 TDO (Output) Output Data Valid Figure 2-46. Test Access Port Timing Diagram TCK (Input) 513 TRST (Input) 512 Figure 2-47. TRST Timing Diagram DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 2-45 Specifications 2.5.12 OnCE Module TimIng Table 2-22. No. OnCE Module Timing Characteristics Expression Min Max Unit 500 TCK frequency of operation Max 22.0 MHz 0.0 22.0 MHz 514 DE assertion time in order to enter Debug mode 1.5 × TC + 10.0 20.0 — ns 515 Response time when DSP56303 is executing NOP instructions from internal memory 5.5 × TC + 30.0 — 67.0 ns 516 Debug acknowledge assertion time 3 × TC + 5.0 25.0 — ns Note: VCC = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, C L = 50 pF. DE 514 515 Figure 2-48. 516 OnCE—Debug Request DSP56303 Technical Data, Rev. 11 2-46 Freescale Semiconductor 3 Packaging This section includes diagrams of the DSP56303 package pin-outs and tables showing how the signals described in Chapter 1, are allocated for each package. The DSP56303 is available in two package types: • 144-pin Thin Quad Flat Pack (TQFP) • 196-pin Molded Array Process-Ball Grid Array (MAP-BGA) DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-1 Packaging 3.1 TQFP Package Description D7 D8 109 (Top View) 73 D6 D5 D4 D3 GNDD VCCD D2 D1 D0 A17 A16 A15 GNDA VCCA A14 A13 A12 VCC Q GNDQ A11 A10 GNDA VCCA A9 A8 A7 A6 GNDA VCCA A5 A4 A3 A2 GNDA VCCA A1 Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQ GNDQ D20 VCCD GNDD D21 D22 D23 MODD MODC MODB MODA TRST Orientation Mark Notes: DE PINIT SRD0 VCCS GNDS STD0 SC10 SC00 RXD TXD SCLK SCK1 SCK0 V CCQ GNDQ NC HDS HRW HACK HREQ VCCS GNDS TIO2 TIO1 TIO0 HCS HA9 HA8 HAS HAD7 HAD6 HAD5 1 37 SRD1 STD1 SC02 SC01 TDO TDI TCK TMS SC12 SC11 A0 BG AA0 AA1 RD WR GNDC VCCC BB BR TA BCLK BCLK CLKOUT GNDC VCCC VCCQ EXTAL GNDQ XTAL CAS AA2 AA3 NC GNDP1 GNDP PCAP VCCP RESET HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4 Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table 3-2 for detailed information about pin functions and signal names. Figure 3-1. DSP56303 Thin Quad Flat Pack (TQFP), Top View DSP56303 Technical Data, Rev. 11 3-2 Freescale Semiconductor A0 BG 73 A1 VCCA GNDA A2 A3 A4 A5 VCCA GNDA A6 A7 A8 A9 VCCA GNDA A10 A11 GNDQ VCCQ A12 A13 A14 VCCA GNDA A15 A16 A17 D0 D1 D2 VCCD GNDD D3 D4 D5 D6 TQFP Package Description 109 (Bottom View) AA0 AA1 RD WR GNDC VCCC BB BR TA BCLK BCLK CLKOUT GNDC VCCC VCCQ EXTAL GNDQ XTAL CAS AA2 AA3 NC GNDP1 GNDP PCAP VCCP RESET TRST Orientation Mark (on top side) Notes: DE TDO TDI TCK TMS SC12 SC11 SC01 SC02 STD1 SRD1 1 37 HAD5 HAD6 HAD7 HAS HA8 HA9 HCS TIO0 TIO1 TIO2 GNDS VCCS HREQ HACK HRW HDS NC GNDQ VCCQ SCK0 SCK1 SCLK TXD RXD SC00 SC10 STD0 GNDS VCCS SRD0 PINIT HAD0 HAD1 HAD2 HAD3 GNDH VCCH HAD4 D7 D8 VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQ GNDQ D20 VCCD GNDD D21 D22 D23 MODD MODC MODB MODA Because of size constraints in this figure, only one name is shown for multiplexed pins. Refer to Table 3-1 and Table 3-2 for detailed information about pin functions and signal names. Figure 3-2. DSP56303 Thin Quad Flat Pack (TQFP), Bottom View DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-3 Packaging Table 3-1. Pin No. Signal Name DSP56303 TQFP Signal Identification by Pin Number Pin No. Signal Name Pin No. Signal Name 1 SRD1 or PD4 26 GNDS 51 AA2/RAS2 2 STD1 or PD5 27 TIO2 52 CAS 3 SC02 or PC2 28 TIO1 53 XTAL 4 SC01 or PC1 29 TIO0 54 GNDQ 5 DE 30 HCS/HCS, HA10, or PB13 55 EXTAL 6 PINIT/NMI 31 HA2, HA9, or PB10 56 VCCQ 7 SRD0 or PC4 32 HA1, HA8, or PB9 57 VCCC 8 VCCS 33 HA0, HAS/HAS, or PB8 58 GNDC 9 GNDS 34 H7, HAD7, or PB7 59 CLKOUT 10 STD0 or PC5 35 H6, HAD6, or PB6 60 BCLK 11 SC10 or PD0 36 H5, HAD5, or PB5 61 BCLK 12 SC00 or PC0 37 H4, HAD4, or PB4 62 TA 13 RXD or PE0 38 VCCH 63 BR 14 TXD or PE1 39 GNDH 64 BB 15 SCLK or PE2 40 H3, HAD3, or PB3 65 VCCC 16 SCK1 or PD3 41 H2, HAD2, or PB2 66 GNDC 17 SCK0 or PC3 42 H1, HAD1, or PB1 67 WR 18 VCCQ 43 H0, HAD0, or PB0 68 RD 19 GNDQ 44 RESET 69 AA1/RAS1 20 Not Connected (NC), reserved 45 V CCP 70 AA0/RAS0 21 HDS/HDS, HWR/HWR, or PB12 46 PCAP 71 BG 22 HRW, HRD/HRD, or PB11 47 GNDP 72 A0 23 HACK/HACK, HRRQ/HRRQ, or PB15 48 GNDP1 73 A1 24 HREQ/HREQ, HTRQ/HTRQ, or PB14 49 Not Connected (NC), reserved 74 VCCA 25 VCCS 50 AA3/RAS3 75 GNDA DSP56303 Technical Data, Rev. 11 3-4 Freescale Semiconductor TQFP Package Description Table 3-1. Pin No. Signal Name DSP56303 TQFP Signal Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name 76 A2 99 A17 122 D16 77 A3 100 D0 123 D17 78 A4 101 D1 124 D18 79 A5 102 D2 125 D19 80 VCCA 103 VCCD 126 VCCQ 81 GNDA 104 GNDD 127 GNDQ 82 A6 105 D3 128 D20 83 A7 106 D4 129 VCCD 84 A8 107 D5 130 GNDD 85 A9 108 D6 131 D21 86 VCCA 109 D7 132 D22 87 GNDA 110 D8 133 D23 88 A10 111 VCCD 134 MODD/IRQD 89 A11 112 GNDD 135 MODC/IRQC 90 GNDQ 113 D9 136 MODB/IRQB 91 VCCQ 114 D10 137 MODA/IRQA 92 A12 115 D11 138 TRST 93 A13 116 D12 139 TDO 94 A14 117 D13 140 TDI 95 VCCA 118 D14 141 TCK 96 GNDA 119 VCCD 142 TMS 97 A15 120 GNDD 143 SC12 or PD2 98 A16 121 D15 144 SC11 or PD1 Notes: Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted but act as interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some pins have two or more configurable functions; names assigned to these pins indicate the function for a specific configuration. For example, Pin 34 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-5 Packaging Table 3-2. DSP56303 TQFP Signal Identification by Name Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. A0 72 BG 71 D7 109 A1 73 BR 63 D8 110 A10 88 CAS 52 D9 113 A11 89 CLKOUT 59 DE 5 A12 92 D0 100 EXTAL 55 A13 93 D1 101 GNDA 75 A14 94 D10 114 GNDA 81 A15 97 D11 115 GNDA 87 A16 98 D12 116 GNDA 96 A17 99 D13 117 GNDC 58 A2 76 D14 118 GNDC 66 A3 77 D15 121 GNDD 104 A4 78 D16 122 GNDD 112 A5 79 D17 123 GNDD 120 A6 82 D18 124 GNDD 130 A7 83 D19 125 GNDH 39 A8 84 D2 102 GNDP 47 A9 85 D20 128 GNDP1 48 AA0 70 D21 131 GNDQ 19 AA1 69 D22 132 GNDQ 54 AA2 51 D23 133 GNDQ 90 AA3 50 D3 105 GNDQ 127 BB 64 D4 106 GNDS 9 BCLK 60 D5 107 GNDS 26 BCLK 61 D6 108 H0 43 DSP56303 Technical Data, Rev. 11 3-6 Freescale Semiconductor TQFP Package Description Table 3-2. DSP56303 TQFP Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. H1 42 HRD/HRD 22 PB2 41 H2 41 HREQ/HREQ 24 PB3 40 H3 40 HRRQ/HRRQ 23 PB4 37 H4 37 HRW 22 PB5 36 H5 36 HTRQ/HTRQ 24 PB6 35 H6 35 HWR/HWR 21 PB7 34 H7 34 IRQA 137 PB8 33 HA0 33 IRQB 136 PB9 32 HA1 32 IRQC 135 PC0 12 HA10 30 IRQD 134 PC1 4 HA2 31 MODA 137 PC2 3 HA8 32 MODB 136 PC3 17 HA9 31 MODC 135 PC4 7 HACK/HACK 23 MODD 134 PC5 10 HAD0 43 NC 20 PCAP 46 HAD1 42 NMI 6 PD0 11 HAD2 41 NC 49 PD1 144 HAD3 40 PB0 43 PD2 143 HAD4 37 PB1 42 PD3 16 HAD5 36 PB10 31 PD4 1 HAD6 35 PB11 22 PD5 2 HAD7 34 PB12 21 PE0 13 HAS/HAS 33 PB13 30 PE1 14 HCS/HCS 30 PB14 24 PE2 15 HDS/HDS 21 PB15 23 PINIT 6 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-7 Packaging Table 3-2. DSP56303 TQFP Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. RAS0 70 SRD1 1 VCCC 57 RAS1 69 STD0 10 VCCC 65 RAS2 51 STD1 2 VCCD 103 RAS3 50 TA 62 VCCD 111 RD 68 TCK 141 VCCD 119 RESET 44 TDI 140 VCCD 129 RXD 13 TDO 139 VCCH 38 SC00 12 TIO0 29 VCCP 45 SC01 4 TIO1 28 VCCQ 18 SC02 3 TIO2 27 VCCQ 56 SC10 11 TMS 142 VCCQ 91 SC11 144 TRST 138 VCCQ 126 SC12 143 TXD 14 VCCS 8 SCK0 17 VCCA 74 VCCS 25 SCK1 16 VCCA 80 WR 67 SCLK 15 VCCA 86 XTAL 53 SRD0 7 VCCA 95 DSP56303 Technical Data, Rev. 11 3-8 Freescale Semiconductor TQFP Package Mechanical Drawing 3.2 TQFP Package Mechanical Drawing 0.20 T L-M N 4X Pin 1 ident 0.20 T L-M N 4X 36 TIPS 144 109 1 108 4X J1 P J1 M L C L B V 140X B1 V1 View Y 36 View Y 73 Notes: 1. Dimensions and tolerancing per ASME Y14.5, 1994. 2. Dimensions in millimeters. 3. Datums L, M and N to be determined at the seating plane, datum T. 4. Dimensions S and V to be determined at the seating plane, datum T. 5. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.25 per side. Dimensions A and B do include mold mismatch and are determined at datum plane H. 6. Dimension D does not include dambar protrusion. Allowable dambar protrusion shall not cause the D dimension to exceed 0.35. 72 37 N A1 S1 A S View AB C 0.1 T θ2 144X Seating plane θ2 T Plating J F AA C2 — 0.05 R2 θ R1 D 0.08 M 0.25 Base metal Gage plane T L-M N Section J1-J1 (rotated 90) 144 PL (K) C1 E (Y) View AB X X=L, M or N G θ1 DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA θ θ1 θ2 Millimeters MIN MAX 20.00 BSC 10.00 BSC 20.00 BSC 10.00 BSC 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.45 0.75 0.17 0.23 0.50 BSC 0.09 0.20 0.50 REF 0.25 BSC 0.13 0.20 0.13 0.20 22.00 BSC 11.00 BSC 22.00 BSC 11.00 BSC 0.25 REF 1.00 REF 0.09 0.16 0° 0° 7° 11° 13° (Z) CASE 918-03 ISSUE C Figure 3-3. DSP56303 Mechanical Information, 144-pin TQFP Package DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-9 Packaging 3.3 MAP-BGA Package Description Top and bottom views of the MAP-BGA package are shown in Figure 3-4 and Figure 3-5 with their pin-outs. Top View 1 2 3 4 5 10 11 12 13 14 NC SC11 TMS TDO MODB D16 D14 D11 D9 D7 NC B SRD1 SC12 TDI TRST D17 D15 D13 D10 D8 D5 NC C SC02 STD1 TCK VCCQ D18 VCCD D12 VCCD D6 D3 D4 D PINIT SC01 DE GND GND GND GND GND GND GND D1 D2 VCCD E STD0 VCCS SRD0 GND GND GND GND GND GND GND A17 A16 D0 F RXD SC10 GND GND GND GND GND GND GND GND VCCA A14 A15 G SCK1 TXD GND GND GND GND GND GND GND GND A13 VCCQ A12 H NC VCCQ SCK0 GND GND GND GND GND GND GND GND VCCA A10 A11 J HACK HRW HDS GND GND GND GND GND GND GND GND A8 A7 A9 K VCCS HREQ TIO2 GND GND GND GND GND GND GND GND VCCA A5 A6 L HCS TIO1 TIO0 GND GND GND GND GND GND GND GND VCCA A3 A4 M HA1 HA2 HA0 VCCH PB0 VCCP NC EXTAL CLK OUT BCLK WR RD A1 A2 N H6 H7 H4 H2 RESET GNDP AA3 CAS VCCQ BCLK BR VCCC AA0 A0 P NC H5 H3 H1 PCAP GNDP1 AA2 XTAL VCCC TA BB AA1 BG NC A 7 8 9 D23 VCCD D19 MODD D21 D20 MODA MODC D22 GND GND SC00 SCLK Figure 3-4. 6 DSP56303 Molded Array Process-Ball Grid Array (MAP-BGA), Top View DSP56303 Technical Data, Rev. 11 3-10 Freescale Semiconductor MAP-BGA Package Description Bottom View 14 13 12 11 10 9 8 7 NC D7 D9 D11 D14 D16 D19 VCCD NC D5 D8 D10 D13 D15 D17 D4 D3 D6 VCCD D12 VCCD VCCD D2 D1 GND GND D0 A16 A17 GND A15 A14 VCCA A12 VCCQ A11 5 4 3 2 1 D23 MODB TDO TMS SC11 NC D20 D21 MODD TRST TDI SC12 SRD1 B D18 VCCQ D22 MODC MODA TCK STD1 SC02 C GND GND GND GND GND GND DE SC01 PINIT D GND GND GND GND GND GND GND SRD0 VCCS STD0 E GND GND GND GND GND GND GND GND SC00 SC10 RXD F A13 GND GND GND GND GND GND GND GND TXD SCLK SCK1 G A10 VCCA GND GND GND GND GND GND GND GND SCK0 VCCQ A9 A7 A8 GND GND GND GND GND GND GND GND HDS HRW HACK J A6 A5 VCCA GND GND GND GND GND GND GND GND TIO2 HREQ VCCS K A4 A3 VCCA GND GND GND GND GND GND GND GND TIO0 TIO1 HCS L A2 A1 RD WR BCLK CLK OUT EXTAL NC VCCP PB0 VCCH HA0 HA2 HA1 M A0 AA0 VCCC BR BCLK VCCQ CAS AA3 GND P RESET H2 H4 H7 H6 N NC BG AA1 BB TA VCCC XTAL AA2 GNDP1 PCAP H1 H3 H5 NC P Figure 3-5. 6 NC A H DSP56303 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-11 Packaging Table 3-3. DSP56303 MAP-BGA Signal Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name A1 Not Connected (NC), reserved B12 D8 D9 GND A2 SC11 or PD1 B13 D5 D10 GND A3 TMS B14 NC D11 GND A4 TDO C1 SC02 or PC2 D12 D1 A5 MODB/IRQB C2 STD1 or PD5 D13 D2 A6 D23 C3 TCK D14 VCCD A7 VCCD C4 MODA/IRQA E1 STD0 or PC5 A8 D19 C5 MODC/IRQC E2 VCCS A9 D16 C6 D22 E3 SRD0 or PC4 A10 D14 C7 VCCQ E4 GND A11 D11 C8 D18 E5 GND A12 D9 C9 VCCD E6 GND A13 D7 C10 D12 E7 GND A14 NC C11 VCCD E8 GND B1 SRD1 or PD4 C12 D6 E9 GND B2 SC12 or PD2 C13 D3 E10 GND B3 TDI C14 D4 E11 GND B4 TRST D1 PINIT/NMI E12 A17 B5 MODD/IRQD D2 SC01 or PC1 E13 A16 B6 D21 D3 DE E14 D0 B7 D20 D4 GND F1 RXD or PE0 B8 D17 D5 GND F2 SC10 or PD0 B9 D15 D6 GND F3 SC00 or PC0 B10 D13 D7 GND F4 GND B11 D10 D8 GND F5 GND DSP56303 Technical Data, Rev. 11 3-12 Freescale Semiconductor MAP-BGA Package Description Table 3-3. DSP56303 MAP-BGA Signal Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name F6 GND H3 SCK0 or PC3 J14 A9 F7 GND H4 GND K1 VCCS F8 GND H5 GND K2 HREQ/HREQ, HTRQ/HTRQ, or PB14 F9 GND H6 GND K3 TIO2 F10 GND H7 GND K4 GND F11 GND H8 GND K5 GND F12 VCCA H9 GND K6 GND F13 A14 H10 GND K7 GND F14 A15 H11 GND K8 GND G1 SCK1 or PD3 H12 VCCA K9 GND G2 SCLK or PE2 H13 A10 K10 GND G3 TXD or PE1 H14 A11 K11 GND G4 GND J1 HACK/HACK, HRRQ/HRRQ, or PB15 K12 VCCA G5 GND J2 HRW, HRD/HRD, or PB11 K13 A5 G6 GND J3 HDS/HDS, HWR/HWR, or PB12 K14 A6 G7 GND J4 GND L1 HCS/HCS, HA10, or PB13 G8 GND J5 GND L2 TIO1 G9 GND J6 GND L3 TIO0 G10 GND J7 GND L4 GND G11 GND J8 GND L5 GND G12 A13 J9 GND L6 GND G13 VCCQ J10 GND L7 GND G14 A12 J11 GND L8 GND H1 NC J12 A8 L9 GND H2 VCCQ J13 A7 L10 GND L11 GND M13 A1 P1 NC L12 VCCA M14 A2 P2 H5, HAD5, or PB5 L13 A3 N1 H6, HAD6, or PB6 P3 H3, HAD3, or PB3 L14 A4 N2 H7, HAD7, or PB7 P4 H1, HAD1, or PB1 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-13 Packaging Table 3-3. DSP56303 MAP-BGA Signal Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name M1 HA1, HA8, or PB9 N3 H4, HAD4, or PB4 P5 PCAP M2 HA2, HA9, or PB10 N4 H2, HAD2, or PB2 P6 GND P1 M3 HA0, HAS/HAS, or PB8 N5 RESET P7 AA2/RAS2 M4 VCCH N6 GNDP P8 XTAL M5 H0, HAD0, or PB0 N7 AA3/RAS3 P9 VCCC M6 VCCP N8 CAS P10 TA M7 NC N9 VCCQ P11 BB M8 EXTAL N10 BCLK P12 AA1/RAS1 M9 CLKOUT N11 BR P13 BG M10 BCLK N12 VCCC P14 NC M11 WR N13 AA0/RAS0 M12 RD N14 A0 Notes: Signal names are based on configured functionality. Most connections supply a single signal. Some connections provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted but act as interrupt lines during operation. Some signals have configurable polarity; these names are shown with and without overbars, such as HAS/HAS. Some connections have two or more configurable functions; names assigned to these connections indicate the function for a specific configuration. For example, connection N2 is data line H7 in non-multiplexed bus mode, data/address line HAD7 in multiplexed bus mode, or GPIO line PB7 when the GPIO function is enabled for this pin. Unlike in the TQFP package, most of the GND pins are connected internally in the center of the connection array and act as heat sink for the chip. Therefore, except for GNDP and GND P1 that support the PLL, other GND signals do not support individual subsystems in the chip. DSP56303 Technical Data, Rev. 11 3-14 Freescale Semiconductor MAP-BGA Package Description Table 3-4. DSP56303 MAP-BGA Signal Identification by Name Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. A0 N14 BG P13 D7 A13 A1 M13 BR N11 D8 B12 A10 H13 CAS N8 D9 A12 A11 H14 CLKOUT M9 DE D3 A12 G14 D0 E14 EXTAL M8 A13 G12 D1 D12 GND D4 A14 F13 D10 B11 GND D5 A15 F14 D11 A11 GND D6 A16 E13 D12 C10 GND D7 A17 E12 D13 B10 GND D8 A2 M14 D14 A10 GND D9 A3 L13 D15 B9 GND D10 A4 L14 D16 A9 GND D11 A5 K13 D17 B8 GND E4 A6 K14 D18 C8 GND E5 A7 J13 D19 A8 GND E6 A8 J12 D2 D13 GND E7 A9 J14 D20 B7 GND E8 AA0 N13 D21 B6 GND E9 AA1 P12 D22 C6 GND E10 AA2 P7 D23 A6 GND E11 AA3 N7 D3 C13 GND F4 BB P11 D4 C14 GND F5 BCLK M10 D5 B13 GND F6 BCLK N10 D6 C12 GND F7 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-15 Packaging Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. GND F8 GND J9 H4 N3 GND F9 GND J10 H5 P2 GND F10 GND J11 H6 N1 GND F11 GND K4 H7 N2 GND G4 GND K5 HA0 M3 GND G5 GND K6 HA1 M1 GND G6 GND K7 HA10 L1 GND G7 GND K8 HA2 M2 GND G8 GND K9 HA8 M1 GND G9 GND K10 HA9 M2 GND G10 GND K11 HACK/HACK J1 GND G11 GND L4 HAD0 M5 GND H4 GND L5 HAD1 P4 GND H5 GND L6 HAD2 N4 GND H6 GND L7 HAD3 P3 GND H7 GND L8 HAD4 N3 GND H8 GND L9 HAD5 P2 GND H9 GND L10 HAD6 N1 GND H10 GND L11 HAD7 N2 GND H11 GNDP N6 HAS/HAS M3 GND J4 GND P1 P6 HCS/HCS L1 GND J5 H0 M5 HDS/HDS J3 GND J6 H1 P4 HRD/HRD J2 GND J7 H2 N4 HREQ/HREQ K2 GND J8 H3 P3 HRRQ/HRRQ J1 DSP56303 Technical Data, Rev. 11 3-16 Freescale Semiconductor MAP-BGA Package Description Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. HRW J2 PB14 K2 PE2 G2 HTRQ/HTRQ K2 PB15 J1 PINIT D1 HWR/HWR J3 PB2 N4 RAS0 N13 IRQA C4 PB3 P3 RAS1 P12 IRQB A5 PB4 N3 RAS2 P7 IRQC C5 PB5 P2 RAS3 N7 IRQD B5 PB6 N1 RD M12 MODA C4 PB7 N2 RESET N5 MODB A5 PB8 M3 RXD F1 MODC C5 PB9 M1 SC00 F3 MODD B5 PC0 F3 SC01 D2 NC A1 PC1 D2 SC02 C1 NC A14 PC2 C1 SC10 F2 NC B14 PC3 H3 SC11 A2 NC H1 PC4 E3 SC12 B2 NC M7 PC5 E1 SCK0 H3 NC P1 PCAP P5 SCK1 G1 NC P14 PD0 F2 SCLK G2 NMI D1 PD1 A2 SRD0 E3 PB0 M5 PD2 B2 SRD1 B1 PB1 P4 PD3 G1 STD0 E1 PB10 M2 PD4 B1 STD1 C2 PB11 J2 PD5 C2 TA P10 PB12 J3 PE0 F1 TCK C3 PB13 L1 PE1 G3 TDI B3 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 3-17 Packaging Table 3-4. DSP56303 MAP-BGA Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. TDO A4 VCCA K12 VCCP M6 TIO0 L3 VCCA L12 VCCQ C7 TIO1 L2 VCCC N12 VCCQ G13 TIO2 K3 VCCC P9 VCCQ H2 TMS A3 VCCD A7 VCCQ N9 TRST B4 VCCD C9 VCCS E2 TXD G3 VCCD C11 VCCS K1 VCCA F12 VCCD D14 WR M11 VCCA H12 VCCH M4 XTAL P8 3.4 MAP-BGA Package Mechanical Drawing Figure 3-6. DSP56303 Mechanical Information, 196-pin MAP-BGA Package DSP56303 Technical Data, Rev. 11 3-18 Freescale Semiconductor Design Considerations 4 This section describes various areas to consider when incorporating the DSP56303 device into a system design. 4.1 Thermal Design Considerations An estimate of the chip junction temperature, T J, in ° C can be obtained from this equation: Equation 1: T J = T A + ( P D × R θJA ) Where: TA RθJA PD = = = ambient temperature °C package junction-to-ambient thermal resistance °C/W power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a caseto-ambient thermal resistance, as in this equation: Equation 2: R θJ A = R θJC + R θCA Where: RθJA RθJC RθCA = = = package junction-to-ambient thermal resistance °C/W package junction-to-case thermal resistance °C/W package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB) or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimates obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. A complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 4-1 Design Considerations • To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to the point at which the leads attach to the case. • If the temperature of the package case (TT) is determined by a thermocouple, thermal resistance is computed from the value obtained by the equation (TJ – TT)/PD. As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable to determine the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will yield an estimate of a junction temperature slightly higher than actual temperature. Hence, the new thermal metric, thermal characterization parameter or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection when the surface temperature of the package is used. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). Use the following list of recommendations to ensure correct DSP operation. • Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. • Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. • Use at least a four-layer PCB with two inner layers for VCC and GND. • Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQC, IRQD, TA, and BG pins. Maximum PCB trace lengths on the order of 6 inches are recommended. DSP56303 Technical Data, Rev. 11 4-2 Freescale Semiconductor Power Consumption Considerations • Consider all device loads as well as parasitic capacitance due to PCB traces when you calculate capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. • All inputs must be terminated (that is, not allowed to float) by CMOS levels except for the three pins with internal pull-up resistors (TRST, TMS, DE). • Take special care to minimize noise levels on the VCCP, GNDP, and GNDP1 pins. • The following pins must be asserted after power-up: RESET and TRST. • If multiple DSP devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. • RESET • At power-up, ensure that the voltage difference between the 5 V tolerant pins and the chip V CC never exceeds 3.5 V. must be asserted when the chip is powered up. A stable EXTAL signal should be supplied before deassertion of RESET. 4.3 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications. Some of the factors affecting current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by this formula: Equation 3: I = C × V × f Where: C V f = = = node/pin capacitance voltage swing frequency of node/pin toggle Example 4-1. Current Consumption For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, with a 66 MHz clock, toggling at its maximum possible rate (33 MHz), the current consumption is expressed in Equation 4. Equation 4: I = 50 × 10 – 12 × 3.3 × 33 × 10 6 = 5.48 mA The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on bestcase operation conditions—not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. Perform the following steps for applications that require very low current consumption: 1. Set the EBD bit when you are not accessing external memory. 2. Minimize external memory accesses, and use internal memory accesses. 3. Minimize the number of pins that are switching. 4. Minimize the capacitive load on the pins. 5. Connect the unused inputs to pull-up or pull-down resistors. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 4-3 Design Considerations 6. Disable unused peripherals. 7. Disable unused pin activity (for example, CLKOUT, XTAL). One way to evaluate power consumption is to use a current-per-MIPS measurement methodology to minimize specific board effects (that is, to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A. Use the test algorithm, specific test current measurements, and the following equation to derive the current-per-MIPS value. Equation 5: I ⁄ MIPS = I ⁄ MHz = ( I typF2 – ItypF1 ) ⁄ ( F2 – F1 ) Where: ItypF2 ItypF1 F2 F1 = = = = current at F2 current at F1 high frequency (any specified operating frequency) low frequency (any specified operating frequency lower than F2) Note: F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. 4.4 PLL Performance Issues The following explanations should be considered as general observations on expected PLL behavior. There is no test that replicates these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges. 4.4.1 Phase Skew Performance The phase skew of the PLL is defined as the time difference between the falling edges of EXTAL and CLKOUT for a given capacitive load on CLKOUT, over the entire process, temperature and voltage ranges. As defined in Figure 22, External Clock Timing, on page 2-5 for input frequencies greater than 15 MHz and the MF ≤4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this skew is between −1.4 ns and +3.2 ns. 4.4.2 Phase Jitter Performance The phase jitter of the PLL is defined as the variations in the skew between the falling edges of EXTAL and CLKOUT for a given device in specific temperature, voltage, input frequency, MF, and capacitive load on CLKOUT. These variations are a result of the PLL locking mechanism. For input frequencies greater than 15 MHz and MF ≤4, this jitter is less than ±0.6 ns; otherwise, this jitter is not guaranteed. However, for MF < 10 and input frequencies greater than 10 MHz, this jitter is less than ±2 ns. 4.4.3 Frequency Jitter Performance The frequency jitter of the PLL is defined as the variation of the frequency of CLKOUT. For small MF (MF < 10) this jitter is smaller than 0.5 percent. For mid-range MF (10 < MF < 500) this jitter is between 0.5 percent and approximately 2 percent. For large MF (MF > 500), the frequency jitter is 2–3 percent. DSP56303 Technical Data, Rev. 11 4-4 Freescale Semiconductor Input (EXTAL) Jitter Requirements 4.5 Input (EXTAL) Jitter Requirements The allowed jitter on the frequency of EXTAL is 0.5 percent. If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. The phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. DSP56303 Technical Data, Rev. 11 Freescale Semiconductor 4-5 Design Considerations DSP56303 Technical Data, Rev. 11 4-6 Freescale Semiconductor Power Consumption Benchmark A The following benchmark program evaluates DSP56303 power use in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate (MAC) instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation. ;************************************************************************** ;************************************************************************** ;* * ;* CHECKS Typical Power Consumption * ;* * ;************************************************************************** page 200,55,0,0,0 nolist I_VEC EQU START EQU INT_PROG INT_XDAT INT_YDAT $000000; Interrupt vectors for program debug only $8000; MAIN (external) program starting address EQU $100 ; INTERNAL program memory starting address EQU $0; INTERNAL X-data memory starting address EQU $0; INTERNAL Y-data memory starting address INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org P:START ; movep #$0243FF,x:M_BCR ;; BCR: Area 3 = 2 w.s (SRAM) ; Default: 2w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 do #(XDAT_END-XDAT_START),XLOAD_LOOP DSP56303 Technical Data, Rev. 11 Freescale Semiconductor A-1 Power Consumption Benchmark move p:(r1)+,x0 move x0,x:(r0)+ XLOAD_LOOP ; ; Load the Y-data ; move #INT_YDAT,r0 move #YDAT_START,r1 do #(YDAT_END-YDAT_START),YLOAD_LOOP move p:(r1)+,x0 move x0,y:(r0)+ YLOAD_LOOP ; jmp PROG_START move move move move ; clr clr move move move move bset ; sbr dor mac mac add mac mac move _end bra nop nop nop nop PROG_END nop nop XDAT_START ; org dc dc dc dc dc dc dc dc dc dc INT_PROG #$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr ; ebd #60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 sbr x:0 $262EB9 $86F2FE $E56A5F $616CAC $8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 DSP56303 Technical Data, Rev. 11 A-2 Freescale Semiconductor dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc XDAT_END YDAT_START ; org dc dc $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5 $CA641A $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127 $482FD4 $7257D $E53C72 $1A8C3 $E27540 y:0 $5B6DA $C3F70B DSP56303 Technical Data, Rev. 11 Freescale Semiconductor A-3 Power Consumption Benchmark dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 $EF7AE1 $6E3006 $62F6C7 $6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF DSP56303 Technical Data, Rev. 11 A-4 Freescale Semiconductor dc dc YDAT_END $6162BC $E4A245 ;************************************************************************** ; ; EQUATES for DSP56303 I/O registers and ports ; ; Last update: June 11 1995 ; ;************************************************************************** page opt ioequ ident 132,55,0,0,0 mex 1,0 ;-----------------------------------------------------------------------; ; EQUATES for I/O Port Programming ; ;-----------------------------------------------------------------------; Register Addresses M_HDR EQU $FFFFC9 M_HDDR EQU $FFFFC8 M_PCRC EQU $FFFFBF M_PRRC EQU $FFFFBE M_PDRC EQU $FFFFBD M_PCRD EQU $FFFFAF M_PRRD EQU $FFFFAE M_PDRD EQU $FFFFAD M_PCRE EQU $FFFF9F M_PRRE EQU $FFFF9E M_PDRE EQU $FFFF9D M_OGDB EQU $FFFFFC ; ; ; ; ; ; ; ; ; ; ; ; Host Host Port Port Port Port Port Port Port Port Port OnCE port GPIO data Register port GPIO direction Register C Control Register C Direction Register C GPIO Data Register D Control register D Direction Data Register D GPIO Data Register E Control register E Direction Register E Data Register GDB Register ;-----------------------------------------------------------------------; ; EQUATES for Host Interface ; ;-----------------------------------------------------------------------; Register Addresses M_HCR EQU $FFFFC2 M_HSR EQU $FFFFC3 M_HPCR EQU $FFFFC4 M_HBAR EQU $FFFFC5 M_HRX EQU $FFFFC6 M_HTX EQU $FFFFC7 ; ; ; ; ; ; Host Host Host Host Host Host Control Register Status Register Polarity Control Register Base Address Register Receive Register Transmit Register ; HCR bits definition M_HRIE EQU $0 M_HTIE EQU $1 M_HCIE EQU $2 M_HF2 EQU $3 M_HF3 EQU $4 ; ; ; ; ; Host Host Host Host Host Receive interrupts Enable Transmit Interrupt Enable Command Interrupt Enable Flag 2 Flag 3 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor A-5 Power Consumption Benchmark ; HSR bits definition M_HRDF EQU $0 M_HTDE EQU $1 M_HCP EQU $2 M_HF0 EQU $3 M_HF1 EQU $4 ; ; ; ; ; Host Host Host Host Host Receive Data Full Receive Data Empty Command Pending Flag 0 Flag 1 ; HPCR bits definition M_HGEN EQU $0 M_HA8EN EQU $1 M_HA9EN EQU $2 M_HCSEN EQU $3 M_HREN EQU $4 M_HAEN EQU $5 M_HEN EQU $6 M_HOD EQU $8 M_HDSP EQU $9 M_HASP EQU $A M_HMUX EQU $B M_HD_HS EQU $C M_HCSP EQU $D M_HRP EQU $E M_HAP EQU $F ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Host Host Host Host Host Host Host Host Host Host Host Host Host Host Host Port GPIO Enable Address 8 Enable Address 9 Enable Chip Select Enable Request Enable Acknowledge Enable Enable Request Open Drain mode Data Strobe Polarity Address Strobe Polarity Multiplexed bus select Double/Single Strobe select Chip Select Polarity Request Polarity Acknowledge Polarity ;-----------------------------------------------------------------------; ; EQUATES for Serial Communications Interface (SCI) ; ;-----------------------------------------------------------------------; Register Addresses M_STXH EQU $FFFF97 M_STXM EQU $FFFF96 M_STXL EQU $FFFF95 M_SRXH EQU $FFFF9A M_SRXM EQU $FFFF99 M_SRXL EQU $FFFF98 M_STXA EQU $FFFF94 M_SCR EQU $FFFF9C M_SSR EQU $FFFF93 M_SCCR EQU $FFFF9B ; ; ; ; ; ; ; ; ; ; ; SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI Transmit Data Register (high) Transmit Data Register (middle) Transmit Data Register (low) Receive Data Register (high) Receive Data Register (middle) Receive Data Register (low) Transmit Address Register Control Register Status Register Clock Control Register SCI Control Register Bit Flags M_WDS EQU $7 M_WDS0 EQU 0 M_WDS1 EQU 1 M_WDS2 EQU 2 M_SSFTD EQU 3 M_SBK EQU 4 M_WAKE EQU 5 M_RWU EQU 6 M_WOMS EQU 7 M_SCRE EQU 8 M_SCTE EQU 9 M_ILIE EQU 10 ; ; ; ; ; ; ; ; ; ; ; ; Word Select Mask (WDS0-WDS3) Word Select 0 Word Select 1 Word Select 2 SCI Shift Direction Send Break Wakeup Mode Select Receiver Wakeup Enable Wired-OR Mode Select SCI Receiver Enable SCI Transmitter Enable Idle Line Interrupt Enable DSP56303 Technical Data, Rev. 11 A-6 Freescale Semiconductor M_SCRIE EQU 11 M_SCTIE EQU 12 M_TMIE EQU 13 M_TIR EQU 14 M_SCKP EQU 15 M_REIE EQU 16 ; SCI Receive Interrupt Enable SCI Transmit Interrupt Enable Timer Interrupt Enable Timer Interrupt Rate SCI Clock Polarity SCI Error Interrupt Enable (REIE) SCI Status Register Bit Flags M_TRNE EQU M_TDRE EQU M_RDRF EQU M_IDLE EQU M_OR EQU 4 M_PE EQU 5 M_FE EQU 6 M_R8 EQU 7 ; ; ; ; ; ; ; 0 1 2 3 ; ; ; ; ; ; ; ; Transmitter Empty Transmit Data Register Empty Receive Data Register Full Idle Line Flag Overrun Error Flag Parity Error Framing Error Flag Received Bit 8 (R8) Address ; ; ; ; ; Clock Divider Mask (CD0-CD11) Clock Out Divider Clock Prescaler Receive Clock Mode Source Bit Transmit Clock Source Bit SCI Clock Control Register M_CD EQU $FFF M_COD EQU 12 M_SCP EQU 13 M_RCM EQU 14 M_TCM EQU 15 ;-----------------------------------------------------------------------; ; EQUATES for Synchronous Serial Interface (SSI) ; ;-----------------------------------------------------------------------; ; Register Addresses Of SSI0 M_TX00 EQU $FFFFBC M_TX01 EQU $FFFFBB M_TX02 EQU $FFFFBA M_TSR0 EQU $FFFFB9 M_RX0 EQU $FFFFB8 M_SSISR0 EQU $FFFFB7 M_CRB0 EQU $FFFFB6 M_CRA0 EQU $FFFFB5 M_TSMA0 EQU $FFFFB4 M_TSMB0 EQU $FFFFB3 M_RSMA0 EQU $FFFFB2 M_RSMB0 EQU $FFFFB1 ; ; ; ; ; ; ; ; ; ; ; ; SSI0 SSIO SSIO SSI0 SSI0 SSI0 SSI0 SSI0 SSI0 SSI0 SSI0 SSI0 Transmit Data Register 0 Transmit Data Register 1 Transmit Data Register 2 Time Slot Register Receive Data Register Status Register Control Register B Control Register A Transmit Slot Mask Register A Transmit Slot Mask Register B Receive Slot Mask Register A Receive Slot Mask Register B ; Register Addresses Of SSI1 M_TX10 EQU $FFFFAC M_TX11 EQU $FFFFAB M_TX12 EQU $FFFFAA M_TSR1 EQU $FFFFA9 M_RX1 EQU $FFFFA8 M_SSISR1 EQU $FFFFA7 M_CRB1 EQU $FFFFA6 M_CRA1 EQU $FFFFA5 M_TSMA1 EQU $FFFFA4 M_TSMB1 EQU $FFFFA3 M_RSMA1 EQU $FFFFA2 M_RSMB1 EQU $FFFFA1 ; ; ; ; ; ; ; ; ; ; ; ; SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 SSI1 Transmit Data Register 0 Transmit Data Register 1 Transmit Data Register 2 Time Slot Register Receive Data Register Status Register Control Register B Control Register A Transmit Slot Mask Register A Transmit Slot Mask Register B Receive Slot Mask Register A Receive Slot Mask Register B DSP56303 Technical Data, Rev. 11 Freescale Semiconductor A-7 Power Consumption Benchmark ; SSI Control Register A Bit Flags M_PM EQU $FF M_PSR EQU 11 M_DC EQU $1F000 M_ALC EQU 18 M_WL EQU $380000 M_SSC1 EQU 22 ; Serial Output Flag Mask Serial Output Flag 0 Serial Output Flag 1 Serial Control Direction Mask Serial Control 0 Direction Serial Control 1 Direction Serial Control 2 Direction Clock Source Direction Shift Direction Frame Sync Length Mask (FSL0-FSL1) Frame Sync Length 0 Frame Sync Length 1 Frame Sync Relative Timing Frame Sync Polarity Clock Polarity Sync/Async Control SSI Mode Select SSI Transmit enable Mask SSI Transmit #2 Enable SSI Transmit #1 Enable SSI Transmit #0 Enable SSI Receive Enable SSI Transmit Interrupt Enable SSI Receive Interrupt Enable SSI Transmit Last Slot Interrupt Enable SSI Receive Last Slot Interrupt Enable SSI Transmit Error Interrupt Enable SI Receive Error Interrupt Enable ; ; ; ; ; ; ; ; ; Serial Input Flag Mask Serial Input Flag 0 Serial Input Flag 1 Transmit Frame Sync Flag Receive Frame Sync Flag Transmitter Underrun Error FLag Receiver Overrun Error Flag Transmit Data Register Empty Receive Data Register Full SSI Transmit Slot Mask Register A M_SSTSA EQU $FFFF ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; SSI Status Register Bit Flags M_IF EQU $3 M_IF0 EQU 0 M_IF1 EQU 1 M_TFS EQU 2 M_RFS EQU 3 M_TUE EQU 4 M_ROE EQU 5 M_TDE EQU 6 M_RDF EQU 7 ; Prescale Modulus Select Mask (PM0-PM7) Prescaler Range Frame Rate Divider Control Mask (DC0-DC7) Alignment Control (ALC) Word Length Control Mask (WL0-WL7) Select SC1 as TR #0 drive enable (SSC1) SSI Control Register B Bit Flags M_OF EQU $3 M_OF0 EQU 0 M_OF1 EQU 1 M_SCD EQU $1C M_SCD0 EQU 2 M_SCD1 EQU 3 M_SCD2 EQU 4 M_SCKD EQU 5 M_SHFD EQU 6 M_FSL EQU $180 M_FSL0 EQU 7 M_FSL1 EQU 8 M_FSR EQU 9 M_FSP EQU 10 M_CKP EQU 11 M_SYN EQU 12 M_MOD EQU 13 M_SSTE EQU $1C000 M_SSTE2 EQU 14 M_SSTE1 EQU 15 M_SSTE0 EQU 16 M_SSRE EQU 17 M_SSTIE EQU 18 M_SSRIE EQU 19 M_STLIE EQU 20 M_SRLIE EQU 21 M_STEIE EQU 22 M_SREIE EQU 23 ; ; ; ; ; ; ; ; SSI Transmit Slot Bits Mask A (TS0-TS15) SSI Transmit Slot Mask Register B M_SSTSB EQU $FFFF ; SSI Transmit Slot Bits Mask B (TS16-TS31) DSP56303 Technical Data, Rev. 11 A-8 Freescale Semiconductor ; SSI Receive Slot Mask Register A M_SSRSA EQU $FFFF ; ; SSI Receive Slot Bits Mask A (RS0-RS15) SSI Receive Slot Mask Register B M_SSRSB EQU $FFFF ; SSI Receive Slot Bits Mask B (RS16-RS31) ;-----------------------------------------------------------------------; ; EQUATES for Exception Processing ; ;------------------------------------------------------------------------ ; Register Addresses M_IPRC EQU $FFFFFF M_IPRP EQU $FFFFFE ; ; Interrupt Priority Register Core ; Interrupt Priority Register Peripheral Interrupt Priority Register Core (IPRC) M_IAL EQU $7 M_IAL0 EQU 0 M_IAL1 EQU 1 M_IAL2 EQU 2 M_IBL EQU $38 M_IBL0 EQU 3 M_IBL1 EQU 4 M_IBL2 EQU 5 M_ICL EQU $1C0 M_ICL0 EQU 6 M_ICL1 EQU 7 M_ICL2 EQU 8 M_IDL EQU $E00 M_IDL0 EQU 9 M_IDL1 EQU 10 M_IDL2 EQU 11 M_D0L EQU $3000 M_D0L0 EQU 12 M_D0L1 EQU 13 M_D1L EQU $C000 M_D1L0 EQU 14 M_D1L1 EQU 15 M_D2L EQU $30000 M_D2L0 EQU 16 M_D2L1 EQU 17 M_D3L EQU $C0000 M_D3L0 EQU 18 M_D3L1 EQU 19 M_D4L EQU $300000 M_D4L0 EQU 20 M_D4L1 EQU 21 M_D5L EQU $C00000 M_D5L0 EQU 22 M_D5L1 EQU 23 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; IRQA IRQA IRQA IRQA IRQB IRQB IRQB IRQB IRQC IRQC IRQC IRQC IRQD IRQD IRQD IRQD DMA0 DMA0 DMA0 DMA1 DMA1 DMA1 DMA2 DMA2 DMA2 DMA3 DMA3 DMA3 DMA4 DMA4 DMA4 DMA5 DMA5 DMA5 Mode Mask Mode Interrupt Priority Level (low) Mode Interrupt Priority Level (high) Mode Trigger Mode Mode Mask Mode Interrupt Priority Level (low) Mode Interrupt Priority Level (high) Mode Trigger Mode Mode Mask Mode Interrupt Priority Level (low) Mode Interrupt Priority Level (high) Mode Trigger Mode Mode Mask Mode Interrupt Priority Level (low) Mode Interrupt Priority Level (high) Mode Trigger Mode Interrupt priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Interrupt Priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Interrupt priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Interrupt Priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Interrupt priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) Interrupt priority Level Mask Interrupt Priority Level (low) Interrupt Priority Level (high) DSP56303 Technical Data, Rev. 11 Freescale Semiconductor A-9 Power Consumption Benchmark ; Interrupt Priority Register Peripheral (IPRP) M_HPL EQU $3 M_HPL0 EQU 0 M_HPL1 EQU 1 M_S0L EQU $C M_S0L0 EQU 2 M_S0L1 EQU 3 M_S1L EQU $30 M_S1L0 EQU 4 M_S1L1 EQU 5 M_SCL EQU $C0 M_SCL0 EQU 6 M_SCL1 EQU 7 M_T0L EQU $300 M_T0L0 EQU 8 M_T0L1 EQU 9 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Host Interrupt Priority Level Mask Host Interrupt Priority Level (low) Host Interrupt Priority Level (high) SSI0 Interrupt Priority Level Mask SSI0 Interrupt Priority Level (low) SSI0 Interrupt Priority Level (high) SSI1 Interrupt Priority Level Mask SSI1 Interrupt Priority Level (low) SSI1 Interrupt Priority Level (high) SCI Interrupt Priority Level Mask SCI Interrupt Priority Level (low) SCI Interrupt Priority Level (high) TIMER Interrupt Priority Level Mask TIMER Interrupt Priority Level (low) TIMER Interrupt Priority Level (high) ;-----------------------------------------------------------------------; ; EQUATES for TIMER ; ;-----------------------------------------------------------------------; Register Addresses Of TIMER0 M_TCSR0 EQU M_TLR0 EQU M_TCPR0 EQU M_TCR0 EQU ; Timer 0 Control/Status Register TIMER0 Load Reg TIMER0 Compare Register TIMER0 Count Register $FFFF8B $FFFF8A $FFFF89 $FFFF88 ; ; ; ; TIMER1 TIMER1 TIMER1 TIMER1 ; ; ; ; ; ; TIMER2 Control/Status Register TIMER2 Load Reg TIMER2 Compare Register TIMER2 Count Register TIMER Prescaler Load Register TIMER Prescalar Count Register Control/Status Register Load Reg Compare Register Count Register Register Addresses Of TIMER2 M_TCSR2 EQU M_TLR2 EQU M_TCPR2 EQU M_TCR2 EQU M_TPLR EQU M_TPCR EQU ; ; ; ; ; Register Addresses Of TIMER1 M_TCSR1 EQU M_TLR1 EQU M_TCPR1 EQU M_TCR1 EQU ; $FFFF8F $FFFF8E $FFFF8D $FFFF8C $FFFF87 $FFFF86 $FFFF85 $FFFF84 $FFFF83 $FFFF82 Timer Control/Status Register Bit Flags M_TE EQU 0 M_TOIE EQU 1 M_TCIE EQU 2 M_TC EQU $F0 M_INV EQU 8 M_TRM EQU 9 M_DIR EQU 11 ; ; ; ; ; ; ; Timer Enable Timer Overflow Interrupt Enable Timer Compare Interrupt Enable Timer Control Mask (TC0-TC3) Inverter Bit Timer Restart Mode Direction Bit DSP56303 Technical Data, Rev. 11 A-10 Freescale Semiconductor M_DI EQU 12 M_DO EQU 13 M_PCE EQU 15 M_TOF EQU 20 M_TCF EQU 21 ; ; ; ; ; ; Timer Prescaler Register Bit Flags M_PS EQU $600000 M_PS0 EQU 21 M_PS1 EQU 22 ; M_TC0 M_TC1 M_TC2 M_TC3 Data Input Data Output Prescaled Clock Enable Timer Overflow Flag Timer Compare Flag ; Prescaler Source Mask Timer Control Bits EQU 4 EQU 5 EQU 6 EQU 7 ; ; ; ; Timer Timer Timer Timer Control Control Control Control 0 1 2 3 ;-----------------------------------------------------------------------; ; EQUATES for Direct Memory Access (DMA) ; ;-----------------------------------------------------------------------; M_DSTR M_DOR0 M_DOR1 M_DOR2 M_DOR3 ; M_DSR0 M_DDR0 M_DCO0 M_DCR0 ; M_DSR1 M_DDR1 M_DCO1 M_DCR1 ; M_DSR2 M_DDR2 M_DCO2 M_DCR2 ; M_DSR3 M_DDR3 M_DCO3 M_DCR3 Register Addresses Of DMA EQU FFFFF4 EQU $FFFFF3 EQU $FFFFF2 EQU $FFFFF1 EQU $FFFFF0 ; ; ; ; ; DMA DMA DMA DMA DMA Status Offset Offset Offset Offset Register Register Register Register Register ; ; ; ; DMA0 DMA0 DMA0 DMA0 Source Address Register Destination Address Register Counter Control Register ; ; ; ; DMA1 DMA1 DMA1 DMA1 Source Address Register Destination Address Register Counter Control Register ; ; ; ; DMA2 DMA2 DMA2 DMA2 Source Address Register Destination Address Register Counter Control Register ; ; ; ; DMA3 DMA3 DMA3 DMA3 Source Address Register Destination Address Register Counter Control Register 0 1 2 3 Register Addresses Of DMA0 EQU EQU EQU EQU $FFFFEF $FFFFEE $FFFFED $FFFFEC Register Addresses Of DMA1 EQU EQU EQU EQU $FFFFEB $FFFFEA $FFFFE9 $FFFFE8 Register Addresses Of DMA2 EQU EQU EQU EQU $FFFFE7 $FFFFE6 $FFFFE5 $FFFFE4 Register Addresses Of DMA4 EQU EQU EQU EQU $FFFFE3 $FFFFE2 $FFFFE1 $FFFFE0 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor A-11 Power Consumption Benchmark ; M_DSR4 M_DDR4 M_DCO4 M_DCR4 ; Register Addresses Of DMA4 EQU EQU EQU EQU $FFFFDF $FFFFDE $FFFFDD $FFFFDC DMA4 DMA4 DMA4 DMA4 Source Address Register Destination Address Register Counter Control Register ; ; ; ; DMA5 DMA5 DMA5 DMA5 Source Address Register Destination Address Register Counter Control Register ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA ; ; ; ; ; ; ; ; ; ; ; ; Channel Transfer Done Status MASK (DTD0-DTD5) DMA Channel Transfer Done Status 0 DMA Channel Transfer Done Status 1 DMA Channel Transfer Done Status 2 DMA Channel Transfer Done Status 3 DMA Channel Transfer Done Status 4 DMA Channel Transfer Done Status 5 DMA Active State DMA Active Channel Mask (DCH0-DCH2) DMA Active Channel 0 DMA Active Channel 1 DMA Active Channel 2 Register Addresses Of DMA5 M_DSR5 M_DDR5 M_DCO5 M_DCR5 EQU EQU EQU EQU ; DMA Control Register $FFFFDB $FFFFDA $FFFFD9 $FFFFD8 M_DSS EQU $3 M_DSS0 EQU 0 M_DSS1 EQU 1 M_DDS EQU $C M_DDS0 EQU 2 M_DDS1 EQU 3 M_DAM EQU $3f0 M_DAM0 EQU 4 M_DAM1 EQU 5 M_DAM2 EQU 6 M_DAM3 EQU 7 M_DAM4 EQU 8 M_DAM5 EQU 9 M_D3D EQU 10 M_DRS EQU $F800 M_DCON EQU 16 M_DPR EQU $60000 M_DPR0 EQU 17 M_DPR1 EQU 18 M_DTM EQU $380000 M_DTM0 EQU 19 M_DTM1 EQU 20 M_DTM2 EQU 21 M_DIE EQU 22 M_DE EQU 23 ; ; ; ; ; Source Space Mask (DSS0-Dss1) Source Memory space 0 Source Memory space 1 Destination Space Mask (DDS-DDS1) Destination Memory Space 0 Destination Memory Space 1 Address Mode Mask (DAM5-DAM0) Address Mode 0 Address Mode 1 Address Mode 2 Address Mode 3 Address Mode 4 Address Mode 5 Three Dimensional Mode Request Source Mask (DRS0-DRS4) Continuous Mode Channel Priority Channel Priority Level (low) Channel Priority Level (high) Transfer Mode Mask (DTM2-DTM0) Transfer Mode 0 Transfer Mode 1 Transfer Mode 2 Interrupt Enable bit Channel Enable bit DMA Status Register M_DTD EQU $3F M_DTD0 EQU 0 M_DTD1 EQU 1 M_DTD2 EQU 2 M_DTD3 EQU 3 M_DTD4 EQU 4 M_DTD5 EQU 5 M_DACT EQU 8 M_DCH EQU $E00 M_DCH0 EQU 9 M_DCH1 EQU 10 M_DCH2 EQU 11 ;------------------------------------------------------------------------ DSP56303 Technical Data, Rev. 11 A-12 Freescale Semiconductor ; ; EQUATES for Phase Locked Loop (PLL) ; ;-----------------------------------------------------------------------; Register Addresses Of PLL M_PCTL EQU $FFFFFD ; ; PLL Control Register PLL Control Register M_MF EQU $FFF M_DF EQU $7000 M_XTLR EQU 15 M_XTLD EQU 16 M_PSTP EQU 17 M_PEN EQU 18 M_PCOD EQU 19 M_PD EQU $F00000 ; ; ; ; ; ; ; ; Multiplication Factor Bits Mask (MF0-MF11) Division Factor Bits Mask (DF0-DF2) XTAL Range select bit XTAL Disable Bit STOP Processing State Bit PLL Enable Bit PLL Clock Output Disable Bit PreDivider Factor Bits Mask (PD0-PD3) ;-----------------------------------------------------------------------; ; EQUATES for BIU ; ;-----------------------------------------------------------------------; Register Addresses Of BIU M_BCR EQU $FFFFFB M_DCR EQU $FFFFFA M_AAR0 EQU $FFFFF9 M_AAR1 EQU $FFFFF8 M_AAR2 EQU $FFFFF7 M_AAR3 EQU $FFFFF6 M_IDR EQU $FFFFF5 ; Bus Control Register DRAM Control Register Address Attribute Register Address Attribute Register Address Attribute Register Address Attribute Register ID Register ; ; ; ; ; ; ; ; Area 0 Wait Control Mask (BA0W0-BA0W4) Area 1 Wait Control Mask (BA1W0-BA14) Area 2 Wait Control Mask (BA2W0-BA2W2) Area 3 Wait Control Mask (BA3W0-BA3W3) Default Area Wait Control Mask (BDFW0-BDFW4) Bus State Bus Lock Hold Bus Request Hold ; ; ; ; ; ; ; ; In Page Wait States Bits Mask (BCW0-BCW1) Out Of Page Wait States Bits Mask (BRW0-BRW1) DRAM Page Size Bits Mask (BPS0-BPS1) Page Logic Enable Mastership Enable Refresh Enable Software Triggered Refresh Refresh Rate Bits Mask (BRF0-BRF7) 0 1 2 3 Bus Control Register M_BA0W EQU $1F M_BA1W EQU $3E0 M_BA2W EQU $1C00 M_BA3W EQU $E000 M_BDFW EQU $1F0000 M_BBS EQU 21 M_BLH EQU 22 M_BRH EQU 23 ; ; ; ; ; ; ; ; DRAM Control Register M_BCW EQU $3 M_BRW EQU $C M_BPS EQU $300 M_BPLE EQU 11 M_BME EQU 12 M_BRE EQU 13 M_BSTR EQU 14 M_BRF EQU $7F8000 DSP56303 Technical Data, Rev. 11 Freescale Semiconductor A-13 Power Consumption Benchmark M_BRP EQU 23 ; Address Attribute Registers M_BAT EQU $3 M_BAAP EQU 2 M_BPEN EQU 3 M_BXEN EQU 4 M_BYEN EQU 5 M_BAM EQU 6 M_BPAC EQU 7 M_BNC EQU $F00 M_BAC EQU $FFF000 ; ; Refresh prescaler ; ; ; ; ; ; ; ; ; Ext. Access Type and Pin Def. Bits Mask (BAT0-BAT1) Address Attribute Pin Polarity Program Space Enable X Data Space Enable Y Data Space Enable Address Muxing Packing Enable Number of Address Bits to Compare Mask (BNC0-BNC3) Address to Compare Bits Mask (BAC0-BAC11) control and status bits in SR M_CP EQU $c00000 M_CA EQU 0 M_V EQU 1 M_Z EQU 2 M_N EQU 3 M_U EQU 4 M_E EQU 5 M_L EQU 6 M_S EQU 7 M_I0 EQU 8 M_I1 EQU 9 M_S0 EQU 10 M_S1 EQU 11 M_SC EQU 13 M_DM EQU 14 M_LF EQU 15 M_FV EQU 16 M_SA EQU 17 M_CE EQU 19 M_SM EQU 20 M_RM EQU 21 M_CP0 EQU 22 M_CP1 EQU 23 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; mask for CORE-DMA priority bits in SR Carry Overflow Zero Negative Unnormalized Extension Limit Scaling Bit Interupt Mask Bit 0 Interupt Mask Bit 1 Scaling Mode Bit 0 Scaling Mode Bit 1 Sixteen_Bit Compatibility Double Precision Multiply DO-Loop Flag DO-Forever Flag Sixteen-Bit Arithmetic Instruction Cache Enable Arithmetic Saturation Rounding Mode bit 0 of priority bits in SR bit 1 of priority bits in SR ; control and status bits in OMR M_CDP EQU $300 ; mask for CORE-DMA priority bits in OMR M_MA equ0 ; Operating Mode A M_MB equ1 ; Operating Mode B M_MC equ2 ; Operating Mode C M_MD equ3 ; Operating Mode D M_EBD EQU 4 ; External Bus Disable bit in OMR M_SD EQU 6 ; Stop Delay M_MS EQU 7 ; Memory Switch bit in OMR M_CDP0 EQU 8 ; bit 0 of priority bits in OMR M_CDP1 EQU 9 ; bit 1 of priority bits in OMR M_BEN EQU 10 ; Burst Enable M_TAS EQU 11 ; TA Synchronize Select M_BRT EQU 12 ; Bus Release Timing M_ATE EQU 15 ; Address Tracing Enable bit in OMR. M_XYS EQU 16 ; Stack Extension space select bit in OMR. M_EUN EQU 17 ; Extensed stack UNderflow flag in OMR. M_EOV EQU 18 ; Extended stack OVerflow flag in OMR. M_WRP EQU 19 ; Extended WRaP flag in OMR. DSP56303 Technical Data, Rev. 11 A-14 Freescale Semiconductor M_SEN EQU 20 ; Stack Extension Enable bit in OMR. ;************************************************************************* ; ; EQUATES for DSP56303 interrupts ; ; Last update: June 11 1995 ; ;************************************************************************* page opt intequ ident if 132,55,0,0,0 mex 1,0 @DEF(I_VEC) ;leave user definition as is. else I_VEC EQU $0 endif ;-----------------------------------------------------------------------; Non-Maskable interrupts ;-----------------------------------------------------------------------I_RESET EQU I_VEC+$00 ; Hardware RESET I_STACK EQU I_VEC+$02 ; Stack Error I_ILL EQU I_VEC+$04 ; Illegal Instruction I_DBG EQU I_VEC+$06 ; Debug Request I_TRAP EQU I_VEC+$08 ; Trap I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt ;-----------------------------------------------------------------------; Interrupt Request Pins ;-----------------------------------------------------------------------I_IRQA EQU I_VEC+$10 ; IRQA I_IRQB EQU I_VEC+$12 ; IRQB I_IRQC EQU I_VEC+$14 ; IRQC I_IRQD EQU I_VEC+$16 ; IRQD ;-----------------------------------------------------------------------; DMA Interrupts ;-----------------------------------------------------------------------I_DMA0 EQU I_VEC+$18 ; DMA Channel 0 I_DMA1 EQU I_VEC+$1A ; DMA Channel 1 I_DMA2 EQU I_VEC+$1C ; DMA Channel 2 I_DMA3 EQU I_VEC+$1E ; DMA Channel 3 I_DMA4 EQU I_VEC+$20 ; DMA Channel 4 I_DMA5 EQU I_VEC+$22 ; DMA Channel 5 ;-----------------------------------------------------------------------; Timer Interrupts ;-----------------------------------------------------------------------I_TIM0C EQU I_VEC+$24 ; TIMER 0 compare I_TIM0OF EQU I_VEC+$26 ; TIMER 0 overflow I_TIM1C EQU I_VEC+$28 ; TIMER 1 compare DSP56303 Technical Data, Rev. 11 Freescale Semiconductor A-15 Power Consumption Benchmark I_TIM1OF EQU I_VEC+$2A I_TIM2C EQU I_VEC+$2C I_TIM2OF EQU I_VEC+$2E ; TIMER 1 overflow ; TIMER 2 compare ; TIMER 2 overflow ;-----------------------------------------------------------------------; ESSI Interrupts ;-----------------------------------------------------------------------I_SI0RD EQU I_VEC+$30 ; ESSI0 Receive Data I_SI0RDE EQU I_VEC+$32 ; ESSI0 Receive Data w/ exception Status I_SI0RLS EQU I_VEC+$34 ; ESSI0 Receive last slot I_SI0TD EQU I_VEC+$36 ; ESSI0 Transmit data I_SI0TDE EQU I_VEC+$38 ; ESSI0 Transmit Data w/ exception Status I_SI0TLS EQU I_VEC+$3A ; ESSI0 Transmit last slot I_SI1RD EQU I_VEC+$40 ; ESSI1 Receive Data I_SI1RDE EQU I_VEC+$42 ; ESSI1 Receive Data w/ exception Status I_SI1RLS EQU I_VEC+$44 ; ESSI1 Receive last slot I_SI1TD EQU I_VEC+$46 ; ESSI1 Transmit data I_SI1TDE EQU I_VEC+$48 ; ESSI1 Transmit Data w/ exception Status I_SI1TLS EQU I_VEC+$4A ; ESSI1 Transmit last slot ;-----------------------------------------------------------------------; SCI Interrupts ;-----------------------------------------------------------------------I_SCIRD EQU I_VEC+$50 ; SCI Receive Data I_SCIRDE EQU I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD EQU I_VEC+$54 ; SCI Transmit Data I_SCIIL EQU I_VEC+$56 ; SCI Idle Line I_SCITM EQU I_VEC+$58 ; SCI Timer ;-----------------------------------------------------------------------; HOST Interrupts ;-----------------------------------------------------------------------I_HRDF EQU I_VEC+$60 ; Host Receive Data Full I_HTDE EQU I_VEC+$62 ; Host Transmit Data Empty I_HC EQU I_VEC+$64 ; Default Host Command ;----------------------------------------------------------------------; INTERRUPT ENDING ADDRESS ;-----------------------------------------------------------------------I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space DSP56303 Technical Data, Rev. 11 A-16 Freescale Semiconductor Ordering Information Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Part Supply Voltage DSP56303 3.3 V Pin Count Core Frequency (MHz) Solder Spheres Order Number Thin Quad Flat Pack (TQFP) 144 100 Lead-free DSP56303AG100 Lead-bearing DSP56303PV100 Molded Array Process-Ball Grid Array (MAP-BGA) 196 100 Lead-free DSP56303VL100 Lead-bearing DSP56303VF100 Package Type How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations not listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GMBH Technical Information Center Schatzbogen 7 81829 München, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. 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