DSP56858FVE

56858 Data Sheet Technical Data 56800E 16-bit Digital Signal Controllers DSP56858 Rev. 6 01/2007 freescale.com DSP56858 General Description • 120 MIPS at 120MHz • Two (2) Serial Communication Interfaces (SCI) • 40K x 16-bit Program SRAM • Serial Port Interface (SPI) • 24K x 16-bit Data SRAM • 8-bit Parallel Host Interface • 1K x 16-bit Boot ROM • General Purpose 16-bit Quad Timer • Access up to 2M words of program memory or 8M data memory • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Chip Select Logic for glue-less interface to ROM and SRAM • Computer Operating Properly (COP)/Watchdog Timer • Six (6) independent channels of DMA • 144 LQFP and 144 MAPBGA packages • Two (2) Enhanced Synchronous Serial Interfaces (ESSI) • Up to 47 GPIO • Time-of -Day (TOD) 6 VDDIO VDD 12 8 VSSIO 14 JTAG/ Enhanced OnCE Program Controller and Hardware Looping Unit VSS VDDA 8 VSSA 2 16-Bit 56800E Core Address Generation Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit PAB PDB CDBR CDBW Data Memory 24,576 x 16 SRAM XAB1 XAB2 System Bus Control PAB DMA 6 channel PDB Core CLK Boot ROM 1024 x 16 ROM XDB2 CDBR CDBW DMA Requests Memory Program Memory 40,960 x 16 SRAM IPRDB IPAB Decoding Peripherals A0-20 [20:0] IPWDB IPBus Bridge (IPBB) IPBus CLK External Address Bus Switch D0-D15 [15:0] External Data Bus Switch RD Enable WR Enable CS0-CS3[3:0] or GPIOA0-A3 Bus Control POR System COP/TOD CLK Integration Module CLKO 3 MODE A-C or GPIOH0-H2 RSTO RESET External Bus Interface Unit 2 SCI ESSI0 or or GPIOE GPIOC 4 6 ESSI1 or GPIOD 6 Quad Timer or GPIOG 4 SPI Host Interrupt or Interface Controller GPIOF or GPIOB 4 16 COP/ Watchdog Time of Day Clock Generator EXTAL XTAL OSC PLL IRQA IRQB 56858 Block Diagram 56858 Technical Data, Rev. 6 Freescale Semiconductor 3 Part 1 Overview 1.1 56858 Features 1.1.1 • • • • • • • • • • • • • • • • 1.1.2 • • Digital Signal Processing Core Efficient 16-bit engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four (4) 36-bit accumulators including extension bits 16-bit bidirectional shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three (3) internal address buses and one (1) external address bus Four (4) internal data buses and one (1) external data bus Instruction set supports both DSP and controller functions Four (4) hardware interrupt levels Five (5) software interrupt levels Controller-style addressing modes and instructions for compact code Efficient C-Compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/Enhanced OnCE debug programming interface Memory Harvard architecture permits up to three (3) simultaneous accesses to program and data memory On-Chip Memory — 40K × 16-bit Program RAM — 24K × 16-bit Data RAM — 1K × 16-bit Boot ROM • Off-Chip Memory Expansion (EMI) — Access up to 2M words of program or 8M data memory (using chip selects) — Chip Select Logic for glue-less interface to ROM and SRAM 1.1.3 • • • • • • 56858 Peripheral Circuit Features General Purpose 16-bit Quad Timer* Two Serial Communication Interfaces (SCI)* Serial Peripheral Interface (SPI) Port* Two (2) Enhanced Synchronous Serial Interface (ESSI) modules* Computer Operating Properly (COP)/Watchdog Timer JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging 56858 Technical Data, Rev. 6 4 Freescale Semiconductor 56858 Description • • • • Six (6) independent channels of DMA 8-bit Parallel Host Interface* Time-of-Day (TOD) Up to 47 GPIO * Each peripheral I/O can be used alternately as a GPIO if not needed 1.1.4 • • Energy Information Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs Wait and Stop modes available 1.2 56858 Description The 56858 is a member of the 56800E core-based family of controllers. This device combines the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals on a single chip to create an extremely cost-effective solution. The low cost, flexibility, and compact program code make this device well-suited for many applications. The 56858 includes peripherals that are especially useful for teledatacom devices; Internet appliances; portable devices; TAD; voice recognition; hands-free devices; and general purpose applications. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of optimized control applications. The 56858 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56858 also provides two external dedicated interrupt lines, and up to 47 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56858 controller includes 40K words of Program RAM, 24K words of Data RAM and 1K of Boot RAM. It also supports program execution from external memory. This controller also provides a full set of standard programmable peripherals that include an 8-bit Parallel Host Interface, two Enhanced Synchronous Serial Interfaces (ESSI), one Serial Peripheral Interface (SPI), two Serial Communications Interfaces (SCI), and one Quad Timer. The Host Interface, Quad Timer, SSI, SPI, SCI I/O and four chip selects can be used as General Purpose Input/Outputs when its primary function is not required. 1.3 State of the Art Development Environment • • Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 56858 Technical Data, Rev. 6 Freescale Semiconductor 5 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description of and proper design with the 56858. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 56858 Chip Documentation Topic Description Order Number 56800E Reference Manual Detailed description of the 56800E architecture, 16-bit core processor and the instruction set 56800ERM DSP56858 User’s Manual Detailed description of memory, peripherals, and interfaces of the 56858 DSP5685xUM 56858 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) DSP56858 DSP56858 Errata Details any chip issues that might be present DSP56858E 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol Logic State Signal State Voltage1 PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56858 Technical Data, Rev. 6 6 Freescale Semiconductor Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56858 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals present. Table 2-1 56858 Functional Group Pin Allocations Functional Group Number of Pins Power (VDD, VDDIO, or VDDA) (8, 12, 1)1 Ground (VSS, VSSIO,or VSSA) (8, 14, 2)1 PLL and Clock 3 External Bus Signals 39 External Chip Select* 4 Interrupt and Program Control 72 Host Interface (HI)* 163 Enhanced Synchronous Serial Interface (ESSI0) Port* 6 Enhanced Synchronous Serial Interface (ESSI1) Port* 6 Serial Communications Interface (SCI0) Ports* 2 Serial Communications Interface (SCI1) Ports* 2 Serial Peripheral Interface (SPI) Port* 4 Quad Timer Module Port* 4 JTAG/On-Chip Emulation (OnCE) 6 *Alternately, GPIO pins 1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA 2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed. 3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ. 56858 Technical Data, Rev. 6 Freescale Semiconductor 7 Logic Power VDD VSS 1 8 1 8 56858 I/O Power VDDIO VSSIO 12 1 1 14 1 Analog Power1 VDDA VSSA 1 2 1 1 1 1 A0 - A20 Address Bus D0 - D15 RD WR 21 1 16 1 1 1 1 1 1 Chip Select CS0 - CS3 (GPIOA0 - A3) 4 1 1 HD0 - HD7 (GPIOB0 - B7) HA0 - HA2 (GPIOB8 - B10) HRWB (HRD) (GPIOB11) Host Interface HDS (HWR) (GPIOB12) HCS (GPIOB13) HREQ (HTRQ) (GPIOB14) HACK (HRRQ) (GPIOB15) Timer Module TIO0 - TIO3 (GPIOG0 - G3) IRQA IRQB Interrupt / Program Control MODA, MODB, MODC (GPIOH0 - H2) RESET RSTO 8 3 1 1 1 1 1 1 1 RXDO (GPIOE0) SCI 0 TXDO (GPIOE1) RXD1 (GPIOE2) SCI 2 TXD1 (GPIOE3) STD0 (GPIOC0) SRD0 (GPIOC1) SCK0 (GPIOC2) ESSI 0 SC00 (GPIOC3) SC01 (GPIOC4) SC02 (GPIOC5) STD1 (GPIOD0) SRD1 (GPIOD1) SCK1 (GPIOD2) ESSI 1 SC10 (GPIOD3) SC11 (GPIOD4) SC12 (GPIOD5) MISO (GPIOF0) MOSI (GPIOF1) SPI SCK (GPIOF2) SS (GPIOF3) 1 1 1 1 4 1 1 1 1 1 1 3 1 1 1 1 1 XTAL EXTAL PLL / Clock CLKO TCK TDI TDO JTAG / Enhanced OnCE TMS TRST DE Figure 2-1 56858 Signals Identified by Functional Group2 1. Specifically for PLL, OSC, and POR. 2. Alternate pin functions are shown in parentheses. Pin direction/type is represented as the preferred functionality. GPIO may provide bidirectional use of any pin. 56858 Technical Data, Rev. 6 8 Freescale Semiconductor Introduction Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be disabled under software control. 2. MODE A, MODE B and MODE C pins have no pull-up. 3. TCK has a weak pull-down circuit always active. 4. Bidirectional I/O pullups automatically disable when the output is enabled. This table is presented consistently with the Signals Identified by Functional Group figure. 1. BOLD entries in the Type column represents the state of the pin just out of reset. 2. Output(Z) means an output in a High-Z condition. Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type VDD E1 14 VDD VDD M6 36 Logic Power (VDD)—These pins provide power to the internal structures of the chip, and should all be attached to VDD. VDD F12 52 VDD A9 72 VDD M2 87 VDD J12 88 VDD E12 109 VDD A12 125 VSS G1 15 VSS VSS L6 16 Logic Power–Ground (VSS)—These pins provide grounding for the internal structures of the chip and should all be attached to VSS. VSS D12 53 VSS A7 54 VSS F1 71 VSS M7 89 VSS K12 126 VSS A8 127 Description 56858 Technical Data, Rev. 6 Freescale Semiconductor 9 Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type VDDIO B1 5 VDDIO VDDIO H1 6 I/O Power (VDDIO)—These pins provide power for all I/O and ESD structures of the chip and should all be attached to VDDIO (3.3V). VDDIO M3 20 VDDIO M8 45 VDDIO M11 61 VDDIO H12 67 VDDIO C12 68 VDDIO A11 80 VDDIO A5 105 VDDIO A3 113 VDDIO C1 129 VDDIO M10 139 VSSIO D1 7 VSSIO VSSIO J1 21 I/O Power–Ground (VSSIO)—These pins provide grounding for all I/O and ESD structures of the chip and should all be attached to VSS. VSSIO M5 46 VSSIO M9 47 VSSIO L12 62 VSSIO G12 69 VSSIO B12 70 VSSIO A10 82 VSSIO A4 106 VSSIO A1 115 VSSIO A2 128 VSSIO M4 130 VSSIO M12 140 VSSIO A6 141 VDDA K1 24 VDDA Analog Power (VDDA)—These pins supply an analog power source. VSSA M1 25 VSSA L1 26 VSSA Description Analog Ground (VSSA)—This pin supplies an analog ground. 56858 Technical Data, Rev. 6 10 Freescale Semiconductor Introduction Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type A0 E5 10 Output(Z) A1 E4 11 A2 E3 12 A3 E2 13 A4 J2 29 A5 H3 30 A6 G4 31 A7 H4 32 A8 G5 48 A9 L5 49 A10 J6 50 A11 K6 51 A12 J8 63 A13 K8 64 A14 L9 65 A15 K9 66 A16 K10 75 A17 K11 76 A18 J9 77 A19 J10 78 A20 J11 79 Description Address Bus (A0-A20)—These signals specify a word address for external program or data memory access. 56858 Technical Data, Rev. 6 Freescale Semiconductor 11 Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. D0 H7 81 D1 G7 94 D2 F9 95 D3 F10 96 D4 F11 97 D5 E10 98 D6 D7 120 D7 B7 121 D8 E7 122 D9 F8 123 D10 F7 124 D11 D5 137 D12 B4 138 D13 C4 142 D14 F6 143 D15 B3 144 RD D3 8 Type Input/ Output(Z) Output Description Data Bus (D0-D15)—These pins provide the bidirectional data for external program or data memory accesses. Read Enable (RD) — is asserted during external memory read cycles. This signal is pulled high during reset. WR D4 9 Output Write Enable (WR) —is asserted during external memory write cycles. This signal is pulled high during reset. CS0 H8 83 Input/Output GPIOA0 CS1 H9 84 H11 85 GPIOA3 Output Input/Output GPIOA2 CS3 Output Input/Output GPIOA1 CS2 Output H10 86 Output Input/Output External Chip Select (CS0)—This pin is used as a dedicated GPIO. Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. External Chip Select (CS1)—This pin is used as a dedicated GPIO. Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. External Chip Select (CS2)—This pin is used as a dedicated GPIO. Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. External Chip Select (CS3)—This pin is used as a dedicated GPIO. Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. 56858 Technical Data, Rev. 6 12 Freescale Semiconductor Introduction Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type HD0 J3 33 Input Description Host Address (HD0)—This input provides data selection for HI registers. This pin is disconnected internally during reset. GPIOB0 HD1 Input/Output K2 34 Input Port B GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD1)—This input provides data selection for HI registers. This pin is disconnected internally during reset. GPIOB1 HD2 Input/Output L2 35 Input Port B GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD2)—This input provides data selection for HI registers. This pin is disconnected internally during reset. GPIOB2 HD3 Input/Output J4 40 Input Port B GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD3)—This input provides data selection for HI registers. This pin is disconnected internally during reset. GPIOB3 HD4 Input/Output L4 41 Input Port B GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD4)—This input provides data selection for HI registers. This pin is disconnected internally during reset. GPIOB4 HD5 Input/Output J5 42 Input Port B GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD5)—This input provides data selection for HI registers. This pin is disconnected internally during reset. GPIOB5 Input/Output Port B GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. 56858 Technical Data, Rev. 6 Freescale Semiconductor 13 Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type HD6 K5 43 Input Description Host Address (HD6)—This input provides data selection for HI registers. This pin is disconnected internally during reset. GPIOB6 HD7 Input/Output H5 44 Input Port B GPIO (6)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Host Address (HD7)—This input provides data selection for HI registers. This pin is disconnected internally during reset. GPIOB7 HA0 G10 90 Input/Output Port B GPIO (7)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Input Host Address (HA0)—These inputs provide the address selection for HI registers. These pins are disconnected internally during reset. GPIOB8 HA1 Input/Output G11 91 Input Port B GPIO (8)—These pins are General Purpose I/O (GPIO) pins when not configured for host port usage. Host Address (HA0)—These inputs provide the address selection for HI registers. These pins are disconnected internally during reset. GPIOB9 HA2 Input/Output G9 92 Input Port B GPIO (9)—These pins are General Purpose I/O (GPIO) pins when not configured for host port usage. Host Address (HA0)—These inputs provide the address selection for HI registers. These pins are disconnected internally during reset. GPIOB10 HRWB Input/Output G8 93 Input Port B GPIO (10)—These pins are General Purpose I/O (GPIO) pins when not configured for host port usage. Host Read/Write (HRWB)—When the HI08 is programmed to interface to a single-data-strobe host bus and the HI function is selected, this signal is the Read/Write input. These pins are disconnected internally during reset. HRD Input GPIOB11 Input/Output Host Read Data (HRD)—This signal is the Read Data input when the HI08 is programmed to interface to a double-data-strobe host bus and the HI function is selected. Port B GPIO (11) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. 56858 Technical Data, Rev. 6 14 Freescale Semiconductor Introduction Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type Description HDS C8 116 Input Host Data Strobe (HDS)—When the HI08 is programmed to interface to a single-data-strobe host bus and the HI function is selected, this input enables a data transfer on the HI when HCS is asserted. These pins are disconnected internally during reset. HWR Input Host Write Enable (HWR)—This signal is the Write Data input when the HI08 is programmed to interface to a double-data-strobe host bus and the HI function is selected. GPIOB12 Input/Output Port B GPIO (12)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. HCS D8 117 Input Host Chip Select (HCS)—This input is the chip select input for the Host Interface. These pins are disconnected internally during reset. GPIOB13 HREQ B8 118 Input/Output Port B GPIO (13)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Open Drain Output Host Request (HREQ)—When the HI08 is programmed for HRMS=0 functionality (typically used on a single-data-strobe bus), this open drain output is used by the HI to request service from the host processor. The HREQ may be connected to an interrupt request pin of a host processor, a transfer request of a DMA controller, or a control input of external circuitry. These pins are disconnected internally during reset. HTRQ Open Drain Output Transmit Host Request (HTRQ)—This signal is the Transmit Host Request output when the HI08 is programmed for HRMS=1 functionality and is typically used on a double-data-strobe bus. GPIOB14 Input/Output Port B GPIO (14) —This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. 56858 Technical Data, Rev. 6 Freescale Semiconductor 15 Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type Description HACK C7 119 Input Host Acknowledge (HACK)—When the HI08 is programmed for HRMS=0 functionality (typically used on a single-data-strobe bus), this input has two functions: (1) provide a Host Acknowledge signal for DMA transfers or (2) to control handshaking and provide a Host Interrupt Acknowledge compatible with the MC68000 family processors. These pins are disconnected internally during reset. HRRQ Open Drain Output Receive Host Request (HRRQ)—This signal is the Receive Host Request output when the HI08 is programmed for HRMS=1 functionality and is typically used on a double-data-strobe bus. GPIOB15 Input/Output Port B GPIO (15)—This pin is a General Purpose I/O (GPIO) pin when not configured for host port usage. Input/Output Timer Input/Outputs (TIO0)—This pin can be independently configured to be either a timer input source or an output flag. Input/Output Port G GPIOG0—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. Input/Output Timer Input/Outputs (TIO1)—This pin can be independently configured to be either a timer input source or an output flag. Input/Output Port G GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. Input/Output Timer Input/Outputs (TIO2)—This pin can be independently configured to be either a timer input source or an output flag. Input/Output Port G GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. Input/Output Timer Input/Outputs (TIO3)—This pin can be independently configured to be either a timer input source or an output flag. Input/Output Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as an input or output pin. Input External Interrupt Request A and B—The IRQA and IRQB inputs are asynchronous external interrupt requests that indicate that an external device is requesting service. A Schmitt trigger input is used for noise immunity. They can be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull-up resistor is required for Wired-OR operation. Input Mode Select (MODE A)—During the bootstrap process MODE A selects one of the eight bootstrap modes. TIO0 B9 114 GPIOG0 TIO1 C9 112 GPIOG1 TIO2 D9 111 GPIOG2 TIO3 B10 110 GPIOG3 IRQA G2 22 IRQB F5 23 MODE A F4 17 GPIOH0 Input/Output Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. 56858 Technical Data, Rev. 6 16 Freescale Semiconductor Introduction Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type MODE B F3 18 Input GPIOH1 MODE C Input/Output F2 19 GPIOH2 RESET K4 39 Input Description Mode Select (MODE B)—During the bootstrap process MODE A selects one of the eight bootstrap modes. Port H GPIO (1)—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. Mode Select (MODE C)—During the bootstrap process MODE A selects one of the eight bootstrap modes. Input/Output Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the bootstrap process has completed. Input Reset (RESET)—This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the MODE A, MODE B, and MODE C pins. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware reset is required and it is necessary not to reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but do not assert TRST. RSTO K3 38 Output Reset Output (RSTO)—This output is asserted on any reset condition (external reset, low voltage, software, or COP). RXD0 L10 73 Input Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial data and transfers it to the SCI 0 receive shift register. GPIOE0 TXD0 L11 74 GPIOE1 RXD1 B11 107 GPIOE2 TXD1 C10 GPIOE3 108 Input/Output Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Output(Z) Serial Transmit Data 0 (TXD0)—This signal transmits data from the SCI 0 transmit data register. Input/Output Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Input Serial Receive Data 1 (RXD1)—This input receives byte-oriented serial data and transfers it to the SCI 1 receive shift register. Input/Output Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Output(Z) Serial Transmit Data 1 (TXD1)—This signal transmits data from the SCI 1 transmit data register. Input/Output Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. 56858 Technical Data, Rev. 6 Freescale Semiconductor 17 Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type STD0 B6 131 Output GPIOC0 SRD0 Input/Output C6 132 GPIOC1 SCK0 C5 133 GPIOC2 SC00 D6 134 GPIOC3 SC01 B5 135 GPIOC4 SC02 GPIOC5 E6 136 Input Description ESSI Transmit Data (STD0)—This output pin transmits serial data from the ESSI Transmitter Shift Register. Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Receive Data (SRD0)—This input pin receives serial data and transfers the data to the ESSI Receive Shift Register. Input/Output Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Input/Output ESSI Serial Clock (SCK0)—This bidirectional pin provides the serial bit rate clock for the transmit section of the ESSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. Input/Output Port C GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Input/Output ESSI Serial Control Pin 0 (SC00)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin will be used for the receive clock I/O. For synchronous mode, this pin is used either for transmitter1 output or for serial I/O flag 0. Input/Output Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Input/Output ESSI Serial Control Pin 1 (SC01)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin is the receiver frame sync I/O. For synchronous mode, this pin is used either for transmitter2 output or for serial I/O flag 1. Input/Output Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Input/Output ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Input or Output Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. 56858 Technical Data, Rev. 6 18 Freescale Semiconductor Introduction Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type STD1 E8 99 Output GPIOD0 SRD1 Input/Output E11 100 GPIOD1 SCK1 E9 101 GPIOD2 SC10 D10 102 GPIOD3 SC11 D11 103 GPIOD4 SC12 C11 GPIOC5 104 Input Description ESSI Transmit Data (STD1)—This output pin transmits serial data from the ESSI Transmitter Shift Register. Port D GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. ESSI Receive Data (SRD1)—This input pin receives serial data and transfers the data to the ESSI Receive Shift Register. Input/Output Port D GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Input/Output ESSI Serial Clock (SCK1)—This bidirectional pin provides the serial bit rate clock for the transmit section of the ESSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. Input/Output Port D GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Input/Output ESSI Serial Control Pin 0 (SC10)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin will be used for the receive clock I/O. For synchronous mode, this pin is used either for transmitter1 output or for serial I/O flag 0. Input/Output Port D GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Input/Output ESSI Serial Control Pin 1 (SC11)—The function of this pin is determined by the selection of either synchronous or asynchronous mode. For asynchronous mode, this pin is the receiver frame sync I/O. For synchronous mode, this pin is used either for transmitter2 output or for serial I/O flag 1. Input/Output Port D GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. Input/Output ESSI Serial Control Pin 2 (SC12)—This pin is used for frame sync I/O. SC02 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. When configured as an output, this pin is the internally generated frame sync signal. When configured as an input, this pin receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Input/Output Port D GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the ESSI is not in use. 56858 Technical Data, Rev. 6 Freescale Semiconductor 19 Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type Description MISO B2 1 Input/Output SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The driver on this pin can be configured as an open-drain driver by the SPI’s Wired-OR mode (WOM) bit when this pin is configured for SPI operation. Input/Output Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. GPIOF0 MOSI C3 2 GPIOF1 SCK C2 3 GPIOF2 SS D2 4 GPIOF3 Input/ Output (Z) SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. The driver on this pin can be configured as an open-drain driver by the SPI’s WOM bit when this pin is configured for SPI operation. Input/Output Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as input or output pin. Input/Output SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit rate clock for the SPI. This gated clock signal is an input to a slave device and is generated as an output by a master device. Slave devices ignore the SCK signal unless the SS pin is active low. In both master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. The driver on this pin can be configured as an open-drain driver by the SPI’s WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pull-up device. Input/Output Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Input SPI Slave Select (SS)—This input pin selects a slave device before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. The SS line of the master must be held high. Input/Output Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. XTAL H2 27 Input/Output Crystal Oscillator Output (XTAL)—This output connects the internal crystal oscillator output to an external crystal. If an external clock source other than a crystal oscillator is used, XTAL must be used as the input. EXTAL G3 28 Input External Crystal Oscillator Input (EXTAL)—This input should be connected to an external crystal. If an external clock source other than a crystal oscillator is used, EXTAL must be tied off. See Section 4.5.2 CLKO L3 37 Output Clock Output (CLKO)—This pin outputs a buffered clock signal. When enabled, this signal is the system clock divided by four. 56858 Technical Data, Rev. 6 20 Freescale Semiconductor Introduction Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type TCK L8 60 Input Test Clock Input (TCK)—This input pin provides a gated clock to synchronize the test logic and to shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor. TDI K7 58 Input Test Data Input (TDI)—This input pin provides a serial input data stream to the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. TDO G6 57 Output(Z) TMS J7 59 Input Description Test Data Output (TDO)—This tri-statable output pin provides a serial output data stream from the JTAG/Enhanced OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. Test Mode Select Input (TMS)—This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: TRST L7 56 Input Always tie the TMS pin to VDD through a 2.2K resistor. Test Reset (TRST)—As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment, since the Enhanced OnCE/JTAG module is under the control of the debugger. In this case it is not necessary to assert TRST when asserting RESET. Outside of a debugging environment RESET should be permanently asserted by grounding the signal, thus disabling the Enhanced OnCE/JTAG module on the device. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. 56858 Technical Data, Rev. 6 Freescale Semiconductor 21 Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA Signal Name BGA Pin No. LQFP Pin No. Type Description DE H6 55 Input/Output Debug Event (DE)—This is an open-drain, bidirectional, active low signal. As an input, it is a means of entering debug mode of operation from an external command controller. As an output, it is a means of acknowledging that the chip has entered debug mode. This pin is connected internally to a weak pull-up resistor. Part 4 Specifications 4.1 General Characteristics The 56858 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal operation without causing damage). This 5V tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56858 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. 56858 Technical Data, Rev. 6 22 Freescale Semiconductor General Characteristics CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 4-1 Absolute Maximum Ratings Characteristic Supply voltage, core Supply voltage, IO Supply voltage, analog Symbol Min Max Unit VDD1 VSS – 0.3 VSS + 2.0 V VDDIO2 VSSIO – 0.3 VSSA – 0.3 VSSIO + 4.0 VDDA + 4.0 V VIN VINA VSSIO – 0.3 VSSA – 0.3 VSSIO + 5.5 VDDA + 0.3 V I — 8 mA TJ -40 120 °C TSTG -55 150 °C VDDIO Digital input voltages Analog input voltages (XTAL, EXTAL) Current drain per pin excluding VDD, GND Junction temperature Storage temperature range 2 1. VDD must not exceed VDDIO 2. VDDIO and VDDA must not differ by more that 0.5V Table 4-2 Recommended Operating Conditions Characteristic Symbol Min Max Unit VDD 1.62 1.98 V Supply voltage for I/O Power VDDIO 3.0 3.6 V Supply voltage for Analog Power VDDA 3.0 3.6 V Ambient operating temperature TA -40 85 °C PLL clock frequency1 fpll — 240 MHz Operating Frequency2 fop — 120 MHz Frequency of peripheral bus fipb — 60 MHz Supply voltage for Logic Power 56858 Technical Data, Rev. 6 Freescale Semiconductor 23 Table 4-2 Recommended Operating Conditions (Continued) Characteristic Symbol Min Max Unit Frequency of external clock fclk — 240 MHz Frequency of oscillator fosc 2 4 MHz Frequency of clock via XTAL fxtal — 240 MHz Frequency of clock via EXTAL fextal 2 4 MHz 1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and selected. The actual frequency depends on the source clock frequency and programming of the CGM module. 2. Master clock is derived from on of the following four sources: fclk = fxtal when the source clock is the direct clock to EXTAL fclk = fpll when PLL is selected fclk = fosc when the source clock is the crystal oscillator and PLL is not selected fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected Table 4-3 Thermal Characteristics1 Value Characteristic Symbol Unit 144-pin LQFP 144 MAPBGA 42.9 36.1 Thermal resistance junction-to-ambient (estimated) θJA I/O pin power dissipation PI/O User Determined W Power dissipation PD PD = (IDD x VDD) + PI/O W PDMAX (TJ - TA) / RθJA 2 W Maximum allowed PD °C/W 1. See Section 6.1 for more detail. 2. TJ = Junction Temperature TA = Ambient Temperature 4.2 DC Electrical Characteristics Table 4-4 DC Electrical Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Typ Max Unit Input high voltage (XTAL/EXTAL) VIHC VDDA – 0.8 VDDA VDDA + 0.3 V Input low voltage (XTAL/EXTAL) VILC -0.3 — 0.5 V Input high voltage VIH 2.0 — 5.5 V Input low voltage VIL -0.3 — 0.8 V 56858 Technical Data, Rev. 6 24 Freescale Semiconductor DC Electrical Characteristics Table 4-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Typ Max Unit Input current low (pullups disabled) IIL -1 — 1 μA Input current high (pullups disabled) IIH -1 — 1 μA Output tri-state current low IOZL -10 — 10 μA Output tri-state current high IOZH -10 — 10 μA Output High Voltage VOH VDDIO – 0.7 — — V Output Low Voltage VOL — — 0.4 V Output High Current IOH 8 — 16 mA Output Low Current IOL 8 — 16 mA Input capacitance CIN — 8 — pF Output capacitance COUT — 12 — pF VDD supply current (Core logic, memories, peripherals) IDD4 — — — 70 0.05 5 110 10 14 mA mA mA — 40 0 50 1.5 mA mA — 60 120 μA 1 Run Deep Stop2 Light Stop3 VDDIO supply current (I/O circuity) IDDIO Run5 Deep Stop2 VDDA supply current (analog circuity) Deep IDDA Stop2 Low Voltage Interrupt6 VEI — 2.5 2.85 V Low Voltage Interrupt Recovery Hysteresis VEIH — 50 — mV Power on Reset7 POR — 1.5 2.0 V Note: Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail; no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out. 1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz. 2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating. 3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating. 4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry. 5. Running core and performing external memory access. Clock at 120 MHz. 6. When VDD drops below VEI max value, an interrupt is generated. 7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates. 56858 Technical Data, Rev. 6 Freescale Semiconductor 25 150 EMI Mode5 MAC Mode1 120 IDD (mA) 90 60 30 0 20 40 60 80 120 100 Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4) 4.3 Supply Voltage Sequencing and Separation Cautions DC Power Supply Voltage Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies. 3.3V VDDIO, VDDA 2 1.8V Supplies Stable VDD 1 0 Note: Time 1. VDD rising before VDDIO, VDDA 2. VDDIO, VDDA rising much faster than VDD Figure 4-2 Supply Voltage Sequencing and Separation Cautions 56858 Technical Data, Rev. 6 26 Freescale Semiconductor AC Electrical Characteristics VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from rising faster than VDDIO. VDD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper operation, the difference between supplies will typically be 0.8V and conduction through the diode chain reduces to essentially leakage current. During supply sequencing, the following general relationship should be adhered to: VDDIO > VDD > (VDDIO - 2.1V) In practice, VDDA is typically connected directly to VDDIO with some filtering. Supply VDDIO, VDDA 3.3V Regulator VDD 1.8V Regulator Figure 4-3 Example Circuit to Control Supply Sequencing 4.4 AC Electrical Characteristics Timing waveforms in Section 4.3 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of VIH and VIL for an input signal are shown. Low VIH Input Signal High 90% 50% 10% Midpoint1 VIL Fall Time Rise Time Note: The midpoint is VIL + (VIH – VIL)/2. Figure 4-4 Input Signal Measurement References 56858 Technical Data, Rev. 6 Freescale Semiconductor 27 Figure 4-5 shows the definitions of the following signal states: • • • Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH • Data Invalid state, when a signal level is in transition between VOL and VOH Data2 Valid Data1 Valid Data3 Valid Data2 Data1 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 4-5 Signal States 4.5 External Clock Operation The 56858 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 4.5.1 Crystal Oscillator The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 2–4MHz (optimized for 4MHz) EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 10MΩ TOD_SEL bit in CGM must be set to 0 fc = 4MHz fC Figure 4-6 Crystal Oscillator 56858 Technical Data, Rev. 6 28 Freescale Semiconductor External Clock Operation 4.5.2 High Speed External Clock Source (> 4MHz) The recommended method of connecting an external clock is given in Figure 4-7. The external clock source is connected to XTAL and the EXTAL pin is held at ground, VDDA, or VDDA/2. The TOD_SEL bit in CGM must be set to 0. 56858 XTAL EXTAL GND,VDDA, External Clock or VDDA/2 (up to 240MHz) Figure 4-7 Connecting a High Speed External Clock Signal using XTAL 4.5.3 Low Speed External Clock Source (2-4MHz) The recommended method of connecting an external clock is given in Figure 4-8. The external clock source is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM must be set to 0. 56858 XTAL EXTAL External Clock (2-4MHz) VDDA/2 Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL Table 4-5 External Clock Operation Timing Requirements4 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)1 fosc 0 — 240 MHz Clock Pulse Width4 tPW 6.25 — — ns External clock input rise time2, 4 trise — — TBD ns External clock input fall time3, 4 tfall — — TBD ns 1. See Figure 4-7 for details on using the recommended connection of an external clock driver. 2. External clock input rise time is measured from 10% to 90%. 3. External clock input fall time is measured from 90% to 10%. 4. Parameters listed are guaranteed by design. 56858 Technical Data, Rev. 6 Freescale Semiconductor 29 VIH External Clock 90% 50% 10% tPW 90% 50% 10% tPW trise tfall VIL Note: The midpoint is VIL + (VIH – VIL)/2. Figure 4-9 External Clock Timing Table 4-6 PLL Timing Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 2 4 4 MHz PLL output frequency fclk 40 — 240 MHz PLL stabilization time 2 tplls — 1 10 ms 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 4MHz input crystal. 2. This is the minimum time required after the PLL setup is changed to ensure reliable operation. 4.6 External Memory Interface Timing The External Memory Interface is designed to access static memory and peripheral devices. Figure 4-10 shows sample timing and parameters that are detailed in Table 4-7. The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user controlled wait states. The equation: t = D + P * (M + W) should be used to determine the actual time of each parameter. The terms in the above equation are defined as: t parameter delay time D fixed portion of the delay, due to on-chip path delays. P the period of the system clock, which determines the execution rate of the part (i.e. when the device is operating at 120 MHz, P = 8.33 ns). 56858 Technical Data, Rev. 6 30 Freescale Semiconductor External Memory Interface Timing M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible clock duty cycle derating. W the sum of the applicable wait state controls. See the “Wait State Controls” column of Table 4-7 for the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for details of what each wait state field controls. Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change if the operating frequency of the part changes. The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain two sets of numbers to account for this difference. The “Wait States Configuration” column of Table 4-7 should be used to make the appropriate selection. A0-Axx,CS tRD tARDD tARDA tRDA tRDRD RD tWAC tAWR tWRWR tWRRD tWR tRDWR WR tDWR D0-D15 tDOS tDOH tAD Data Out tRDD tDRD Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 4-10 External Memory Interface Timing 56858 Technical Data, Rev. 6 Freescale Semiconductor 31 Table 4-7 External Memory Interface Timing Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0–3.6V, TA = –40× to +120×C, CL £ 50pF, P = 8.333ns Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Symbol tAWR tWR Data Out Valid to WR Asserted tDWR Wait States Configuration D M Wait States Controls Unit WWS=0 -0.79 0.50 WWS>0 -1.98 0.69 WWSS ns WWS=0 -0.86 0.19 WWS>0 -0.01 0.00 WWS ns WWS=0 -1.52 0.00 WWS=0 - 5.69 0.25 WWS>0 -2.10 0.19 WWSS ns WWS>0 -4.66 0.50 -1.47 0.25 WWSH ns -2.36 0.19 -4.67 0.50 -1.60 0.25 WWSH Valid Data Out Hold Time after WR Deasserted tDOH Valid Data Out Set Up Time to WR Deasserted tDOS Valid Address after WR Deasserted tWAC RD Deasserted to Address Invalid tRDA - 0.44 0.00 RWSH ns Address Valid to RD Deasserted tARDD -2.07 1.00 RWSS,RWS ns Valid Input Data Hold after RD Deasserted tDRD 0.00 N/A1 — ns RD Assertion Width tRD -1.34 1.00 RWS ns Address Valid to Input Data Valid tAD -10.27 1.00 -13.5 1.19 RWSS,RWS ns - 0.94 0.00 RWSS ns -9.53 1.00 -12.64 1.19 RWSS,RWS ns Address Valid to RD Asserted tARDA RD Asserted to Input Data Valid tRDD WWS,WWSS ns WR Deasserted to RD Asserted tWRRD -0.75 0.25 WWSH,RWSS ns RD Deasserted to RD Asserted tRDRD -0.162 0.00 RWSS,RWSH ns WR Deasserted to WR Asserted tWRWR WWS=0 -0.44 0.75 WWS>0 -0.11 1.00 WWSS, WWSH ns 0.14 0.50 -0.57 0.69 MDAR, BMDAR, RWSH, WWSS ns RD Deasserted to WR Asserted tRDWR 1. N/A since device captures data before it deasserts RD 2. If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used. 56858 Technical Data, Rev. 6 32 Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing 4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit See Figure RESET Assertion to Address, Data and Control Signals High Impedance tRAZ — 11 ns Figure 4-11 Minimum RESET Assertion Duration3 tRA 30 — ns Figure 4-11 RESET Deassertion to First External Address Output tRDA — 120T ns Figure 4-11 Edge-sensitive Interrupt Request Width tIRW 1T + 3 — ns Figure 4-12 IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine tIDM 18T — ns Figure 4-13 tIDM -FAST 14T — tIG 18T — ns Figure 4-13 tIG -FAST 14T — tIRI 22T — ns Figure 4-14 tIRI -FAST 18T — 1.5T — IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State4 Delay from IRQA Assertion (exiting Stop) to External Data Memory5 tIW Delay from IRQA Assertion (exiting Wait) to External Data Memory Fast6 Normal7 tIF RSTO pulse width8 normal operation internal reset mode ns Figure 4-15 Figure 4-15 18T 22ET — — ns ns Figure 4-16 tRSTO 128ET 8ET — — — — 1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns. 2. Parameters listed are guaranteed by design. 3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock, txtal, textal or tosc. 4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 5. The interrupt instruction fetch is visible on the pins only in Mode 3. 6. Fast stop mode: Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one less cycle and tclk will continue same value it had before stop mode was entered. 56858 Technical Data, Rev. 6 Freescale Semiconductor 33 7. Normal stop mode: As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate. 8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns. RESET tRA tRAZ tRDA A0–Axx, D0–D15 First Fetch CS, RD, WR First Fetch Figure 4-11 Asynchronous Reset Timing IRQA IRQB tIRW Figure 4-12 External Interrupt Timing (Negative-Edge-Sensitive) A0–Axx, CS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 4-13 External Level-Sensitive Interrupt Timing 56858 Technical Data, Rev. 6 34 Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing IRQA, IRQB tIRI A0–Axx, CS, RD, WR First Interrupt Vector Instruction Fetch Figure 4-14 Interrupt from Wait State Timing tIW IRQA tIF A0–Axx, CS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 4-15 Recovery from Stop State Using Asynchronous Interrupt Timing RESET tRSTO Figure 4-16 Reset Output Timing 56858 Technical Data, Rev. 6 Freescale Semiconductor 35 4.8 Host Interface Port Table 4-9 Host Interface Port Timing1 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit See Figure Access time TACKDV — 13 ns 4-17 Disable time TACKDZ 3 — ns 4-17 Time to disassert TACKREQH 3.5 9 ns 4-17 4-20 Lead time TREQACKL 0 — ns 4-17 4-20 Access time TRADV — 13 Disable time TRADX 5 — Disable time TRADZ 3 — Setup time TDACKS 3 Hold time TACKDH Setup time ns 4-18 4-19 ns 4-18 4-19 ns 4-18 4-19 — ns 4-20 1 — ns 4-20 TADSS 3 — ns 4-21 4-22 Hold time TDSAH 1 — ns 4-21 4-22 Pulse width TWDS 5 — ns 4-21 4-22 TACKREQL 4T + 5 5 5T + 9 13 ns ns 4-19 4-20 Time to re-assert 1. After second write in 16-bit mode 2. After first write in 16-bit mode or after write in 8-bit mode 1. The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns. 56858 Technical Data, Rev. 6 36 Freescale Semiconductor Host Interface Port HACK TACKDZ TACKDV HD TREQACKL TACKREQH TACKREQL HREQ Figure 4-17 Controller-to-Host DMA Read Mode HA TRADX HCS HDS HRW TRADV TRADZ HD Figure 4-18 Single Strobe Read Mode 56858 Technical Data, Rev. 6 Freescale Semiconductor 37 HA TRADX HCS HWR HRD TRADZ TRADV HD Figure 4-19 Dual Strobe Read Mode HACK TDACKS TACKDH HD TREQACKL TACKREQH TACKREQL HREQ Figure 4-20 Host-to-Controller DMA Write Mode 56858 Technical Data, Rev. 6 38 Freescale Semiconductor Host Interface Port HA TDSAH HCS TWDS HDS TDSAH HRW TADSS TADSS TDSAH HD Figure 4-21 Single Strobe Write Mode HA HCS TWDS HWR TDSAH TADSS HRD TADSS HD Figure 4-22 Dual Strobe Write Mode 56858 Technical Data, Rev. 6 Freescale Semiconductor 39 4.9 Serial Peripheral Interface (SPI) Timing Figure 4-23 SPI Timing 1 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Cycle time Master Slave Min Max Unit 25 25 — — ns ns — 12.5 — — ns ns — 12.5 — — ns ns 9 12.5 — — 12 12.5 — — ns ns 10 2 — — ns ns 0 2 — — ns ns 15 ns ns 4-27 5 9 ns ns 4-27 2 — — 2 14 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.0 ns ns tC Enable lead time Master Slave tELD Enable lag time Master Slave tELG Clock (SCLK) high time Master Slave tCH Clock (SCLK) low time Master Slave tCL Data set-up time required for inputs Master Slave tDS Data hold time required for inputs Master Slave tDH Access time (time to data active from high-impedance state) Slave tA Disable time (hold time to high-impedance state) Slave tD Data valid for outputs Master Slave (after enable edge) tDV Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF See Figure 4-24, 4-25, 4-26, 4-27 4-27 4-27 ns ns 4-24, 4-25, 4-26, 4-27 4-27 4-24, 4-25, 4-26, 4-27 4-24, 4-25, 4-26, 4-27 4-24, 4-25, 4-26, 4-27 4-24, 4-25, 4-26, 4-27 4-24, 4-25, 4-26, 4-27 4-24, 4-25, 4-26, 4-27 1. Parameters listed are guaranteed by design. 56858 Technical Data, Rev. 6 40 Freescale Semiconductor Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tDS tCH MISO (Input) tCH MSB in Bits 14–1 tDI(ref) tDV tDI MOSI (Output) LSB in Master MSB out Bits 14–1 Master LSB out tR tF Figure 4-24 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH MISO (Input) MSB in tDS tR tDH Bits 14–1 tDI tDV(ref) MOSI (Output) tR tCL Master MSB out LSB in tDV Bits 14– 1 tF Master LSB out tR Figure 4-25 SPI Master Timing (CPHA = 1) 56858 Technical Data, Rev. 6 Freescale Semiconductor 41 SS (Input) tC tF tR tCL SCLK (CPOL = 0) (Input) tELG tCH tELD tCL SCLK (CPOL = 1) (Input) tA tCH MISO (Output) Slave MSB out tDS tDH MOSI (Input) MSB in tF tR tD Bits 14–1 Slave LSB out tDV tDI Bits 14–1 tDI LSB in Figure 4-26 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD SCLK (CPOL = 1) (Input) tCL tDV tA MISO (Output) tF tCH Slave MSB out tR Bits 14–1 tDV tDS tD Slave LSB out tDI tDH MOSI (Input) MSB in Bits 14–1 LSB in Figure 4-27 SPI Slave Timing (CPHA = 1) 56858 Technical Data, Rev. 6 42 Freescale Semiconductor Quad Timer Timing 4.10 Quad Timer Timing Table 4-10 Quad Timer Timing1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit PIN 2T + 3 — ns Timer input high/low period PINHL 1T + 3 — ns Timer output period POUT 2T - 3 — ns POUTHL 1T - 3 — ns Timer input period Timer output high/low period 1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns. 2. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL POUT POUTHL POUTHL Timer Outputs Figure 4-28 Timer Timing 4.11 Enhanced Synchronous Serial Interface (ESSI) Timing Table 4-11 ESSI Master Mode1 Switching Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Parameter Symbol Min Typ fs — SCK period3 tSCKW SCK high time SCK low time SCK frequency Output clock rise/fall time Delay from SCK high to SC2 (bl) high - Master5 Max Units — 152 MHz 66.7 — — ns tSCKH 33.44 — — ns tSCKL 33.44 — — ns — — 4 — ns tTFSBHM -1.0 — 1.0 ns 56858 Technical Data, Rev. 6 Freescale Semiconductor 43 Table 4-11 ESSI Master Mode1 Switching Characteristics (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Parameter Symbol Min Typ Max Units Delay from SCK high to SC2 (wl) high - Master5 tTFSWHM -1.0 — 1.0 ns Delay from SC0 high to SC1 (bl) high - Master5 tRFSBHM -1.0 — 1.0 ns Delay from SC0 high to SC1 (wl) high - Master5 tRFSWHM -1.0 — 1.0 ns Delay from SCK high to SC2 (bl) low - Master5 tTFSBLM -1.0 — 1.0 ns Delay from SCK high to SC2 (wl) low - Master5 tTFSWLM -1.0 — 1.0 ns Delay from SC0 high to SC1 (bl) low - Master5 tRFSBLM -1.0 — 1.0 ns Delay from SC0 high to SC1 (wl) low - Master5 tRFSWLM -1.0 — 1.0 ns SCK high to STD enable from high impedance - Master tTXEM -0.1 — 2 ns SCK high to STD valid - Master tTXVM -0.1 — 2 ns SCK high to STD not valid - Master tTXNVM -0.1 — — ns SCK high to STD high impedance - Master tTXHIM -4 — 0 ns SRD Setup time before SC0 low - Master tSM 4 — — ns SRD Hold time after SC0 low - Master tHM 4 — — ns Synchronous Operation (in addition to standard internal clock parameters) SRD Setup time before SCK low - Master tTSM 4 — — ns SRD Hold time after SCK low - Master tTHM 4 — — ns 1. Master mode is internally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part. 3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length 56858 Technical Data, Rev. 6 44 Freescale Semiconductor Enhanced Synchronous Serial Interface (ESSI) Timing tSCKH tSCKW tSCKL SCK output tTFSBHM tTFSBLM SC2 (bl) output tTFSWHM tTFSWLM SC2 (wl) output tTXVM tTXEM tTXNVM tTXHIM First Bit STD Last Bit SC0 output tRFSBHM tRFBLM SC1 (bl) output tRFSWHM tRFSWLM SC1 (wl) output tSM tHM tTSM tTHM SRD Figure 4-29 Master Mode Timing Diagram Table 4-12 ESSI Slave Mode1 Switching Characteristics Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Parameter Symbol Min Typ Max Units fs — — 152 MHz SCK period3 tSCKW 66.7 — — ns SCK high time tSCKH 33.44 — — ns SCK low time tSCKL 33.44 — — ns — — 4 — ns SCK frequency Output clock rise/fall time 56858 Technical Data, Rev. 6 Freescale Semiconductor 45 Table 4-12 ESSI Slave Mode1 Switching Characteristics (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Parameter Symbol Min Typ Max Units Delay from SCK high to SC2 (bl) high - Slave5 tTFSBHS -1 — 29 ns Delay from SCK high to SC2 (wl) high - Slave5 tTFSWHS -1 — 29 ns Delay from SC0 high to SC1 (bl) high - Slave5 tRFSBHS -1 — 29 ns Delay from SC0 high to SC1 (wl) high - Slave5 tRFSWHS -1 — 29 ns Delay from SCK high to SC2 (bl) low - Slave5 tTFSBLS -29 — 29 ns Delay from SCK high to SC2 (wl) low - Slave5 tTFSWLS -29 — 29 ns Delay from SC0 high to SC1 (bl) low - Slave5 tRFSBLS -29 — 29 ns Delay from SC0 high to SC1 (wl) low - Slave5 tRFSWLS -29 — 29 ns SCK high to STD enable from high impedance - Slave tTXES — — 15 ns SCK high to STD valid - Slave tTXVS 4 — 15 ns SC2 high to STD enable from high impedance (first bit) - Slave tFTXES 4 — 15 ns SC2 high to STD valid (first bit) - Slave tFTXVS 4 — 15 ns SCK high to STD not valid - Slave tTXNVS 4 — 15 ns SCK high to STD high impedance - Slave tTXHIS 4 — 15 ns SRD Setup time before SC0 low - Slave tSS 4 — — ns SRD Hold time after SC0 low - Slave tHS 4 — — ns Synchronous Operation (in addition to standard external clock parameters) SRD Setup time before SCK low - Slave tTSS 4 — — ns SRD Hold time after SCK low - Slave tTHS 4 — — ns 1. Slave mode is externally generated clocks and frame syncs 2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part. 3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in the tables and in the figures. 4. 50 percent duty cycle 5. bl = bit length; wl = word length 56858 Technical Data, Rev. 6 46 Freescale Semiconductor Enhanced Synchronous Serial Interface (ESSI) Timing tSCKW tSCKH tSCKL SCK input tTFSBLS tTFSBHS SC2 (bl) input tTFSWHS tTFSWLS SC2 (wl) input tFTXVS tFTXES tTXNVS tTXVS tTXES tTXHIS First Bit STD SC0 input Last Bit tRFBLS tRFSBHS SC1 (bl) input tRFSWHS tRFSWLS SC1 (wl) input tSS tHS tTSS tTHS SRD Figure 4-30 Slave Mode Clock Timing 56858 Technical Data, Rev. 6 Freescale Semiconductor 47 4.12 Serial Communication Interface (SCI) Timing Table 4-13 SCI Timing4 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit BR — (fMAX)/(32) Mbps RXD2 Pulse Width RXDPW 0.965/BR 1.04/BR ns TXD3 Pulse Width TXDPW 0.965/BR 1.04/BR ns Baud Rate1 1. fMAX is the frequency of operation of the system clock in MHz. 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) RXDPW Figure 4-31 RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 4-32 TXD Pulse Width 56858 Technical Data, Rev. 6 48 Freescale Semiconductor JTAG Timing 4.13 JTAG Timing Table 4-14 JTAG Timing1, 3 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit TCK frequency of operation2 fOP DC 30 MHz TCK cycle time tCY 33.3 — ns TCK clock pulse width tPW 16.6 — ns TMS, TDI data setup time tDS 3 — ns TMS, TDI data hold time tDH 3 — ns TCK low to TDO data valid tDV — 12 ns TCK low to TDO tri-state tTS — 10 ns tTRST 35 — ns tDE 4T — ns TRST assertion time DE assertion time 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz operation, T = 8.33ns. 2. TCK frequency of operation must be less than 1/4 the processor rate. 3. Parameters listed are guaranteed by design. tCY tPW tPW VIH VM TCK (Input) VM = VIL + (VIH – VIL)/2 VM VIL Figure 4-33 Test Clock Input Timing Diagram 56858 Technical Data, Rev. 6 Freescale Semiconductor 49 TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) Figure 4-34 Test Access Port Timing Diagram TRST (Input) tTRST Figure 4-35 TRST Timing Diagram DE tDE Figure 4-36 Enhanced OnCE—Debug Event 56858 Technical Data, Rev. 6 50 Freescale Semiconductor GPIO Timing 4.14 GPIO Timing Table 4-15 GPIO Timing1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit PIN 2T + 3 — ns GPIO input high/low period PINHL 1T + 3 — ns GPIO output period POUT 2T - 3 — ns POUTHL 1T - 3 — ns GPIO input period GPIO output high/low period 1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns 2. Parameters listed are guaranteed by design. GPIO Inputs PIN PINHL PINHL POUT POUTHL POUTHL GPIO Outputs Figure 4-37 GPIO Timing 56858 Technical Data, Rev. 6 Freescale Semiconductor 51 Part 5 Packaging 5.1 Package and Pin-Out Information 56853 D15 D14 D13 VSSIO VSSIO VDDIO D12 D11 SC02 SC01 SC00 SCK0 SRD0 STD0 VSSIO VDDIO VSSIO VSS VSS VDD D10 D9 D8 D7 D6 HACK HREQ HCS HDS VSSIO TIO0 VDDIO TIO1 TIO2 TIO3 VDD This section contains package and pin-out information for the 144-pin LQFP configuration of the 56858. MISO MOSI SCK SS VDDIO VDDIO VSSIO Orientation Mark PIN 109 PIN 1 RD WR A0 A1 A2 A3 VDD VSS VSS MODA MODB MODC VDDIO VSSIO IRQA IRQB VDDA VSSA VSSA PIN 37 PIN 73 CS3 CS2 CS1 CS0 VSSIO D0 VDDIO A20 A19 A18 A17 A16 TXD0 RXD0 CLKO RSTO RESET HD3 HD4 HD5 HD6 HD7 VDDIO VSSIO VSSIO A8 A9 A10 A11 VDD VSS VSS DE TRST TDO TDI TMS TCK VDDIO VSSIO A12 A13 A14 A15 VDDIO VDDIO VSSIO VSSIO VSS VDD XTAL EXTAL A4 A5 A6 A7 HD0 HD1 HD2 VDD TXD1 RXD1 VSSIO VDDIO SC12 SC11 SC10 SCK1 SRD1 STD1 D5 D4 D3 D2 D1 HRWB HA2 HA1 HA0 VSS VDD VDD Figure 5-1 Top View, 56858 144-pin LQFP Package 56858 Technical Data, Rev. 6 52 Freescale Semiconductor Package and Pin-Out Information 56853 Table 5-1 56858 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 1 MISO 37 CLKO 73 RXD0 109 VDD 2 MOSI 38 RSTO 74 TXD0 110 TIO3 3 SCK 39 RESET 75 A16 111 TIO2 4 SS 40 HD3 76 A17 112 TIO1 5 VDDIO 41 HD4 77 A18 113 VDDIO 6 VDDIO 42 HD5 78 A19 114 TIO0 7 VSSIO 43 HD6 79 A20 115 VSSIO 8 RD 44 HD7 80 VDDIO 116 HDS 9 WR 45 VDDIO 81 D0 117 HCS 10 A0 46 VSSIO 82 VSSIO 118 HREQ 11 A1 47 VSSIO 83 CS0 119 HACK 12 A2 48 A8 84 CS1 120 D6 13 A3 49 A9 85 CS2 121 D7 14 VDD 50 A10 86 CS3 122 D8 15 VSS 51 A11 87 VDD 123 D9 16 VSS 52 VDD 88 VDD 124 D10 17 MODA 53 VSS 89 VSS 125 VDD 18 MODB 54 VSS 90 HA0 126 VSS 19 MODC 55 DE 91 HA1 127 VSS 20 VDDIO 56 TRST 92 HA2 128 VSSIO 21 VSSIO 57 TDO 93 HRWB 129 VDDIO 22 IRQA 58 TDI 94 D1 130 VSSIO 23 IRQB 59 TMS 95 D2 131 STD0 56858 Technical Data, Rev. 6 Freescale Semiconductor 53 Table 5-1 56858 Pin Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 24 VDDA 60 TCK 96 D3 132 SRD0 25 VSSA 61 VDDIO 97 D4 133 SCK0 26 VSSA 62 VSSIO 98 D5 134 SC00 27 XTAL 63 A12 99 STD1 135 SC01 28 EXTAL 64 A13 100 SRD1 136 SC02 29 A4 65 A14 101 SCK1 137 D11 30 A5 66 A15 102 SC10 138 D12 31 A6 67 VDDIO 103 SC11 139 VDDIO 32 A7 68 VDDIO 104 SC12 140 VSSIO 33 HD0 69 VSSIO 105 VDDIO 141 VSSIO 34 HD1 70 VSSIO 106 VSSIO 142 D13 35 HD2 71 VSS 107 RXD1 143 D14 36 VDD 72 VDD 108 TXD1 144 D15 56858 Technical Data, Rev. 6 54 Freescale Semiconductor Package and Pin-Out Information 56853 Figure 5-2 144-pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. 56858 Technical Data, Rev. 6 Freescale Semiconductor 55 This section contains package and pin-out information for the 144-pin MAPBGA configuration of the 56858. METALLIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA 12 11 10 9 8 7 6 5 4 VDD VDDIO VSSIO VDD VSS VSS VSSIO VDDIO VSSIO VSSIO RXD1 TIO3 TIO0 HREQ D7 STD0 SC01 VDDIO SC12 TXD1 TIO1 HDS HACK SRD0 VSS SC11 SC10 TIO2 HCS D6 VDD SRD1 D5 SCK1 STD10 D8 2 1 VDDIO VSSIO VSSIO D12 D15 MISO VDDIO SCK0 D13 MOSI SCK VDDIO SC00 D11 WR RD SS VSSIO SC02 A0 A1 A2 A3 VDD 3 A B C D E F VDD D4 D3 D2 D9 D10 D14 IRQB MODA MODB MODC VSS G VSSIO HA1 HA0 HA2 HRWB D1 TDO A8 A6 EXTAL IRQA VSS VDDIO CS2 CS3 CS1 CS0 D0 DE HD7 A7 A5 XTAL VDDIO VDD A20 A19 A18 A12 TMS A10 HD5 HD3 HD0 A4 VSSIO VSS A17 A16 A15 A13 TDI A11 HD6 RESET RSTO HD1 VDDA VSSIO TXD0 RXD0 A14 TCK TRST VSS A9 HD4 CLKO HD2 VSSA VSS10 VDDIO VDDIO VSSIO VDDIO VSS VDD VSSIO VSSIO VDD VSSA H J K L VDDIO M Figure 5-3 Bottom-View, 56858 144-pin MAPBGA Package 56858 Technical Data, Rev. 6 56 Freescale Semiconductor Package and Pin-Out Information 56853 Table 5-2 56858 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name E5 A0 F7 D10 D8 HCS A5 VDDIO E4 A1 D5 D11 J3 HD0 A3 VDDIO E3 A2 B4 D12 K2 HD1 C1 VDDIO E2 A3 C4 D13 L2 HD2 M10 VDDIO J2 A4 F6 D14 J4 HD3 D3 RD H3 A5 B3 D15 L4 HD4 K4 RESET G4 A6 H6 DE J5 HD5 K3 RSTO H4 A7 G3 EXTAL K5 HD6 L10 RXD0 G5 A8 M1 VSSA H5 HD7 B11 RXD1 L5 A9 L1 VSSA C8 HDS D6 SC00 J6 A10 G1 VSS B8 HREQ B5 SC01 K6 A11 L6 VSS G8 HRWB E6 SC02 J8 A12 D12 VSS G2 IRQA D10 SC10 K8 A13 A7 VSS F5 IRQB D11 SC11 L9 A14 F1 VSS B2 MISO C11 SC12 K9 A15 M7 VSS F4 MODA C5 SCK0 K10 A16 K12 VSS F3 MODB E9 SCK1 K11 A17 A8 VSS F2 MODC C2 SCK J9 A18 D1 VSSIO C3 MOSI C6 SRD0 J10 A19 J1 VSSIO K1 VDDA E11 SRD1 J11 A20 M5 VSSIO E1 VDD D2 SS L3 CLKO M9 VSSIO M6 VDD B6 STD0 H8 CS0 L12 VSSIO F12 VDD E8 STD1 H9 CS1 G12 VSSIO A9 VDD L8 TCK 56858 Technical Data, Rev. 6 Freescale Semiconductor 57 Table 5-2 56858 Pin Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name H11 CS2 B12 VSSIO M2 VDD K7 TDI H10 CS3 A10 VSSIO J12 VDD G6 TDO H7 D0 A4 VSSIO E12 VDD B9 TIO0 G7 D1 A1 VSSIO A12 VDD C9 TIO1 F9 D2 A2 VSSIO B1 VDDIO D9 TIO2 F10 D3 M4 VSSIO H1 VDDIO B10 TIO3 F11 D4 M12 VSSIO M3 VDDIO J7 TMS E10 D5 A6 VSSIO M8 VDDIO L7 TRST D7 D6 G10 HA0 M11 VDDIO L11 TXD0 B7 D7 G11 HA1 H12 VDDIO C10 TXD1 E7 D8 G9 HA2 C12 VDDIO D4 WR F8 D9 C7 HACK A11 VDDIO H2 XTAL 56858 Technical Data, Rev. 6 58 Freescale Semiconductor Package and Pin-Out Information 56853 D X LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA Y Detail K M NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. E 0.20 MILLIMETERS DIM MIN MAX A --1.60 A1 0.27 0.47 A2 1.16 REF b 0.40 0.60 D 13.00 BSC E 13.00 BSC e 1.00 BSC S 0.50 BSC S 11X e 12 11 10 9 8 5 4 3 2 METALIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA 1 A B C D e 11X E 5 F G H S A 0.20 Z A2 J K A1 Z 4 0.12 Z L M 3 144X b 0.25 0.10 Z X Y DETAIL K ROTATED 90 ° CLOCKWISE VIEW M-M Z Figure 5-4 144-pin MAPBGA Mechanical Information Please see www.freescale.com for the most current case outline. 56858 Technical Data, Rev. 6 Freescale Semiconductor 59 Part 6 Design Considerations 6.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: TJ = TA + (PD x RθJA) Where: TA = ambient temperature °C RθJA = package junction-to-ambient thermal resistance °C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: RθJA = RθJC + RθCA Where: RθJA = package junction-to-ambient thermal resistance °C/W RθJC = package junction-to-case thermal resistance °C/W RθCA = package case-to-ambient thermal resistance °C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: • • • Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple. 56858 Technical Data, Rev. 6 60 Freescale Semiconductor Electrical Design Considerations As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 6.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation: • Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the board ground to each VSS (GND) pin. • The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDA/VSSA. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5 inch per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND. • • • • Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade capacitor such as a tantalum capacitor. Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. 56858 Technical Data, Rev. 6 Freescale Semiconductor 61 • • All inputs must be terminated (i.e., not allowed to float) using CMOS levels. Take special care to minimize noise levels on the VDDA and VSSA pins. • • When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device. Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but requires that TRST be asserted at power on. • 56858 Technical Data, Rev. 6 62 Freescale Semiconductor Electrical Design Considerations Part 7 Ordering Information Table 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 7-1 56858 Ordering Information Part Supply Voltage Pin Count Frequency (MHz) Order Number DSP56858 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 144 120 DSP56858FV120 DSP56858 1.8V, 3.3V MAP Ball Grid Array (MAPBGA) 144 120 DSP56858VF120 DSP56858 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 144 120 DSP56858FVE * Package Type *This package is RoHS compliant. 56858 Technical Data, Rev. 6 Freescale Semiconductor 63 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56858 Rev. 6 01/2007