DSPB56720CAG

Freescale Semiconductor Data Sheet: Technical Data Document Number: DSP56720EC Rev. 5, 02/2009 DSP56720/DSP56721 Symphony™ DSP56720/DSP56721 DSP56720 144-Pin LQFP 20 mm × 20 mm 0.5 mm pitch Multi-Core Audio Processors The Symphony DSP56720/DSP56721 Multi-Core Audio Processors are part of the DSP5672x family of programmable CMOS DSPs, designed using multiple DSP56300 24-bit cores. The DSP56720/DSP56721 devices are intended for automotive, consumer, and professional audio applications that require high performance for audio processing. In addition, the DSP56720 is ideally suited for applications that need the capability to expand memory off-chip or to interface to external parallel peripherals. Potential applications include A/V receivers, HD-DVD and Blu-Ray players, car audio/amplifiers, and professional recording equipment. The DSP56720/DSP56721 devices excel at audio processing for automotive and consumer audio applications requiring high MIPs. Higher MIPs and memory requirements are driven by the new high-definition audio standards (Dolby Digital+, Dolby TrueHD, DTS-HD, for example) and the desire to process multiple audio streams. 144-Pin LQFP 20 mm × 20 mm 0.5 mm pitch Communication (ICC), an External Memory Controller (EMC) to support SDRAM, and a Sony/Philips Digital Interface (S/PDIF). The DSP56720/DSP56721 offer 200 million instructions per second (MIPs) per core using an internal 200 MHz clock. The DSP56720/DSP56721 are high density CMOS devices with 3.3 V inputs and outputs. The DSP56720 device is slightly different than the DSP56721 device—the DSP56720 includes an external memory interface while the DSP56721 device does not. The DSP56720 block diagram is shown in Figure 1; the DSP56721 block diagram is shown in Figure 2. In addition, DSP56720/DSP56721 devices are optimal for the professional audio market requiring audio recording, signal processing, and digital audio synthesis. The DSP56720/DSP56721 processors provide a wealth of on-chip audio processing functions, via a plug and play software architecture system that supports audio decoding algorithms, various equalization algorithms, compression, signal generator, tone control, fade/balance, level meter/spectrum analyzer, among others. The DSP56720/DSP56721 devices also support various matrix decoders and sound field processing algorithms. With two DSP56300 cores, a single DSP56720 or DSP56721 device can replace dual-DSP designs, saving costs while meeting high MIPs requirements. Legacy peripherals from the previous DSP5636x/7x families are included, as well as a variety of new modules. Included among the new modules are an Asynchronous Sample Rate Converter (ASRC), Inter-Core Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009. All rights reserved. DSP56721 80-Pin LQFP 14 mm × 14 mm 0.65 mm pitch Table of Contents 1 2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package . .5 1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package . . .6 1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package . .7 1.4 Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .8 2.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . .9 2.3 Power Requirements . . . . . . . . . . . . . . . . . . . . .10 2.5 DC Electrical Characteristics . . . . . . . . . . . . . . .12 2.6 AC Electrical Characteristics . . . . . . . . . . . . . . .13 2.7 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.8 External Clock Operation. . . . . . . . . . . . . . . . . .13 2.9 Reset, Stop, Mode Select, and Interrupt Timing 15 2.10 Serial Host Interface (SHI) SPI Protocol Timing 18 2.11 Serial Host Interface (SHI) I2C Protocol Timing.24 3 4 5 6 7 2.12 Programming the SHI I2C Serial Clock . . . . . . 26 2.13 Enhanced Serial Audio Interface (ESAI) Timing 27 2.14 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.15 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.16 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.17 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . 35 2.18 Host Data Interface (HDI24) Timing . . . . . . . . . 35 2.19 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.20 EMC Timing (DSP56720 Only) . . . . . . . . . . . . 43 Functional Description and Application Information . . . . . . . 47 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.1 80-Pin Package Outline Drawing . . . . . . . . . . . . . . . . . 49 5.2 144-Pin Package Outline Drawing. . . . . . . . . . . . . . . . 51 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 2 Freescale Semiconductor DSP Core-0 On-Chip Memory P GPIO WDT_1 ESAI_3 DSP Core-1 ASRC On-Chip Memory Arbiter 8 Shared Bus 0 Y ESAI_2 TEC_1 SHI_1 Chip Config GPIO CGM Arbiter 9 X S/PDIF EMC GPIO WDT ESAI_1 ESAI TEC SHI EXTAL/XTAL P X Y Shared Bus 1 Arbiters 0–7 PCU / AGU / ALU DMA OnCE PCU / AGU / ALU OnCE Shared Memory 8 Kbytes Blocks 0–7 (64 Kbytes total) MODA0, MODB0, MODC0, MODD0 DMA MODA1, MODB1, MODC1, MODD1 2 JTAGs JTAG Figure 1. DSP56720 Block Diagram DSP Core-0 On-Chip Memory ASRC X GPIO WDT_1 ESAI_3 ESAI_2 TIMER_1 SHI_1 DSP Core-1 On-Chip Memory Arbiter 8 Shared Bus 0 P HDI24_1 GPIO SPDIF CGM Chip Config EXTAL/XTAL HDI24 GPIO WDT ESAI_1 ESAI TIMER SHI HDI24 Shared Bus 1 Y P X Y Arbiters 0–7 PCU / AGU / ALU DMA OnCE OnCE Shared Memory 8 Kbytes Blocks 0–7 (64 Kbytes total) MODA0, MODB0, MODC0, MODD0 2 JTAGs JTAG PCU / AGU / ALU DMA MODA1, MODB1, MODC1, MODD1 Figure 2. DSP56721 Block Diagram Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 3 1 Pin Assignments DSP56720 devices are available in one package type; DSP56721 devices are available in two package types. For the pin assignments of a specific device in a specific package, refer to Section 1.1, “Pinout for DSP56720 144-Pin Plastic LQFP Package,” through Section 1.3, “Pinout for DSP56721 144-Pin Plastic LQFP Package.” Table 1. Pin Assignments by Package Device Package See DSP56720 144-pin plastic LQFP Figure 3 on page 5 DSP56721 80-pin plastic LQFP Figure 4 on page 6 144-pin plastic LQFP Figure 5 on page 7 For more detailed information about signals, refer to the Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors Reference Manuall (DSP56720RM). Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 4 Freescale Semiconductor 1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 SCAN MODA0/IRQA MODB0/IRQB MODC0/PLOCK MODD0/PG1 FSR_3 SCKR_3 HCKR_3 SCKT_3 FST_3 HCKT_3 IO_GND IO_VDD CORE_GND CORE_VDD MODA1/IRQC MODB1/IRQD MODC1/NMI_1 MODD1/PG2 SDO2_2/SDI3_2 SDO3_2/SDI2_2 SDO4_2/SDI1_2 SDO5_2/SDI0_2 SDO2_3/SDI3_3 SDO3_3/SDI2_3 SDO4_3/SDI1_3 SDO5_3/SDI0_3 SS/HA2 HREQ/PH4 SCK/SCL MOSI/HA0 MISO/SDA SS_1/HA2_1 RESET CORE_GND CORE_VDD Figure 3 shows the pinout of the DSP56720 144-pin plastic LQFP package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DSP56720 144-Pin 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 IO_GND IO_VDD WDT PINIT/NMI TDO TDI TCK TMS SDO2_1/SDI3_1 SDO3_1/SDI2_1 SDO4_1/SDI1_1 SDO5_1/SDI0_1 CORE_GND CORE_VDD FSR SCKR HCKR SCKT FST HCKT SDO2/SDI3 SDO3/SDI2 SDO4/SDI1 SDO5/SDI0 SPDIFOUT1 SPDIFIN1 IO_GND IO_VDD EXTAL XTAL PLLP_GND PLLD_GND PLLD_VDD PLLA_GND PLLA_VDD PLLP_VDD LSYNC_IN LSYNC_OUT LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 CORE_VDD CORE_GND IO_VDD IO_GND LAD16 LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 IO_VDD IO_GND CORE_VDD CORE_GND LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 IO_GND IO_VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 CORE_VDD CORE_GND LALE LCS0 LCS1 LCS2 LCS3 LCS4 LCS5 LCS6 LCS7 IO_VDD IO_GND CORE_VDD CORE_GND LWE LOE LGPL5 LSDA10 LCKE LCLK LBCTL LSDWE LSDCAS LGTA LA0 LA1 LA2 IO_VDD IO_GND PLLP1_GND PLLP1_VDD PLLD1_GND PLLD1_VDD PLLA1_GND PLLA1_VDD Figure 3. DSP56720 144-Pin Package Pinout Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 5 1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package CORE_VDD MODA1/IRQC MODB1/IRQD MODC1/NMI_1 SS/HA2 HREQ/PH4 SCK/SCL MOSI/HA0 MISO/SDA SS_1/HA2_1 RESET CORE_GND CORE_VDD 73 72 71 70 69 68 67 66 65 64 63 62 61 IO_GND 76 IO_VDD MODC0/PLOCK 77 CORE_GND MODB0/IRQB 78 74 MODA0/IRQA 79 75 SCAN 80 Figure 4 shows the pinout of the DSP56721 80-pin plastic LQFP package. SDO2_3/SDI3_3 1 60 WDT SDO3_3/SDI2_3 2 59 PINIT/NMI SDO4_3/SDI1_3 3 58 TDO SDO5_3/SDI0_3 4 57 TDI IO_VDD 5 56 TCK IO_GND 6 55 TMS CORE_VDD 7 54 CORE_GND CORE_GND 8 53 CORE_VDD 52 SDO4/SDI1 51 SDO5/SDI0 SPDIFIN1/SDO2_2/SDI3_2 SPDIFOUT1/SDO3_2/SDI2_2 DSP56721 9 10 80-Pin 38 39 40 HCKT SDO2/SDI3 SDO3/SDI2 36 CORE_GND 37 35 CORE_VDD FST 34 PLLP_VDD IO_GND 41 33 PLLA_VDD 20 IO_VDD 42 GND 32 19 SCKT PLLA_GND GND 31 43 HCKR 18 30 PLLD_VDD GND SCKR 44 29 PLLD_GND 17 28 45 GND FSR 16 SDO5_1/SDI0_1 PLLP_GND GND 27 46 SDO4_1/SDI1_1 15 26 XTAL SCKT_3 CORE_GND 47 25 14 CORE_VDD EXTAL SCKR_3 24 48 SDO3_1/SDI2_1 IO_VDD 13 23 49 FSR_3 SDO2_1/SDI3_1 12 22 IO_GND SDO5_2/SDI0_2 21 50 FST_3 11 HCKT_3 SDO4_2/SDI1_2 Figure 4. DSP56721 80-Pin Package Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 6 Freescale Semiconductor 1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 SCAN MODA0/IRQA MODB0/IRQB MODC0/PLOCK MODD0/PG1 IO_GND IO_VDD CORE_GND CORE_VDD MODA1/IRQC MODB1/IRQD MODC1/NMI_1 MODD1/PG2 FSR_2 SCKR_2 SCKT_2 FST_2 SDO0_2 SDO1_2 IO_GND IO_VDD SDO0_3 SDO1_3 SS/HA2 HREQ/PH4 SCK/SCL MOSI/HA0 MISO/SDA SS_1/HA2_1 HREQ_1/PH4_1 SCK_1/SCL_1 MOSI_1/HA0_1 MISO_1/SDA_1 RESET CORE_GND CORE_VDD Figure 5 shows the pinout of the DSP56721 144-pin plastic LQFP package. DSP56721 144-Pin 37 38 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 IO_GND IO_VDD WDT PIINT/NMI TDO TDI TCK TMS SCKR_1 FSR_1 SCKT_1 FST_1 SDO0_1 SDO1_1 IO_GND IO_VDD CORE_GND CORE_VDD SDO0 SDO1 SDO4/SDI1 SDO5/SDI0 SPDIFOUT1/H12/HAD12 SPDIFIN1/H8/HAD8 HACK/HRRQ HOREQ/HTRQ IO_GND IO_VDD EXTAL XTAL PLLP_GND PLLD_GND PLLD_VDD PLLA_GND PLLA_VDD PLLP_VDD HAS/HA0 HA1/HA8 HA2/HA9 HRW/HRD HDS/HWR HCS/HA10 IO_VDD IO_GND FST_3 HCKT_3 SDO2_1/SDI3_1 SDO3_1/SDI2_1 CORE_VDD CORE_GND SDO4_1/SDI1_1 SDO5_1/SDI0_1 FSR SCKR HCKR SCKT IO_VDD IO_GND CORE_VDD CORE_GND FST HCKT SDO2/SDI3 SDO3/SDI2 IO_GND IO_VDD H0/HAD0 H1/HAD1 H2/HAD2 H3/HAD3 H4/HAD4 H5/HAD5 TIO0/H15/HAD15 PG18/HDI_SEL IO_GND TIO0_1/H18/HAD18 CORE_VDD CORE_GND SDO2_3/SDI3_3 SDO3_3/SDI2_3 SDO4_3/SDI1_3 SDO5_3/SDI0_3 IO_VDD IO_GND CORE_VDD CORE_GND SDO2_2/SDI3_2 SDO3_2/SDI2_2 SDO4_2/SDI1_2 SDO5_2/SDI0_2 HCKR_3 FSR_3 SCKR_3 SCKT_3 IO_VDD IO_GND H6/HAD6 H7/HAD7 SPDIFIN2/H9/HAD9 SPDIFIN3/H10/HAD10 SPDIFIN4/H11/HAD11 SPDIFOUT2/H13/HAD13 SPLOCK/H14/HAD14 GND GND GND GND GND Figure 5. DSP56721 144-Pin Package Pinout 1.4 Pin Multiplexing Many pins are multiplexed. For more about pin multiplexing, refer to the Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors Reference Manual (DSP56720RM). Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 7 2 Electrical Characteristics 2.1 Maximum Ratings Table 2 shows the maximum ratings. CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (for example, either GND or VDD). The suggested value for a pull-up or pull-down resistor is 4.7 kΩ. NOTE In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2. Maximum Ratings Rating1 Symbol Value1, 2 Unit VCORE_VDD, VPLLD_VDD –0.3 to + 1.26 V VPLLP_VDD, VIO_VDD, VPLLA_VDD, –0.3 to + 4.0 V Tr 10 ms Input Voltage per pin excluding VDD and GND VIN GND –0.3 to 5.5 V V Current drain per pin excluding VDD and GND (Except for pads listed below) I 12 mA Ilsync_out 16 mA LCLK Ilclk 16 mA LALE Iale 16 mA TDO IJTAG 24 mA TJ –40 to +100 °C Supply Voltage Maximum CORE_VDD power supply ramp time3 LSYNC_OUT Operating temperature range Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 8 Freescale Semiconductor Table 2. Maximum Ratings (Continued) Rating1 Symbol Value1, 2 Unit TSTG –65 to +150 °C ESD protected voltage (Human Body Model) — 2000 V ESD protected voltage (Charged Device) • All pins • Corner pins — Storage temperature V 500 750 Note: 1. GND = 0 V, TJ = –40° C to 100° C, CL = 50 pF 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3. If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneous operation. 2.2 Thermal Characteristics Table 3 provides the thermal characteristics for the device. Table 3. Thermal Characteristics Characteristic Natural Convection, Junction-to-ambient thermal resistance1,2 Board Type Symbol Single layer board (1s) Four layer board (2s2p) Junction-to-case thermal resistance3 — RθJA or θJA LQFP Values Unit 57 for 80 QFP 49 for 144 QFP °C/W 44 for 80 QFP 40 for 144 QFP °C/W RθJC or θJC 10 for 80 QFP 9 for 144 QFP °C/W Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2, Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJMA) Where: • • • • • TA = Ambient Temperature, °C θJMA= Package Thermal Resistance, Junction-to-Ambient, °C/W PD = PINT + PI/O PINT = IDD × VDD, Watts – Chip Internal Power PI/O = Power Dissipation on Input and Output Pins—User Determined For most applications, PI/O < PINT and can be ignored. PD can be calculated using the worst-case conditions of 1.1 V and 780 mA. See Table 4 for more information. To find TJ at 100° C, using the worst-case conditions and a four-layer board: Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 9 PD = 1.1 V × 625 mA = 0.6875 W TJ = 70 + (0.6875 × 40) = 97.5° C 2.3 Power Requirements To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins. IO_VDD External Schottky Diode Core_VDD Figure 6. Prevent High Current Conditions by Using External Schottky Diode If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead of Core_VDD, as shown in Figure 7. Core_VDD IO_VDD Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms, as shown in Figure 8. There are no power down requirement for the digital 1.0 V (CORE) and 3.3 V (IO). For the analog PLL power, the digital (IO) 3.3 V must be power up before the analog 3.3 V power. Similarly, for power down the digital (IO) 3.3 V must be power down after the analog power 3.3 V. This requirement is for avoiding possible leakage. Tr 1.0 V Core_VDD 0V Tr must be < 10 ms Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 10 Freescale Semiconductor 2.4 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula: I = C×V×f where Eqn. 1 C=node/pin capacitance V=voltage swing f=frequency of node/pin toggle Example 1. Power Consumption Example For a GPIO address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 150 MHz clock, toggling at its maximum possible rate (75 MHz), the current consumption is I = 50 x 10– 12 x 3.3 x 75 x 10 6 = 12.375mA Eqn. 2 The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following: • • Minimize the number of pins that are switching. Minimize the capacitive load on the pins. One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (for example, to compensate for measured board current not caused by the DSP). Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. I/MIPS = I/MHz = (ItypF2 - ItypF1)/(F2 - F1) where : Eqn. 3 ItypF2=current at F2 ItypF1=current at F1 F2=high frequency (any specified operating frequency) F1=low frequency (any specified operating frequency lower than F2) NOTE F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 11 2.5 DC Electrical Characteristics Table 4 shows the DC electrical characteristics. Table 4. DC Electrical Characteristics Characteristics Commercial Supply voltages: • Core (Core_VDD) • PLL (PLLD_VDD, PLLD1_VDD) Supply voltages: • I/O (IO_VDD) • PLL (PLLP_VDD, PLLP1_VDD) • PLL (PLLA_VDD, PLLA1_VDD) Automotive Supply voltages: • Core (Core_VDD) • PLL (PLLD_VDD, PLLD1_VDD) Supply voltages: • I/O (IO_VDD) • PLL (PLLP_VDD, PLLP1_VDD) • PLL (PLLA_VDD, PLLA1_VDD) Symbol Min Typ Max Unit VDD 0.9 1 1.1 V VDDIO 3.14 3.3 3.46 V VDD 0.95 1 1.05 V VDDIO 3.14 3.3 3.46 V Note: To avoid a high current condition and possible system damage, all 3.3 V supplies must rise before the 1.0 V supplies rise. Input low voltage VIL –0.3 — 0.8 V Input leakage current IIN — — ± 84 μA Clock pin Input Capacitance (EXTAL) CIN — 18 — pF High impedance (off-state) input current (@ 3.3 V or 0 V) ITSI –10 — 10 μA Output high voltage IOH = -12 mA LSYNC_OUT, LALE, LCLK Pins IOH = -16 mA, TDO Pin IOH = -24 mA VOH 2.4 — — V Output low voltage IOL = 12 mA LSYNC_OUT, LALE, LCLK Pins IOL = 16 mA, TDO Pins IOL = 24 mA VOL — — 0.4 V Internal pull-up resistor RPU 64 92 142 kΩ RPD 57 90 157 kΩ ICCI — 224 445 mA ICCW — 121 353 mA ICCS — 90 327 mA Internal pull-down resistor current1 Commercial Internal supply 200 MHz • In Normal mode • In Wait mode • In Stop mode2 (core only) at internal clock of Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 12 Freescale Semiconductor Table 4. DC Electrical Characteristics (Continued) Characteristics Automotive Symbol Min Typ Max Unit • In Normal Mode ICCI — 242 496 mA • In Wait Mode ICCW — 125 409 mA • In Stop mode ICCS — 107 376 mA CIN — — 10 pF Input capacitance Notes: 1. The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with V CORE_VDD = 1.0 V, VDD_IO = 3.3 V at TJ = 25° C. Maximum internal supply current is measured with VCORE_VDD = 1.10 V, V IO_VDD) = 3.4 V at TJ = 100°C. 2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). 2.6 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a V IL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56720/DSP56721 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. 2.7 Internal Clocks Internal clock characteristics are listed in Table 5. Table 5. Internal Clocks No. Characteristics Symbol Min Typ Max Unit 2 — 8 MHz 1 Comparison Frequency Fref 2 Input Clock Frequency Fin 3 PLL VCO Frequency 4 5 Frequency[1] Output Clock • with PLL enabled • with PLL disabled Duty Cycle Fvco Fref = Fin/NR Max = 200 MHz 200 Fout — — 400 40 MHz Fout= Fvco/NO Fout = Fin 200 200 50 Fvco = (Fin × NF)/NR MHz — 25 — — Condition 60 % Fvco= 200 MHz–400 MHz Notes: Fin = External frequency, NF = Multiplication Factor, NR = Predivision Factor, NO = Output Divider 2.8 External Clock Operation The DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in Figure 9. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 13 EXTAL Suggested component values: XTAL Fosc = 24.576 MHz R = 1 M ±10% C (EXTAL)= 18 pF C (XTAL) = 18 pF R C XTAL1 Calculations are for a 5 – 30 MHz crystal with the following parameters: • Shunt capacitance (C0) of 10 pF – 12 pF • Series resistance 40 Ohm • Drive level of 10 μW C Figure 9. Using the On-Chip Oscillator If the DSP56720/DSP56721 system clock is an externally supplied square wave voltage source, it is connected to EXTAL (Figure 10). When the external square wave source is connected to EXTAL, the XTAL pin is not used. VIH Midpoint EXTAL VIL ETH ETL 1 2 3 Note: ETC The midpoint is 0.5 (VIH + VIL). Figure 10. External Clock Timing Table 6 lists the clock operation. Table 6. Clock Operation No. 1 2 3 4 Characteristics Symbol Min Max Units Eth 16.67 2.5 100 inf ns Etl 16.67 2.5 100 inf ns EXTAL cycle time • With PLL disabled • With PLL enabled Etc 5 33.3 inf 500 ns Instruction cycle time • With PLL disabled • With PLL enabled Tc 5.00 5.00 inf 5120 ns EXTAL input high 1 (40% to 60% duty cycle) • Crystal oscillator • Square wave input EXTAL input low 1 (40% to 60% duty cycle) • Crystal oscillator • Square wave input Notes: 1. Measured at 50% of the input transition. 2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 14 Freescale Semiconductor 2.9 Reset, Stop, Mode Select, and Interrupt Timing Table 7 shows the reset, stop, mode select, and interrupt timing. Table 7. Reset, Stop, Mode Select, and Interrupt Timing Parameters No. 10 11 13 Characteristics Expression Min Max Unit — — 11 ns Required RESET • Power on, external clock generator, PLL disabled • Power on, external clock generator, PLL enabled 2 × TC 2 × TC 10 10 — — ns ns Syn reset deassert delay time • Minimum 2 × TC 10 — ns (2 x TC) + TLOCK 200 — us Delay from RESET assertion to all pins at reset value 3 duration4 • Maximum (PLL enabled) 14 Mode select setup time — 10.0 — ns 15 Mode select hold time — 12 — ns 16 Minimum edge-triggered interrupt request assertion width — 7 — ns 17 Minimum edge-triggered interrupt request deassertion width — 4 — ns 18 Delay from interrupt trigger to interrupt code execution 10 × TC + 4 54 — ns 19 Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)1, 2, 3 • PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0) (128 Kbytes × TC) 655 — μs 25 × TC 125 — ns • PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 = (128 Kbytes × TC) + TLOCK 0) 855 — μs (25 × TC) + TLOCK 200 — μs 10 × TC + 3.8 — 53.8 ns • PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) • PLL is not active during Stop and Stop delay is not enabled (OMR Bit 6 = 1) 20 • Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution1 21 Interrupt Requests Rate1 • ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1 12 × TC — 60.0 ns • DMA 8 × TC — 40.0 ns • IRQ, NMI (edge trigger) 8 × TC — 40.0 ns • IRQ (level trigger) 12 × TC — 60.0 ns Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 15 Table 7. Reset, Stop, Mode Select, and Interrupt Timing Parameters No. 22 Characteristics Expression Min Max Unit DMA Requests Rate • Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1 6 × TC — 30.0 ns • Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1 7 × TC — 35.0 ns • Timer, Timer_1 2 × TC — 10.0 ns • IRQ, NMI (edge trigger) 3 × TC — 15.0 ns Notes: 1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. 2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings. For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 μs. 3. Periodically sampled and not 100% tested. 4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. Figure 11 shows the reset timing diagram. VIH RESET 11 13 10 All Pins Reset Value Figure 11. Reset Timing Diagram Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 16 Freescale Semiconductor Figure 12 shows the external fast interrupt timing diagram. a) First Interrupt Instruction Execution IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 19 18 b) General Purpose I/O General Purpose I/O 20 IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 Figure 12. External Fast Interrupt Timing Diagram Figure 13 shows the negative edge-triggered external interrupt timing diagram. IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 16 IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 17 Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered) Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 17 Figure 14 shows the MODE select set up and hold timing diagram. VIH RESET 14 15 MODA, MODB, MODC, MODD, PINIT VIH VIH VIL VIL IRQA, IRQB, IRQC,IRQD, NMI Figure 14. MODE Select Set Up and Hold Timing Diagram 2.10 Serial Host Interface (SHI) SPI Protocol Timing Table 8 shows the SHI SPI protocol timing parameters and Figure 15 through Figure 18 show the timing diagrams. Table 8. Serial Host Interface SPI Protocol Timing Parameters No. 23 Characteristics1,3,4 Minimum serial clock cycle = tSPICC(min) Mode Filter Mode Expression Min Max Unit Master Bypassed 10 × TC + 9 59.0 — ns Very Narrow 10 × TC + 9 59.0 — ns Narrow 10 × TC + 133 183.0 — ns Wide 10 × TC + 333 373.0 — ns Bypassed 2.0 × TC + 19.6 59.2 — ns Very Narrow 2.0 × TC + 19.6 59.2 — ns Narrow 2.0 × TC + 86.6 193.2 — ns Wide 2.0 × TC + 186.6 393.2 — ns Bypassed — — 0 ns Very Narrow — — 10 ns Narrow — — 50 ns Wide — — 100 ns Bypassed 0.5 × (tSPICC) 29.5 — ns Very Narrow 0.5 × (tSPICC) 29.5 — ns Narrow 0.5 × (tSPICC) 91.5 — ns Wide 0.5 × (tSPICC) 186.5 — ns Bypassed 2.0 × TC + 19.6 29.6 — ns Very Narrow 2.0 × TC + 19.6 29.6 — ns Narrow 2.0 × TC + 86.6 96.6 — ns Wide 2.0 × TC + 186.6 196.6 — ns Slave XX Tolerable Spike width on data or clock in 24 Serial clock high period — Master Slave Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 18 Freescale Semiconductor Table 8. Serial Host Interface SPI Protocol Timing Parameters (Continued) Characteristics1,3,4 No. 25 Serial clock low period Mode Filter Mode Expression Min Max Unit Master Bypassed 0.5 × (tSPICC) 29.5 — ns Very Narrow 0.5 × (tSPICC) 29.5 — ns Narrow 0.5 × (tSPICC 91.5 — ns Wide 0.5 × (tSPICC) 186.5 — ns Bypassed 2.0 × TC + 19.6 29.6 — ns Very Narrow 2.0 × TC + 19.6 29.6 — ns Narrow 2.0 × TC + 86.6 96.6 — ns Wide 2.0 × TC + 186.6 196.6 — ns Slave 26 Serial clock rise/fall time Master Slave — — — — — — — 5 ns ns 27 SS assertion to first SCK edge Slave Bypassed 2.0 × TC+15 25 — ns Very Narrow 2.0 × TC+5 15 — ns Narrow — 0 — ns Wide — 0 — ns Bypassed — 10 — ns Very Narrow — 0 — ns Narrow — 0 — ns Wide — 0 — ns Bypassed — 12 — ns Very Narrow — 22 — ns Narrow — 100 — ns Wide — 200 — ns Bypassed — 0 — ns Very Narrow — 0 — ns Narrow — 0 — ns Wide — 0 — ns Bypassed 3.0 × TC 15 — ns Very Narrow 3.0 × TC + 25 40 — ns Narrow 3.0 × TC + 55 70 — ns Wide 3.0 × TC + 85 100.0 — ns Slave — — 5 — ns Slave — — — 9 ns CPHA = 0 CPHA = 1 28 29 30 31 32 Slave Last SCK edge to SS not asserted Data input valid to SCK edge (data input set-up time) SCK last sampling edge to data input not valid SS assertion to data out active SS deassertion to data high impedance2 Slave Master /Slave Master /Slave Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 19 Table 8. Serial Host Interface SPI Protocol Timing Parameters (Continued) No. 33 34 Characteristics1,3,4 SCK edge to data out valid (data out delay time) SCK edge to data out not valid (data out hold time) Mode Filter Mode Expression Min Max Unit Master /Slave Bypassed 3.0 × TC + 30 — 45 ns Very Narrow 3.0 × TC + 95 — 110 ns Narrow 3.0 × TC + 120 — 135 ns Wide 3.0 × TC + 210 — 225 ns Bypassed 2.0 × TC 10 — ns Very Narrow 2.0 × TC + 5 15 — ns Narrow 2.0 × TC + 45 55 — ns Wide 2.0 × TC + 95 105 — ns Master /Slave 35 SS assertion to data out valid (CPHA = 0) Slave — — — 14.0 ns 36 First SCK sampling edge to HREQ output deassertion Slave Bypassed 3.0 × TC + 30 45 — ns Very Narrow 3.0 × TC + 40 55 — ns Narrow 3.0 × TC + 80 95 — ns Wide 3.0 × TC + 130 145 — ns Bypassed 4.0 × TC + 30 50.0 — ns Very Narrow 4.0 × TC + 40 60.0 — ns Narrow 4.0 × TC + 80 100.0 — ns Wide 4.0 × TC + 130 150.0 — ns 37 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave 38 SS deassertion to HREQ output not deasserted (CPHA = 0) Slave — 3.0 × TC + 30 45.0 — ns 39 SS deassertion pulse width (CPHA = 0) Slave — 2.0 × TC 10.0 — ns 40 HREQ in assertion to first SCK edge Master Bypassed 0.5 × TSPICC + 3.0 × TC + 5 49.5 — ns Very Narrow 0.5 × TSPICC + 3.0 × TC + 5 49.5 — ns Narrow 0.5 × TSPICC + 3.0 × 111.5 TC + 5 — ns Wide 0.5 × TSPICC + 3.0 × 206.5 TC + 5 — ns Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 20 Freescale Semiconductor Table 8. Serial Host Interface SPI Protocol Timing Parameters (Continued) No. Characteristics1,3,4 Mode Filter Mode Expression Min Max Unit 41 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) Master — — 0 — ns 42 First SCK edge to HREQ in not asserted (HREQ in hold time) Master — — 0 — ns 43 HREQ assertion width Master — 3.0 × TC 15 — ns Notes: 1.V CORE_VDD = 1.0± 0.10 V; T J = –40°C to 100°C; CL = 50 pF. 2. Pejriodically sampled, not 100% tested. 3. All times assume noise free inputs. 4. All times assume internal clock frequency of 200 MHz. 5. SHI_1 specs match those of SHI. SS (Input) 25 23 24 26 26 SCK (CPOL = 0) (Output) 23 24 26 25 26 SCK (CPOL = 1) (Output) 29 30 MISO (Input) LSB Valid MSB Valid 34 33 MOSI (Output) 30 29 MSB LSB 40 42 HREQ (Input) 43 Figure 15. SPI Master Timing Diagram (CPHA = 0) Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 21 SS (Input) 25 23 24 26 26 SCK (CPOL = 0) (Output) 24 23 26 25 26 SCK (CPOL = 1) (Output) 29 29 30 MISO (Input) 30 MSB Valid LSB Valid 33 MOSI (Output) 34 MSB LSB 40 41 42 HREQ (Input) 43 Figure 16. SPI Master Timing Diagram (CPHA = 1) Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 22 Freescale Semiconductor SS (Input) 25 23 24 26 28 26 39 SCK (CPOL = 0) (Input) 27 23 24 26 25 26 SCK (CPOL = 1) (Input) 35 33 34 31 MISO (Output) 34 32 MSB LSB 29 29 30 MOSI (Input) MSB Valid 30 LSB Valid 36 38 HREQ (Output) Figure 17. SPI Slave Timing Diagram (CPHA = 0) Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 23 SS (Input) 25 23 24 26 28 26 SCK (CPOL = 0) (Input) 27 24 26 25 26 SCK (CPOL = 1) (Input) 33 33 34 32 31 MISO (Output) MSB LSB 29 29 30 30 MSB Valid MOSI (Input) LSB Valid 37 36 HREQ (Output) Figure 18. SPI Slave Timing Diagram (CPHA = 1) 2.11 Serial Host Interface (SHI) I2C Protocol Timing Table 9 lists the SHI I2C protocol timing parameters and Figure 19 shows the timing diagram. Table 9. SHI I2C Protocol Timing Parameters Standard I2C No. Characteristics1,2,3,4,5 Tolerable Spike Width on SCL or SDA Filters Bypassed Very Narrow Filters enabled Narrow Filters enabled Wide Filters enabled. Symbol/ Expression Standard Fast-Mode Unit Min Max Min Max — — — — 0 10 50 100 — — — — 0 10 50 100 ns ns ns ns — 44 SCL clock frequency FSCL — 100 — 400 kHz 44 SCL clock cycle TSCL 10 — 2.5 — μs 45 Bus free time TBUF 4.7 — 1.3 — μs 46 Start condition set-up time TSUSTA 4.7 — 0.6 — μs 47 Start condition hold time THD;STA 4.0 — 0.6 — μs Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 24 Freescale Semiconductor Table 9. SHI I2C Protocol Timing Parameters (Continued) Standard I2C No. Characteristics1,2,3,4,5 48 SCL low period 49 SCL high period 50 SCL and SDA rise time7 time7 Symbol/ Expression Standard Fast-Mode Unit Min Max Min Max TLOW 4.7 — 1.3 — μs THIGH 4.0 — 1.3 — μs TR — 1000 — 300 ns TF — 5.0 — 5.0 ns 51 SCL and SDA fall 52 Data set-up time TSU;DAT 250 — 100 — ns 53 Data hold time THD;DAT 0.0 — 0.0 0.9 μs 54 DSP clock frequency • Filters bypassed • Very Narrow filters enabled • Narrow filters enabled • Wide filters enabled 10.6 10.6 11.8 13.1 — — — — 28.5 28.5 39.7 61.0 — — — — MHz MHz MHz MHz FOSC 55 SCL low to data out valid TVD;DAT — 3.4 — 0.9 μs 56 Stop condition setup time TSU;STO 4.0 — 0.6 — μs 57 HREQ in deassertion to last SCL edge (HREQ in set-up time) tSU;RQI 0.0 — 0.0 — ns 58 First SCL sampling edge to HREQ output deassertion 2 • Filters bypassed • Very Narrow filters enabled • Narrow filters enabled • Wide filters enabled — — — — 50.0 70.0 250.0 150.0 — — — — 50.0 70.0 150.0 250.0 ns ns ns ns 40 50 90 140 — — — — 40 50 90 140 — — — — ns ns ns ns 59 Last SCL edge to HREQ output not deasserted2 • Filters bypassed • Very Narrow filters enabled • Narrow filters enabled • Wide filters enabled TNG;RQO 4 × TC + 30 4 × TC + 50 4 × TC + 130 4 × TC + 230 TAS;RQO 2 × TC + 30 2 × TC + 40 2 × TC + 80 2 × TC + 130 Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 25 Table 9. SHI I2C Protocol Timing Parameters (Continued) Standard I2C No. 60 61 Symbol/ Expression Characteristics1,2,3,4,5 HREQ in assertion to first SCL edge • Filters bypassed • Very Narrow filters enabled • Narrow filters enabled • Wide filters enabled TAS;RQI First SCL edge to HREQ is not asserted (HREQ in hold time.) tHO;RQI Standard Fast-Mode Unit Min Max Min Max 4327 4317 4282 4227 — — — — 927 917 877 827 — — — — ns ns ns ns 0.0 — 0.0 — ns Notes: 1. VCORE_VDD = 1.00± 0.10 V; TJ = –40°C to 100°C; CL = 50 pF. 2. Pull-up resistor: R P (min) = 1.5kΩ. 3. Capacitive load: C b (max) = 50 pF. 4. All times assume noise free inputs. 5. All times assume internal clock frequency of 200 MHz. 6. SHI_1 specs match those of SHI. 7. Master Mode 2.12 Programming the SHI I2C Serial Clock The programmed serial clock cycle, T I2CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I2CCP is T I2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 — HRS) + 1)] Eqn. 4 where — HRS is the pre scaler rate select bit. When HRS is cleared, the fixed divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed. — HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 × TC (if HDM[7:0] = $02 and HRS = 1) Eqn. 5 4096 × TC (if HDM[7:0] = $FF and HRS = 0) Eqn. 6 to The programmed serial clock cycle (TI2CCP ) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Equation 4. TI2CCP + 3 × TC + 45ns + TR (Nominal, SCL Serial Clock Cycle (TSCL) generated as master) Eqn. 7 Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 26 Freescale Semiconductor 44 46 49 48 SCL 50 53 51 45 52 SDA Stop MSB Start 47 LSB 58 ACK 55 61 Stop 56 57 60 59 HREQ Figure 19. I2C Timing Diagram 2.13 Enhanced Serial Audio Interface (ESAI) Timing Table 10 lists the ESAI timing parameters and Figure 20 through Figure 23 show the timing diagrams. Table 10. Enhanced Serial Audio Interface Timing Parameters Characteristics1, 3, 4 No. Symbol Expression5 Min Max Condition2 Unit tSSICC 4 × Tc 4 × Tc 20.0 20.0 — — i ck i ck 62 Clock cycle5 63 Clock high period • For internal clock — 2 × Tc 10 — — • For external clock — 2 × Tc 10 — — Clock low period • For internal clock — 2 × Tc 10 — — • For external clock — 2 × Tc 10 — — 65 SCKR rising edge to FSR out (bl) high — — — — 17.0 7.0 x ck i ck a ns 66 SCKR rising edge to FSR out (bl) low — — — — 17.0 7.0 x ck i ck a ns 67 SCKR rising edge to FSR out (wr) high6 — — — — 19.0 9.0 x ck i ck a ns 68 SCKR rising edge to FSR out (wr) low6 — — — — 19.0 9.0 x ck i ck a ns 69 SCKR rising edge to FSR out (wl) high — — — — 16.0 6.0 x ck i ck a ns 70 SCKR rising edge to FSR out (wl) low — — — — 17.0 7.0 x ck i ck a ns 64 ns ns ns Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 27 Table 10. Enhanced Serial Audio Interface Timing Parameters (Continued) No. Characteristics1, 3, 4 Symbol Expression5 Min Max Condition2 Unit 71 Data in setup time before SCKR (SCK in synchronous mode) falling edge — — 5 19.0 — — x ck i ck ns 72 Data in hold time after SCKR falling edge — — 3.5 9.0 — — x ck i ck ns 73 FSR input (bl, wr) high before SCKR falling edge 6 — — 2.0 12.0 — — x ck i ck a ns 74 FSR input (wl) high before SCKR falling edge — — 2.0 12.0 — — x ck i ck a ns 75 FSR input hold time after SCKR falling edge — — 2.5 8.5 — — x ck i ck a ns 76 Flags input setup before SCKR falling edge — — 0.0 19.0 — — x ck i ck s ns 77 Flags input hold time after SCKR falling edge — — 6.0 0.0 — — x ck i ck s ns 78 SCKT rising edge to FST out (bl) high — — — — 14 8.0 x ck i ck ns 79 SCKT rising edge to FST out (bl) low — — — — 20.0 10.0 x ck i ck ns 80 SCKT rising edge to FST out (wr) high6 — — — — 20.0 10.0 x ck i ck ns 81 SCKT rising edge to FST out (wr) low6 — — — — 22.0 12.0 x ck i ck ns 82 SCKT rising edge to FST out (wl) high — — — — 14 9.0 x ck i ck ns 83 SCKT rising edge to FST out (wl) low — — — — 14 10.0 x ck i ck ns 84 SCKT rising edge to data out enable from high impedance — — — — 22.0 17.0 x ck i ck ns 85 SCKT rising edge to transmitter #0 drive enable assertion — — — — 17.0 11.0 x ck i ck ns 86 SCKT rising edge to data out valid — — — — 13 13.0 x ck i ck ns 87 SCKT rising edge to data out high impedance7 — — — — 13 16.0 x ck i ck ns 88 SCKT rising edge to transmitter #0 drive enable deassertion7 — — — — 14.0 9.0 x ck i ck ns 89 FST input (bl, wr) setup time before SCKT falling edge6 — — 2.0 18.0 — — x ck i ck ns 90 FST input (wl) setup time before SCKT falling edge — — 2.0 18.0 — — x ck i ck ns 91 FST input hold time after SCKT falling edge — — 4.0 5.0 — — x ck i ck ns Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 28 Freescale Semiconductor Table 10. Enhanced Serial Audio Interface Timing Parameters (Continued) No. Characteristics1, 3, 4 Symbol Expression5 Min Max Condition2 Unit 92 FST input (wl) to data out enable from high impedance — — — 21.0 — ns 93 FST input (wl) to transmitter #0 drive enable assertion — — — 14.0 — ns 94 Flag output valid after SCKT rising edge — — — — 14.0 9.0 x ck i ck ns 95 HCKR/HCKT clock cycle — 2 × TC 10 — — ns 96 HCKT input rising edge to SCKT output — — — 18.0 — ns 97 HCKR input rising edge to SCKR output — — — 18.0 — ns Notes: 1. VCORE_VDD = 1.00 ± 0.10 V; T J = –40°C to 100°C; CL = 50 pF. 2. i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (Asynchronous implies that SCKT and SCKR are two different clocks.) i ck s = internal clock, synchronous mode (Synchronous implies that SCKT and SCKR are the same clock.) 3. bl = bit length wl = word length wr = word length relative 4. SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register. 6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 7. Periodically sampled and not 100% tested. 8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 29 62 63 64 SCKT (Input/Output) 78 79 FST (Bit) Out 82 83 FST (Word) Out 86 86 84 87 First Bit Data Out Last Bit 93 Transmitter #0 Drive Enable (Internal Signal) 89 85 88 91 FST (Bit) In 92 91 90 FST (Word) In 94 See Note Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. Figure 20. ESAI Transmitter Timing Diagram Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 30 Freescale Semiconductor 62 63 64 SCKR (Input/Output) 65 66 FSR (Bit) Out 69 70 FSR (Word) Out 72 71 Data In First Bit Last Bit 75 73 FSR (Bit) In 74 75 FSR (Word) In 76 77 Flags In Figure 21. ESAI Receiver Timing Diagram HCKT SCKT (Output) 95 96 Figure 22. ESAI HCKT Timing Diagram Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 31 HCKR 95 SCKR (Output) 97 Figure 23. ESAI HCKR Timing 2.14 Timer Timing Table 11 lists the timer timing parameters and Figure 24 shows the timing diagram. Table 11. Timer Timing Parameters No. Characteristics Expression Unit Min Max 98 TIO Low 2 × TC + 2.0 12.0 — ns 99 TIO High 2 × TC + 2.0 12.0 — ns Notes: 1. VCORE_VDD = 1.00 V ± 0.10 V; T J = –40°C to 100°C, CL = 50 pF 2. TIMER_1 specs match those of TIMER TIO 98 99 Figure 24. TIO Timer Event Input Restrictions Diagram 2.15 GPIO Timing Table 12 lists the general purpose input and output (GPIO) timing and Figure 25 shows the timing diagram. Table 12. GPIO Timing Parameters No. 100 101 102 Characteristics1 Fsys edge to GPIO out valid (GPIO out delay time)2 Fsys edge to GPIO out not valid (GPIO out hold time)2 Fsys edge to GPIO in not valid (GPIO in hold 104 Minimum GPIO pulse high width Min Max Unit — — 7 ns — — 7 ns 2 — 2 — ns time)2 — 0 — ns 2 × TC 10 — ns Fsys In valid to EXTAL edge (GPIO in set-up time) 103 Expression Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 32 Freescale Semiconductor Table 12. GPIO Timing (Continued)Parameters (Continued) Characteristics1 No. Expression Min Max Unit 2 × TC 10 — ns 105 Minimum GPIO pulse low width 106 GPIO out rise time — — 13.0 ns 107 GPIO out fall time — — 13.0 ns Notes: VCORE_VDD = 1.0 V ± 0.10 V; TJ = –40°C to 100°C; C L = 50 pF Fsys 100 101 GPIO (Output) 102 GPIO Input) 103 Valid GPIO (Output) 104 105 106 107 Figure 25. GPIO Timing Diagram 2.16 JTAG Timing Table 13 lists the joint test action group (JTAG) timing parameters, and Figure 26 through Figure 28 show the timing diagrams. Table 13. JTAG Timing Parameters All Frequencies No. Characteristics Unit Min Max — 10.0 MHz 108 TCK frequency of operation (1/(TC × 3); maximum 10 MHz) 109 TCK cycle time in Crystal mode 100.0 — ns 110 TCK clock pulse width measured at 1.65 V 50.0 — ns 111 TCK rise and fall times — 3.0 ns 112 Boundary scan input data setup time 15.0 — ns 113 Boundary scan input data hold time 24.0 — ns 114 TCK low to output data valid — 40.0 ns 115 TCK low to output high impedance — 40.0 ns Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 33 Table 13. JTAG Timing Parameters (Continued) All Frequencies No. Characteristics Unit Min Max 116 TMS, TDI data setup time 5.0 — ns 117 TMS, TDI data hold time 25.0 — ns 118 TCK low to TDO data valid — 44.0 ns 119 TCK low to TDO high impedance — 44.0 ns Notes: 1. VCORE_VDD = 1.0 V ± 0.10 V; TJ = –40°C to 100°C , CL = 50 pF 2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. 109 TCK (Input) VIH 110 110 VM VM VIL 111 111 Figure 26. Test Clock Input Timing Diagram TCK (Input) VIH VIL 112 Data Inputs 113 Input Data Valid 114 Data Outputs Output Data Valid 115 Data Outputs 114 Data Outputs Output Data Valid Figure 27. Debugger Port Timing Diagram Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 34 Freescale Semiconductor VIH TCK (Input) VIL 117 116 TDI TMS (Input) Input Data Valid 118 TDO (Output) Output Data Valid 119 TDO (Output) 118 TDO (Output) Output Data Valid Figure 28. Test Access Port Timing Diagram 2.17 Watchdog Timer Timing Table 14 lists the watchdog timer timing. Table 14. Watchdog Timer Timing Parameters No. 2.18 Characteristics Expression Min Max Unit 120 Delay from time-out to fall of WDT, WDT_1 2 × Tc 10.0 — ns 121 Delay from timer clear to rise of WDT, WDT_1 2 × Tc 10.0 — ns Host Data Interface (HDI24) Timing The HDI24 module is only on the DSP56721 device; the DSP56720 device does not have a HDI24 module. Also, only 16 bits of the HDI24 interface are pinned out on the DSP56721 device. Table 15 lists HDI24 timing and Figure 29 through Figure 35 show the timing diagrams. Table 15. HDI24 Timing Parameters No. Characteristics 2 317 Read data strobe assertion width3 HACK read assertion width 318 Read data strobe deassertion width3 HACK read deassertion width 319 Read data strobe deassertion width3 after “Last Data Register” reads4,5, or between two consecutive CVR, ICR, or ISR reads6 4,5 HACK deassertion width after “Last Data Register” reads 200 MHz Expression Unit Min Max TC + 9.9 14.9 — ns — 9.9 — ns 2 × TC + 6.6 16.6 — ns Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 35 Table 15. HDI24 Timing Parameters (Continued) 200 MHz Characteristics2 No. Expression Unit Min Max — 13.2 — ns 2 × TC + 6.6 16.6 — ns • after IVR writes, or • after TXH:TXM writes (with HBE=0), or • after TXL:TXM writes (with HBE=1) — 16.5 — — 322 HAS assertion width — 9.9 — ns 323 HAS deassertion to data strobe assertion8 — 0.0 — ns 324 Host data input setup time before write data strobe deassertion7 Host data input setup time before HACK write deassertion — 9.9 — ns 325 Host data input hold time after write data strobe deassertion7 Host data input hold time after HACK write deassertion — 3.3 — ns 326 Read data strobe assertion to output data active from high impedance3 HACK read assertion to output data active from high impedance — 5.9 — ns 327 Read data strobe assertion to output data valid3 HACK read assertion to output data valid — — 29.6 ns 328 Read data strobe deassertion to output data high impedance3 HACK read deassertion to output data high impedance — — 9.9 ns 329 Output data hold time after read data strobe deassertion Output data hold time after HACK read deassertion — 3.3 — ns 330 HCS assertion to read data strobe deassertion TC + 9.9 14.9 — ns — 9.9 — ns 320 Write data strobe assertion width7 HACK write assertion width 321 Write data strobe deassertion width7 HACK write deassertion width • after ICR, CVR and “Last Data Register” writes4 3 3 7 331 HCS assertion to write data strobe deassertion 332 HCS assertion to output data valid — — 19.1 ns 333 HCS hold time after data strobe deassertion8 — 0.0 — ns 334 Address (AD7—AD0) setup time before HAS deassertion (HMUX=1) — 4.7 — ns 335 Address (AD7—AD0) hold time after HAS deassertion (HMUX=1) — 3.3 — ns 336 A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W setup time before data strobe assertion8 • Read — 0 — ns • Write — 4.7 — 337 A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W hold time after data strobe deassertion8 — 3.3 — ns 338 Delay from read data strobe deassertion to host request assertion for “Last Data Register” read3, 4, 9 TC 5.0 — ns Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 36 Freescale Semiconductor Table 15. HDI24 Timing Parameters (Continued) Characteristics2 No. 200 MHz Expression Unit Min Max 2 × TC 10.0 — ns 339 Delay from write data strobe deassertion to host request assertion for “Last Data Register” write4, 7, 9 340 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD = 0)4, 8, 9 — — 19.1 ns 341 Delay from data strobe assertion to host request deassertion for “Last Data Register” read or write (HROD = 1, open drain Host Request)4, 8, 9, 10 — — 300.0 ns 342 Delay from DMA HACK deassertion to HOREQ assertion ns • For “Last Data Register” read4 2 × TC + 19.1 29.1 — • For “Last Data Register” write4 1 × TC + 19.1 24.1 — • For other cases — 0.0 — 343 Delay from DMA HACK assertion to HOREQ deassertion 4 • HROD = 0 — — 20.2 ns 344 Delay from DMA HACK assertion to HOREQ deassertion for “Last Data Register” read or write • HROD = 1, open drain Host Request4, 10 — — 300.0 ns Notes: 1. In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable. 2. VCC = 1.0 V ± 10%; TJ = —40°C to +100°C; CL = 50 pF. 3. The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. 4. The “last data register” is the register at address $7, which is the last location to be read or written in data transfers. 5. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal. 6. This timing is applicable only if two consecutive reads from one of these registers are executed. 7. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 8. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode. 9. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 10. In this calculation, the host request signal is pulled up by a 4.7 kW resistor in the open-drain mode. 11. HDI24_1 specs match those of HDI24. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 37 317 318 HACK 328 327 329 326 HD23–HD0 HOREQ Figure 29. HDI24 Host Interrupt Vector Register (IVR) Read Timing Diagram HA0–HA2 336 337 333 330 HCS 317 HRD, HDS 318 328 332 319 327 329 326 HD0–HD23 340 338 341 HOREQ, HRRQ, HTRQ Figure 30. HDI24 Read Timing Diagram, Non-Multiplexed Bus Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 38 Freescale Semiconductor HA0–HA2 337 336 331 333 HCS 320 HWR, HDS 321 324 325 HD0–HD23 340 339 341 HOREQ, HRRQ, HTRQ Figure 31. HDI24 Write Timing Diagram, Non-Multiplexed Bus Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 39 HA8–HA10 336 337 322 HAS 323 317 HRD, HDS 334 318 335 319 327 328 329 HAD0–HAD23 Address Data 326 340 338 341 HOREQ, HRRQ, HTRQ Figure 32. HDI24 Read Timing Diagram, Multiplexed Bus Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 40 Freescale Semiconductor HA8–HA10 336 322 HAS 323 320 HWR, HDS 334 324 321 335 HAD0–HAD23 325 Address Data 340 339 341 HOREQ, HRRQ, HTRQ Figure 33. HDI24 Write Timing Diagram, Multiplexed Bus HOREQ (Output) 342 343 344 320 HACK (Input) 321 TXH/M/L Write 324 325 H0–H23 (Input) Data Valid Figure 34. HDI24 Host DMA Write Timing Diagram Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 41 HOREQ (Output) 343 342 342 318 317 RXH Read HACK (Input) 327 328 326 H0-H23 (Output) 329 Data Valid Figure 35. HDI24 Host DMA Read Timing Diagram 2.19 S/PDIF Timing Table 16 lists the Sony/Philips Digital Interconnect Format (S/PDIF) timing parameters and Figure 36 and Figure 37 show the timing diagrams. Table 16. S/PDIF Timing Parameters All Frequency Characteristics Symbol Unit Min Max — — 0.7 ns SPDIFOUT1,SPDIFOUT2 output (Load = 50 pf) • Skew • Transition Risng • Transition Falling — — — — — — 1.5 24.2 31.3 ns SPDIFOUT1, SPDIFOUT2 output (Load = 30 pf) • Skew • Transition Risng • Transition Falling — — — — — — 1.5 13.6 18.0 ns SRCK period srckp 40.0 — ns SRCK high period srckph 16.0 — ns SRCK low period srckpl 16.0 — ns STCLK period stclkp 40.0 — ns STCLK high period stclkph 16.0 — ns STCLK low period stclkpl 16.0 — ns SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew: asynchronous inputs, no specs apply Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 42 Freescale Semiconductor srckp srckpl srckph VM VM SRCK (Output) Figure 36. S/PDIF SRCK Timing Diagram stclkp stclkpl stclkph VM VM STCLK (Input) Figure 37. S/PIDF STCLK Timing Diagram 2.20 EMC Timing (DSP56720 Only) The DSP56721 device does not have an EMC module. For EMC timing parameters in DSP56720 devices, see Table 17, through Table 19; for timing diagrams, see Figure 38 through Figure 40. Table 17. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2) Parameter Symbol Min Max Unit Tclk 10 — ns Tclk_skew — 160 ps Input setup to LSYNC_IN (except LGTA/LUPWAIT) Tin_s 3 — ns Input hold from LSYNC_IN (except LGTA/LUPWAIT) Tin_h 2 — ns LGTA valid time Tgta 12 — ns LUPWAIT valid time Tupwait 12 — ns LALE negedge to LAD(address phase) invaild (address latch hold time) Tale_h 3 — ns Tale 3.8 — ns Output setup from LSYNC_IN (except LAD[23:0] and LALE) Tout_s 4 — ns Output hold from LSYNC_IN (except LAD[23:0] and LALE) Tout_h 2 — ns LAD[23:0] output setup from LSYNC_IN Tad_s 3.5 — ns LAD[23:0] output hold from LSYNC_IN Tad_h 1.5 — ns LSYNC_IN to output high impedance for LAD[23:0] Tad_z — 4.3 ns LCLK cycle time LCLK skew to LSYNC_OUT LALE valid time Chapter 22, “External Memory Controller (EMC),” in the Symphony DSP56720/DSP56721 Multi-Core Audio Processors Reference Manual explains in detail the interfacing and features of EMC. The applicable sections are as follows: • • Section 22.4.4.3, “UPM Signal Timing” Section 22.4.4.7, “Memory System Interface Example Using UPM” Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 43 Tclk LCLK Tclk_skew LSYNC_OUT Tsync_in_skew LSYNC_IN Tin_s Tin_h LAD[23:0] (data) asynchronous input Tgta LGTA Tupwait asynchronous input LUPWAIT Tout_s Output Signals Tout_h LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0] Tad_z Tad_s Tad_h LAD[23:0] Tale Tale_h LALE Figure 38. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV] = 2) Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 44 Freescale Semiconductor Table 18. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4) Parameter Symbol Min Max Unit Tclk 20 — ns Tin_s 8 — ns Tin_h -1 — ns Tgta 22 — ns LUPWAIT valid time Tupwait 22 — ns LALE negedge to LAD (address phase) invalid (address latch hold time) Tale_h 4 — ns Tale 14 — ns Output setup from LCLK (except LAD[23:0] and LALE) Tout_s 9 — ns Output hold from LCLK (except LAD[23:0] and LALE) Tout_h 8 — ns LAD[23:0] output setup from LCLK Tad_s 8 — ns LAD[23:0] output hold from LCLK Tad_h 7 — ns LCLK to output high impedance for LAD[23:0] Tad_z — 8.1 ns LCLK cycle time Input setup to LCLK (except LGTA/LUPWAIT) Input hold from LCLK (except LGTA/LUPWAIT)1 LGTA valid time LALE valid time Notes: 1. A negative hold time means that the signal could be invalid before the LCLK rising edge. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 45 Tclk LCLK Tin_s Tin_h LAD[23:0] (data) asynchronous input Tgta LGTA Tupwait asynchronous input LUPWAIT Tout_s Output Signals Tout_h LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0] Tad_z Tad_s Tad_h LAD[23:0] Tale Tale_h LALE Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4) Table 19. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) Parameter Symbol Min Max Unit Tclk 40 — ns Tin_s 8 — ns Tin_h –1 — ns Tgta 42 — ns LUPWAIT valid time Tupwait 42 — ns LALE negedge to LAD (address phase) invalid (address latch hold time) Tale_h 5 — ns Tale 34 — ns Output setup from LCLK (except LAD[23:0] and LALE) Tout_s 19 — ns Output hold from LCLK (except LAD[23:0] and LALE) Tout_h 18 — ns LCLK cycle time Input setup to LCLK (except LGTA/LUPWAIT) Input hold from LCLK (except LGTA/LUPWAIT)1 LGTA valid time LALE valid time Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 46 Freescale Semiconductor Table 19. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) (Continued) Parameter Symbol Min Max Unit LAD[23:0] output setup from LCLK Tad_s 12 — ns LAD[23:0] output hold from LCLK Tad_h 17 — ns LCLK to output high impedance for LAD[23:0] Tad_z — 17.1 ns Notes: 1. A negative hold time means that the signal could be invalid before the LCLK rising edge. Tclk LCLK Tin_s Tin_h LAD[23:0] (data) asynchronous input Tgta LGTA Tupwait asynchronous input LUPWAIT Tout_s Output Signals Tout_h LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0] Tad_z Tad_s Tad_h LAD[23:0] Tale Tale_h LALE Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8) 3 Functional Description and Application Information See the Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors Reference Manual (DSP56720RM) for detailed functional and applications information. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 47 4 Ordering Information Table 20 provides ordering information for both the DSP56720 and DSP56721. Table 20. Ordering Information Device Device Marking DSP56720 Commercial DSP56720 Automotive DSP56721 Commercial DSP56721 Automotive 5 Ambient Temp. LQFP Package DSPA56720AG 0°C–70°C 20 mm × 20 mm DSPB56720AG 0°C–70°C 20 mm × 20 mm DSPC56720AG 0°C–70°C 20 mm × 20 mm DSPA56720CAG –40°C–85°C 20 mm × 20 mm DSPB56720CAG –40°C–85°C 20 mm × 20 mm DSPC56720CAG –40°C–85°C 20 mm × 20 mm DSPA56721AG 0°C–70°C 20 mm × 20 mm DSPB56721AG 0°C–70°C 20 mm × 20 mm DSPC56721AG 0°C–70°C 20 mm × 20 mm DSPA56721AF 0°C–70°C 14 mm × 14 mm DSPB56721AF 0°C–70°C 14 mm × 14 mm DSPC56721AF 0°C–70°C 14 mm × 14 mm DSPA56721CAG –40°C–85°C 20 mm × 20 mm DSPB56721CAG –40°C–85°C 20 mm × 20 mm DSPC56721CAG –40°C–85°C 20 mm × 20 mm DSPA56721CAF –40°C–85°C 14 mm × 14 mm DSPB56721CAF –40°C–85°C 14 mm × 14 mm DSPC56721CAF –40°C–85°C 14 mm × 14 mm Package Information For the outline drawings of available device packages, see Table 21 and sections 5.1–5.2. Table 21. Package Outline Drawings Device Package See DSP56720 144-pin plastic LQFP Figure 43 on page 51 and Figure 44 on page 52 DSP56721 80-pin plastic LQFP Figure 43 on page 51 and Figure 42 on page 50 144-pin plastic LQFP Figure 43 on page 51 and Figure 44 on page 52 Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 48 Freescale Semiconductor 5.1 80-Pin Package Outline Drawing Figure 41 and Figure 42 show the 80-pin package outline drawings. Figure 41. 80-Pin Package Outline Drawing (1 of 2) Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 49 Figure 42. 80-Pin Package Outline Drawing (2 of 2) NOTES 1 Dimensioning and tolerancing per asme Y14.5M-1994. 2 Controlling dimension: millimeter 3 Datum plane H is located at the bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4 Datum E, F and D to be determined at datum plane H. 5 Dimensions to be determined at seating plane C. 6 Dimensions do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions include mold mismatch and are determined at datum plane H. 7 Dimension does not include dambar protrusion. Dambar protrusion shall not cause the lead width to exceed 0.46 mm. Minimnum space between protrusion and adjacent lead or protrusion 0.07 mm. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 50 Freescale Semiconductor 5.2 144-Pin Package Outline Drawing Figure 43 and Figure 44 show the 144-pin package drawings. Figure 43. 144-Pin Package Outline Drawing (1 of 2) Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 51 Figure 44. 144-Pin Package Outline Drawing (2 of 2) NOTES 1 All dimensinos are in millimeters 2 Interpret dimensions and tolerances per ASME Y14.5M-1994. 3 Datums B, C and D to be determined at datum plane H. 4 The top ppackage body size may be smaller than the bottom package size by a maximum of 0.1 mm. 5 These dimensions do not include mold protrusions. The maximum allowable protrusion is 0.25 mm per side. These dimensions are maximum body size dimensions including mold mismatch. 6 This dimension does not include dambar protrusion. Protrusions shall not cause the lead width to exceed 0.35 mm minimum space between protrusion and an adjacent lead shall be 0.07 mm. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 52 Freescale Semiconductor 7 These dimensions are determined at the seating plane, datum A. 6 Product Documentation This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. Documentation is available from a local Freescale Semiconductor, Inc. distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). The following documents are required for a complete description of the device and are necessary to design properly with the parts: DSP56300 Family Manual (document number DSP56300FM). Detailed description of the 56300-family architecture and the 24-bit core processor and instruction set. Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors Reference Manual (document number DSP56720RM). Detailed description of memory, peripherals, and interfaces. DSP56720 Product Brief (DSP56720PB). Brief description of the DSP56720 device. DSP56721 Product Brief (DSP56721PB). Brief description of the DSP56721 device. 7 Revision History Table 22 summarizes revisions to this document. Table 22. Revision History Revision Date Description 5 02/2009 • Updated values and added Commercial and Automotive columns in Table 4, “DC Electrical Characteristics.” • Updated values in the following tables: Table 7, Table 9, Table 10, Table 11, Table 12, Table 13, Table 15, Table 17, Table 18, and Table 19. • In Table 10, “Enhanced Serial Audio Interface Timing Parameters,” changed value for 87 to “13”. • Added Section 2.4, “Power Consumption Considerations.” • In Section 2.20, “EMC Timing (DSP56720 Only),” added text regarding the EMC chapter and applicable sections. • Added automotive information to Table 20, “Ordering Information.” 4 04/2008 • Added formula for thermal characteristics on page 10. • Added values for pull-up and pull-down resistors on page 12. 3 03/2008 • Updated order information on page 1 to include additional parts with temperature specification. 2 02/2008 • Timing updates. 1 12/2007 • Initial release Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semiconductor 53 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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