NXP Semiconductors
Data Sheet: Technical Data
Document Number S32K1XX
Rev. 13, 04/2020
S32K1XX
S32K1xx Data Sheet
Notes
• Supports S32K116, S32K118, S32K142, S32K142W,
S32K144, S32K144W, S32K146, and S32K148
– Technical information for S32K142W and
S32K144W device families is preliminary until
these devices achieve qualification
• The following two attachments are available with the
Datasheet:
– S32K1xx_Orderable_Part_Number_ List.xlsx
– S32K1xx_Power_Modes_Configuration.xlsx
Key Features
• Operating characteristics
– Voltage range: 2.7 V to 5.5 V
– Ambient temperature range: -40 °C to 105 °C for
HSRUN mode, -40 °C to 150 °C for RUN mode
• Arm™ Cortex-M4F/M0+ core, 32-bit CPU
– Supports up to 112 MHz frequency (HSRUN mode)
with 1.25 Dhrystone MIPS per MHz
– Arm Core based on the Armv7 Architecture and
Thumb®-2 ISA
– Integrated Digital Signal Processor (DSP)
– Configurable Nested Vectored Interrupt Controller
(NVIC)
– Single Precision Floating Point Unit (FPU)
• Clock interfaces
– 4 - 40 MHz fast external oscillator (SOSC) with up
to 50 MHz DC external square input clock in
external clock mode
– 48 MHz Fast Internal RC oscillator (FIRC)
– 8 MHz Slow Internal RC oscillator (SIRC)
– 128 kHz Low Power Oscillator (LPO)
– Up to 112 MHz (HSRUN) System Phased Lock
Loop (SPLL)
– Up to 20 MHz TCLK and 25 MHz SWD_CLK
– 32 kHz Real Time Counter external clock
(RTC_CLKIN)
• Power management
– Low-power Arm Cortex-M4F/M0+ core with
excellent energy efficiency
– Power Management Controller (PMC) with multiple
power modes: HSRUN, RUN, STOP, VLPR, and
VLPS. Note: CSEc (Security) or EEPROM writes/
erase will trigger error flags in HSRUN mode (112
MHz) because this use case is not allowed to
execute simultaneously. The device will need to
switch to RUN mode (80 MHz) to execute CSEc
(Security) or EEPROM writes/erase.
– Clock gating and low power operation supported on
specific peripherals.
• Memory and memory interfaces
– Up to 2 MB program flash memory with ECC
– 64 KB FlexNVM for data flash memory with ECC
and EEPROM emulation. Note: CSEc (Security) or
EEPROM writes/erase will trigger error flags in
HSRUN mode (112 MHz) because this use case is
not allowed to execute simultaneously. The device
will need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
– Up to 256 KB SRAM with ECC
– Up to 4 KB of FlexRAM for use as SRAM or
EEPROM emulation
– Up to 4 KB Code cache to minimize performance
impact of memory access latencies
– QuadSPI with HyperBus™ support
• Mixed-signal analog
– Up to two 12-bit Analog-to-Digital Converter
(ADC) with up to 32 channel analog inputs per
module
– One Analog Comparator (CMP) with internal 8-bit
Digital to Analog Converter (DAC)
• Debug functionality
– Serial Wire JTAG Debug Port (SWJ-DP) combines
– Debug Watchpoint and Trace (DWT)
– Instrumentation Trace Macrocell (ITM)
– Test Port Interface Unit (TPIU)
– Flash Patch and Breakpoint (FPB) Unit
• Human-machine interface (HMI)
– Up to 156 GPIO pins with interrupt functionality
– Non-Maskable Interrupt (NMI)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Communications interfaces
– Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support
and low power availability
– Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability
– Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability
– Up to three FlexCAN modules (with optional CAN-FD support)
– FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc).
– Up to one 10/100Mbps Ethernet with IEEE1588 support and two Synchronous Audio Interface (SAI) modules.
• Safety and Security
– Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the
SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will
trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The
device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
– 128-bit Unique Identification (ID) number
– Error-Correcting Code (ECC) on flash and SRAM memories
– System Memory Protection Unit (System MPU)
– Cyclic Redundancy Check (CRC) module
– Internal watchdog (WDOG)
– External Watchdog monitor (EWM) module
• Timing and control
– Up to eight independent 16-bit FlexTimers (FTM) modules, offering up to 64 standard channels (IC/OC/PWM)
– One 16-bit Low Power Timer (LPTMR) with flexible wake up control
– Two Programmable Delay Blocks (PDB) with flexible trigger system
– One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels
– 32-bit Real Time Counter (RTC)
• Package
– 32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA, 144-pin LQFP, 176-pin LQFP package
options
• 16 channel DMA with up to 63 request sources using DMAMUX
S32K1xx Data Sheet, Rev. 13, 04/2020
2
NXP Semiconductors
Table of Contents
1
Block diagram.................................................................................... 4
2
Feature comparison............................................................................ 5
3
Ordering information......................................................................... 8
4
6.2.5
6.3 Memory and memory interfaces................................................42
6.3.1
specifications................................................................42
3.2 Ordering information ................................................................ 9
6.3.1.1
General............................................................................................... 10
Flash timing specifications —
commands................................................ 42
6.3.1.2
4.2 Voltage and current operating requirements..............................12
6.3.2
4.3 Thermal operating characteristics..............................................13
Reliability specifications..........................49
QuadSPI AC specifications..........................................49
6.4 Analog modules......................................................................... 54
4.4 Power and ground pins.............................................................. 15
6.4.1
ADC electrical specifications...................................... 54
4.5 LVR, LVD and POR operating requirements............................17
6.4.1.1
12-bit ADC operating conditions............. 54
4.6 Power mode transition operating behaviors.............................. 18
6.4.1.2
12-bit ADC electrical characteristics....... 57
4.7 Power consumption................................................................... 20
6.4.2
4.8 ESD handling ratings.................................................................27
CMP with 8-bit DAC electrical specifications............ 59
6.5 Communication modules........................................................... 65
4.9 EMC radiated emissions operating behaviors........................... 27
6.5.1
LPUART electrical specifications............................... 65
I/O parameters....................................................................................28
6.5.2
LPSPI electrical specifications.................................... 65
5.1 AC electrical characteristics...................................................... 28
6.5.3
LPI2C electrical specifications.................................... 71
5.2 General AC specifications......................................................... 28
6.5.4
FlexCAN electical specifications.................................72
5.3 DC electrical specifications at 3.3 V Range.............................. 29
6.5.5
SAI electrical specifications........................................ 72
5.4 DC electrical specifications at 5.0 V Range.............................. 31
6.5.6
Ethernet AC specifications.......................................... 74
5.5 AC electrical specifications at 3.3 V range .............................. 32
6.5.7
Clockout frequency......................................................77
5.6 AC electrical specifications at 5 V range ................................. 33
6
Flash memory module (FTFC/FTFM) electrical
3.1 Selecting orderable part number ...............................................8
4.1 Absolute maximum ratings........................................................10
5
SPLL electrical specifications .....................................42
6.6 Debug modules.......................................................................... 77
5.7 Standard input pin capacitance.................................................. 34
6.6.1
SWD electrical specofications .................................... 77
5.8 Device clock specifications....................................................... 35
6.6.2
Trace electrical specifications......................................79
Peripheral operating requirements and behaviors.............................. 36
6.6.3
JTAG electrical specifications..................................... 80
6.1 System modules......................................................................... 36
7
6.2 Clock interface modules............................................................ 36
Thermal attributes.............................................................................. 84
7.1 Description.................................................................................84
6.2.1
External System Oscillator electrical specifications....36
7.2 Thermal characteristics..............................................................84
6.2.2
External System Oscillator frequency specifications . 38
7.3 General notes for specifications at maximum junction
6.2.3
System Clock Generation (SCG) specifications.......... 40
6.2.3.1
Fast internal RC Oscillator (FIRC)
temperature................................................................................ 89
8
electrical specifications............................ 40
6.2.3.2
Slow internal RC oscillator (SIRC)
electrical specifications ........................... 41
6.2.4
Low Power Oscillator (LPO) electrical specifications
Dimensions.........................................................................................90
8.1 Obtaining package dimensions ................................................. 90
9
Pinouts................................................................................................91
9.1 Package pinouts and signal descriptions....................................91
10 Revision History.................................................................................91
......................................................................................41
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
3
Block diagram
1 Block diagram
Following figures show superset high level architecture block diagrams of S32K14x,
S32K14xW and S32K11x series respectively. Other devices within the family have a
subset of the features. See Feature comparison for chip specific values.
Async
Trace
port
JTAG &
Serial Wire
Arm Cortex M4F
Core
MCM
TPIU
PPB
SWJ-DP
NVIC
AHB-AP
FPU
FPB
DSP
DWT
System
ICODE
DCODE
LMEM
Upper region
EIM
LMEM
controller
Lower region
System MPU1
Mux
Main SRAM2
AWIC
ITM
Clock generation
DMA
MUX
LPO
128 kHz
eDMA
FIRC
48 MHz
SIRC
8 MHz
SOSC
4-40 MHz 8-40 MHz
SPLL
TCD
512B
Code Cache
ENET
S1
System MPU1
M3
M2
M1
M0
S2
Crossbar switch (AXBS-Lite)
S3
S0
System MPU1
Mux
System MPU1
QuadSPI
GPIO
Flash memory
controller
Peripheral bus controller
ERM
WDOG
EWM
CRC
12-bit ADC
CMP
8-bit DAC
TRGMUX
LPI2C
LPUART
LPSPI
FlexCAN
PDB
Low Power
Timer
FlexIO
FlexTimer
FlexRAM/
SRAM
LPIT
QSPI
LPIT
RTC
Code flash
memory
CSEc3
SAI
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned
different access rights to each protected memory region. The Arm M4 core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this
use case is not allowed to execute simultaneously. The device need to switch to RUN mode (80 MHz) to
execute CSEc (Security) or EEPROM writes/erase.
Data flash
memory
Device architectural IP
on all S32K devices
Key:
Peripherals present
on all S32K devices
Peripherals present
on selected S32K devices
(see the "Feature Comparison"
section)
Figure 1. High-level architecture diagram for the S32K14x and S32K14xW family
S32K1xx Data Sheet, Rev. 13, 04/2020
4
NXP Semiconductors
Feature comparison
IO PORT
Arm Cortex M0+
Clock generation
IO PORT
Serial Wire
SW-DP
NVIC
AHB-AP
LPO
128 kHz
AWIC
FIRC
48 MHz
SIRC
8 MHz
SOSC
4-40 MHz
DMA
MUX
PPB
Unified Bus
BPU
MTB+DWT
eDMA
AHBLite
AHBLite
M2
M0
Crossbar switch (AXBS-Lite)
S0
S2
S1
System MPU1
System MPU1
EIM
Flash memory
controller
SRAM2
FlexRAM/
SRAM2
Code flash
memory
Peripheral bus controller
Data flash
memory
ERM
12-bit ADC
WDOG
LPI2C
FlexIO
Low Power
Timer
LPIT
CSEc
CMP
8-bit DAC
CMU
CRC
LPUART
TRGMUX
FlexCAN
LPSPI
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Crossbar master (Core, DMA) can be assigned
different access rights to each protected memory region. The Arm M0+ core version in this family
does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K1xx Series Reference Manual.
PDB
FlexTimer
GPIO
RTC
LPIT
Device architectural IP
on all S32K devices
Peripherals present
on all S32K devices
Key:
Peripherals present
on selected S32K devices
(see the "Feature Comparison"
section)
Figure 2. High-level architecture diagram for the S32K11x family
2 Feature comparison
The following figure summarizes the memory, peripherals and packaging options for the
S32K1xx and S32K14xW devices. All devices which share a common package are pinto-pin compatible.
NOTE
Availability of peripherals depends on the pin availability in a
particular package. For more information see IO Signal
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
5
Feature comparison
Description Input Multiplexing sheet(s) attached with
Reference Manual.
S32K14x
S32K11x
K116
Parameter
K118
Core
Arm® Cortex™-M0+
Frequency
48 MHz
K142
K146
K144
K148
Arm® Cortex™-M4F
80 MHz (RUN mode) or 112 MHz (HSRUN mode)1
IEEE-754 FPU
Cryptographic Services Engine (CSEc)1
1x
1x
capable up to ASIL-B
capable up to ASIL-B
up to 48 MHz
up to 112 MHz (HSRUN)
1x
1x
CRC module
ISO 26262
Peripheral speed
System
Crossbar
DMA
External Watchdog Monitor (EWM)
Memory Protection Unit (MPU)
FIRC CMU
Watchdog
Low power modes
HSRUN mode1
up to 58
up to 43
Number of I/Os
up to 89
up to 128
2.7 - 5.5 V
Single supply voltage
Ambient Operation Temperature (Ta)
-40oC to +105oC / +125oC
128 KB
Flash
up to 156
2.7 - 5.5 V
-40oC to +105oC / +125oC
256 KB
256 KB
512 KB
25 KB
32 KB
64 KB
1 MB
2 MB2
128 KB
256 KB
Error Correcting Code (ECC)
Memory
System RAM (including FlexRAM and MTB)
17 KB
FlexRAM (also available as system RAM)
2 KB
4 KB
4 KB
Cache
EEPROM emulated by FlexRAM1
See footnote 3
4 KB (up to 64 KB D-Flash)
2 KB (up to 32 KB D-Flash)
QuadSPI incl.
HyperBus™
External memory interface
Analog
Timer
Low Power Interrupt Timer (LPIT)
1x
1x
2x (16)
FlexTimer (16-bit counter) 8 channels
4x (32)
1x
1x
Real Time Counter (RTC)
1x
1x
Programmable Delay Block (PDB)
1x
Low Power Timer (LPTMR)
6x (48)
8x (64)
2x
Trigger mux (TRGMUX)
1x (43)
1x (45)
1x (64)
1x (73)
1x (81)
12-bit SAR ADC (1 Msps each)
1x (13)
1x (16)
2x (16)
2x (24)
2x (32)
Comparator with 8-bit DAC
1x
1x
1x
Communication
10/100 Mbps IEEE-1588 Ethernet MAC
2x
Serial Audio Interface (AC97, TDM, I2S)
Low Power UART/LIN (LPUART)
2x
(Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602)
1x
Low Power SPI (LPSPI)
2x
Other
IDEs
FlexIO (8 pins configurable as UART, SPI, I2C, I2S)
Packages5
2x
3x
1x
1x
(1x with FD)
FlexCAN
(CAN-FD ISO/CD 11898-1)
Ecosystem
(IDE, compiler, debugger)
3x
1x
Low Power I2C (LPI2C)
Debug & trace
2x
2x
(1x with FD)
1x
3x
(2x with FD)
3x
(3x with FD)
1x
SWD, MTB (1 KB), JTAG4
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, Arm®, Lauterbach, iSystems
32-pin QFN
48-pin LQFP
2x
3x
(1x with FD)
48-pin LQFP
64-pin LQFP
SWD, JTAG (ITM, SWV, SWO)
SWD, JTAG
(ITM, SWV,
SWO), ETM
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, Arm®, Lauterbach, iSystems
64-pin LQFP 100-pin MAPBGA
48-pin LQFP
48-pin LQFP
64-pin LQFP 100-pin MAPBGA 100-pin LQFP6
64-pin LQFP
144-pin LQFP
100-pin LQFP
100-pin LQFP
100-pin LQFP
176-pin LQFP
100-pin MAPBGA 144-pin LQFP
LEGEND:
Not implemented
Available on the device
1 No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when
device is running at HSRUN mode (112MHz) or VLPR mode.
2 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash.
3 4 KB (up to 512 KB D-Flash as a part of 2 MB Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB
of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details.
4 Only for Boundary Scan Register
5 See Dimensions section for package drawings
6 QuadSPI is not supported for S32K148 in 100-pin LQFP
Figure 3. S32K1xx product series comparison
S32K1xx Data Sheet, Rev. 13, 04/2020
6
NXP Semiconductors
Feature comparison
S32K14xW
Parameter
S32K144W
S32K142W
Arm® Cortex™-M4F
Core
up to 80 MHz
Frequency
IEEE-754 FPU
Cryptographic Services Engine (CSEc)
1x
CRC module
capable up to ASIL-B
ISO 26262
Peripheral speed
up to 80 MHz
System
Crossbar
DMA
External Watchdog Monitor (EWM)
Memory Protection Unit (MPU)
FIRC CMU
Watchdog
Low power modes
HSRUN mode
43 (48-pin LQFP)
Number of I/Os
58 (64-pin LQFP)
3.13 - 5.5 V
Single supply voltage
Ambient Operation Temperature (Ta)
Flash
-40oC to +150oC
256 KB
512 KB
Error Correcting Code (ECC)
Memory
System RAM (including FlexRAM)
64 KB
FlexRAM
32 KB
4 KB
4 KB
Cache
EEPROM emulated by FlexRAM
4 KB (up to 64 KB D-Flash)
External memory interface
Timer
Low Power Interrupt Timer (LPIT)
FlexTimer (16-bit counter) 8 channels
1x
64-pin LQFP: 4x (30 channels)
48-pin LQFP: 4x (26 channels)
Low Power Timer (LPTMR)
1x
Real Time Counter (RTC)
1x
2x
Programmable Delay Block (PDB)
1x (59)
Analog
Trigger mux (TRGMUX)
12-bit SAR ADC (1 Msps each)
Comparator with 8-bit DAC
48-pin LQFP: 1x (14 channels), 1x(9 channels)
64-pin LQFP: 1x (16 channels), 1x(13 channels)
48-pin LQFP: 1x (6 channels)
64-pin LQFP: 1x (8 channels)
Communication
10/100 Mbps IEEE-1588 Ethernet MAC
Serial Audio Interface (AC97, TDM, I2S)
Low Power UART/LIN (LPUART)
(Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A, and SAE J2602)
Low Power SPI (LPSPI)
48-pin LQFP: 2x
48-pin LQFP: 2x(2x FD)
Other
IDEs
FlexIO (8 pins configurable as UART, SPI, I2C, I2S)
Ecosystem
(IDE, compiler, debugger)
Packages1
64-pin LQFP: 3x
1x
Low Power I2C (LPI2C)
FlexCAN
(CAN-FD ISO/CD 11898-1)
Debug & trace
64-pin LQFP: 3x
48-pin LQFP: 2x
64-pin LQFP: 2x(2x FD)
1x
SWD, JTAG (ITM, SWV, SWO)
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, Arm®, Lauterbach, iSystems
48-pin LQFP
64-pin LQFP
LEGEND:
Not implemented
Available on the device
1 See Dimensions section of Datasheet for package drawings
Figure 4. S32K14xW product series comparison
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
7
Ordering information
3 Ordering information
3.1 Selecting orderable part number
Not all part number combinations are available. See the attachment
S32K1xx_Orderable_Part_Number_ List.xlsx attached with the Datasheet for a list of
standard orderable part numbers.
S32K1xx Data Sheet, Rev. 13, 04/2020
8
NXP Semiconductors
Ordering information
3.2 Ordering information
F/P S32 K 1 0 0 X Y T0 M LH R
Product status
Product type/brand
Product line
Series/Family
(including generation)
Core platform/
Performance
Memory size
Ordering option 1: Letter
Ordering option 2: Letter
Wafer Fab and
revision
Temperature
Package
Tape and Reel
Product status
P: Prototype
F: Qualified
Product type/brand
S32: Automotive 32-bit MCU
Product line
K: Arm Cortex MCUs
Series/Family
1: 1st product series
2: 2nd product series
Core platform/Performance
1: Arm Cortex M0+
4: Arm Cortex M4F
Ordering option
X: Speed
L: 48 MHz with DMA (S32K11x only)
H: 80 MHz
U1: 112 MHz (Not valid with M temperature/125C)
W: 80 MHz (S32K14xW only)
Y: Optional feature
V: NFC Stack License
F: CAN FD, FlexIO
A1: CAN FD, FlexIO, Security
X1: CAN FD, FlexIO, Security with NFC Stack License
E: Ethernet, Serial Audio Interface (S32K148 only)
J1: Ethernet, Serial Audio Interface, CAN FD,
FlexIO, Security (S32K148 only)
I: ISELED, FlexIO
L1: ISELED, CAN FD, FlexIO, Security
G1: ISELED, Ethernet, Serial Audio Interface, CAN FD,
FlexIO, Security (S32K148 only)
Memory size
2
4
6
S32K11x
S32K14x/
S32K14xW
Wafer Fab and Mask revision identifier
Tx: Wafer Fab identifier
x0: Mask Revision identifier
8
128K 256K
256K 512K
1M
Temperature
V: -40C to 105C
M: -40C to 125C
W: -40 to 150C
Package
Pins
LQFP
QFN
BGA
-
32
-
FM
48
LF
-
MH
LH
-
100
LL
-
144
LQ
-
-
176
LU
-
-
64
Tape and Reel
T: Trays/Tubes
R: Tape and Reel
2M
1. CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to
execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase.
2. Part numbers no longer offered as standard include:
Ordering Option X
M: 64MHz
B: 48 MHz without DMA (S32K11x only)
Ordering Option Y
N: limited RAM. 16KB for K142, 48KB for K144, 96KB for K146, 192KB for K148
R: Basic feature set
S: Security
B: CAN FD, FlexIO, limited RAM (S32K14x only)
C: CAN FD, FlexIO, Security, limited RAM (S32K14x only)
Temperature
C: -40C to 85C
NOTE
Not all part number combinations are available. See S32K1xx_Orderable_Part_Number_List.xlsx
attached with the Datasheet for list of standard orderable parts.
Figure 5. Ordering information
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
9
General
4 General
4.1 Absolute maximum ratings
•
•
•
•
NOTE
Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maximum
values is not guaranteed. See footnotes in the following
table for specific conditions.
Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
All the limits defined in the datasheet specification must be
honored together and any violation to any one or more will
not guarantee desired operation.
Unless otherwise specified, all maximum and minimum
values in the datasheet are across process, voltage, and
temperature.
Table 1. Absolute maximum ratings for S32K1xx series
Symbol
Conditions1
Parameter
2
VDD
2.7 V - 5. 5V input supply voltage
VREFH
—
Min
Max
-0.3
5.8
3
Unit
V
5.8
3
V
3.3 V / 5.0 V ADC high reference voltage
—
-0.3
Continuous DC input current (positive /
negative) that can be injected into an I/O
pin
—
-3
+3
mA
Continuous DC Voltage on any I/O pin
with respect to VSS
—
-0.8
5.85
V
Sum of absolute value of injected currents
on all the pins (Continuous DC limit)
—
—
30
mA
Tramp6
ECU supply ramp rate
—
0.5 V/min
500 V/ms
—
Tramp_MCU7
4
IINJPAD_DC_ABS
VIN_DC
IINJSUM_DC_ABS
MCU supply ramp rate
—
0.5 V/min
100 V/ms
—
TA8
Ambient temperature
—
-40
125
°C
TSTG
Storage temperature
—
-55
165
°C
—
9
VIN_TRANSIENT
Transient overshoot voltage allowed on
I/O pin beyond VIN_DC limit
—
6.8
V
1. All voltages are referred to VSS unless otherwise specified.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the
ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.
3. 60 seconds lifetime – No restrictions i.e. the part is not held in reset and can switch.
10 hours lifetime – The part is held in reset by an external circuit i.e. the part cannot switch.
S32K1xx Data Sheet, Rev. 13, 04/2020
10
NXP Semiconductors
General
The supply should be kept in operating conditions and once out of operating conditions, the device should be either reset
or powered off.
Operation with supply between 5.5 V and 5.8 V not in reset condition is allowed for 60 seconds cumulative over lifetime,
the part will operate with reduced functionality.
Operation with supply between 5.5 V and 5.8 V but held in reset condition by external circuit is allowed for 10 hours
cumulative over lifetime.
If the given time limits or supply levels are exceeded, the device may get damaged.
4. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
5. While respecting the maximum current injection limit
6. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both
maximum absolute maximum ramp rate and typical operating conditions.
7. This is the MCU supply ramp rate and the ramp rate assumes that the S32K1xx HW design guidelines in AN5426 are
followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.
8. TJ (Junction temperature)=135 °C. Assumes TA=125 °C for RUN mode
TJ (Junction temperature)=125 °C. Assumes TA=105 °C for HSRUN mode
• Assumes maximum θJA for 2s2p board. See Thermal characteristics
9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)
Table 2. Absolute maximum ratings for S32K14xW series
Conditions1
Min
Max
Unit
2.7 V - 5. 5V input supply voltage
—
-0.3
5.8 3
V
3.3 V / 5.0 V ADC high reference voltage
—
-0.3
5.8 3
V
Continuous DC input current (positive /
negative) that can be injected into an I/O
pin
—
-3
+3
mA
Continuous DC Voltage on any I/O pin
with respect to VSS
—
-0.8
5.85
V
Sum of absolute value of injected currents
on all the pins (Continuous DC limit)
—
—
30
mA
Tramp6
ECU supply ramp rate
—
0.5 V/min
500 V/ms
—
Tramp_MCU7
Symbol
Parameter
VDD2
VREFH
4
IINJPAD_DC_ABS
VIN_DC
IINJSUM_DC_ABS
MCU supply ramp rate
—
0.5 V/min
100 V/ms
—
TA8
Ambient temperature
—
-40
150
°C
TSTG
Storage temperature
—
-55
165
°C
Transient overshoot voltage allowed on
I/O pin beyond VIN_DC limit
—
—
6.8 9
V
VIN_TRANSIENT
1. All voltages are referred to VSS unless otherwise specified.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the
ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.
3. 60 seconds lifetime – No restrictions i.e. the part is not held in reset and can switch.
10 hours lifetime – The part is held in reset by an external circuit i.e. the part cannot switch.
The supply should be kept in operating conditions and once out of operating conditions, the device should be either reset
or powered off.
Operation with supply between 5.5 V and 5.8 V not in reset condition is allowed for 60 seconds cumulative over lifetime,
the part will operate with reduced functionality.
Operation with supply between 5.5 V and 5.8 V but held in reset condition by external circuit is allowed for 10 hours
cumulative over lifetime.
If the given time limits or supply levels are exceeded, the device may get damaged.
4. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
5. While respecting the maximum current injection limit
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
11
General
6. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both
maximum absolute maximum ramp rate and typical operating conditions.
7. This is the MCU supply ramp rate and the ramp rate assumes that the S32K1xx HW design guidelines in AN5426 are
followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.
8. TJ (Junction temperature)=170 °C. Assumes TA=150 °C for RUN mode
• TJ is the absolute maximum rating temperature at which the product will not be damaged, guaranteed by intrinsic
reliability.
• Assumes maximum θJA for 2s2p board. See Thermal characteristics
9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)
4.2 Voltage and current operating requirements
NOTE
Device functionality is guaranteed up to the LVR assert level,
however electrical performance of 12-bit ADC, CMP with 8-bit
DAC, IO electrical characteristics, and communication modules
electrical characteristics would be degraded when voltage drops
below 2.7 V
Table 3. Voltage and current operating requirements for S32K1xx series 1
Symbol
Description
Min.
Max.
Unit
Notes
VDD2
Supply voltage
2.73
5.5
V
4
0
0.1
V
VDD_OFF
Voltage allowed to be developed on VDD
pin when it is not powered from any
external power supply source.
VDDA
Analog supply voltage
VDD – VDDA
VDD-to-VDDA differential voltage
2.7
5.5
V
4
– 0.1
0.1
V
4
5
VREFH
ADC reference voltage high
2.7
VDDA + 0.1
V
VREFL
ADC reference voltage low
-0.1
0.1
V
Open drain pullup voltage level
VDD
VDD
V
VODPU
7
IINJPAD_DC_OP
Continuous DC input current (positive /
negative) that can be injected into an I/O
pin
-3
+3
mA
IINJSUM_DC_OP
Continuous total DC input current that can
be injected across all I/O pins such that
there's no degradation in accuracy of
analog modules: ADC and ACMP (See
section Analog Modules)
—
30
mA
6
1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise
stated.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the
ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.
3. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to
operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.
4. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC
only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for
reference supply design for SAR ADC.
5. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V
S32K1xx Data Sheet, Rev. 13, 04/2020
12
NXP Semiconductors
General
6. Open drain outputs must be pulled to VDD.
7. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
Table 4. Voltage and current operating requirements for S32K14xW series 1
Symbol
Description
Min.
Max.
Unit
Notes
VDD2
Supply voltage
3.13
5.5
V
3
0
0.1
V
Analog supply voltage
3.13
5.5
V
3
VDD_OFF
Voltage allowed to be developed on VDD
pin when it is not powered from any
external power supply source.
VDDA
VDD – VDDA
VDD-to-VDDA differential voltage
– 0.1
0.1
V
3
VREFH
ADC reference voltage high
3.13
VDDA + 0.1
V
4
VREFL
ADC reference voltage low
-0.1
0.1
V
Open drain pullup voltage level
VDD
VDD
V
VODPU
6
IINJPAD_DC_OP
Continuous DC input current (positive /
negative) that can be injected into an I/O
pin
-3
+3
mA
IINJSUM_DC_OP
Continuous total DC input current that can
be injected across all I/O pins such that
there's no degradation in accuracy of
analog modules: ADC and ACMP (See
section Analog Modules)
—
30
mA
5
1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise
stated.
2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the
ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.
3. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC
only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for
reference supply design for SAR ADC.
4. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V
5. Open drain outputs must be pulled to VDD.
6. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.
4.3 Thermal operating characteristics
Table 5. Thermal operating characteristics for S32K1xx series
Symbol
TA C-Grade Part
TJ C-Grade Part
Parameter
Ambient temperature under bias
Junction temperature under bias
Value
Unit
Min.
Typ.
Max.
−40
—
851
℃
—
1051
℃
℃
−40
TA V-Grade Part
Ambient temperature under bias
−40
—
1051
TJ V-Grade Part
Junction temperature under bias
−40
—
1251
℃
TA M-Grade Part
Ambient temperature under bias
−40
—
1252
℃
—
1352
℃
TJ M-Grade Part
Junction temperature under bias
−40
1. Values mentioned are measured at ≤ 112 MHz in HSRUN mode.
2. Values mentioned are measured at ≤ 80 MHz in RUN mode.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
13
General
Table 6. Thermal operating characteristics for S32K14xW series
Symbol
Parameter
Value
Unit
Min.
Typ.
Max.
TA C-Grade Part
Ambient temperature under bias
−40
—
85
℃
TJ C-Grade Part
Junction temperature under bias
−40
—
105
℃
TA V-Grade Part
Ambient temperature under bias
−40
—
105
℃
TJ V-Grade Part
Junction temperature under bias
−40
—
125
℃
—
1251
℃
—
1351
℃
—
1501
℃
—
1701
℃
TA M-Grade Part
TJ M-Grade Part
TA W-Grade Part
TJ W-Grade Part
Ambient temperature under bias
Junction temperature under bias
Ambient temperature under bias
Junction temperature under bias
−40
−40
−40
−40
1. Values mentioned are measured at ≤ 80 MHz in RUN mode.
S32K1xx Data Sheet, Rev. 13, 04/2020
14
NXP Semiconductors
General
VSS
VDD
48 LQFP
Package
VREFH/VDDA
VSS
C DEC
VDD
CREF
VREFL/VSSA/VSS
32 QFN
Package
C DEC
VREFH/VDDA/VDD
VDD
C DEC
CREF
4.4 Power and ground pins
VREFL/VSSA/VSS
CREF
C DEC
VSS
C DEC
VREFL/VSSA/VSS
VREFH
VREFL
VDD
100 LQFP
Package
VSS
VSSA/VSS
VSS
VDD
CREF
VREFH
VDDA
C DEC
C DEC
VDD
64 LQFP
Package
VDDA
C DEC
VDD
VDD
C DEC
VSS
VDD
C DEC
C DEC
C DEC
C DEC
VDD
C DEC
VSS
VDD
VSS
C DEC
VSS
VDD
VSS
VSS
VSS
VSS
CREF
VREFL
VSSA/VSS
VDD
176 LQFP
Package
VDD
VSS
VDD
VSS
VSS
VDD
VDD
VREFH
VDD
C DEC
C DEC
VSS
C DEC
VSS
VDDA
DEC
VDD
C
VREFL
VSSA/VSS
144 LQFP
Package
C DEC
VREFH
VDD
VDD
VSS
VSS
CREF
DEC
C
C DEC
CDEC
C DEC
VDD
VDDA
C DEC
VDD
C DEC
C DEC
NOTE: VDD and VDDA must be shorted to a common source on PCB
Figure 6. Pinout decoupling
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
15
General
Table 7. Supplies decoupling capacitors 1, 2
Symbol
Description
Min. 3
Typ.
Max.
Unit
CREF, 4, 5
ADC reference high decoupling capacitance
70
100
—
nF
CDEC5, 6, 7
Recommended decoupling capacitance
70
100
—
nF
1. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC
only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for
reference supply design for SAR ADC. All VSS pins should be connected to common ground at the PCB level.
2. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type).
3. Minimum recommendation is after considering component aging and tolerance.
4. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel.
5. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins.
6. Contact your local Field Applications Engineer for details on best analog routing practices.
7. The filtering used for decoupling the device supplies must comply with the following best practices rules:
• The protection/decoupling capacitors must be on the path of the trace connected to that component.
• No trace exceeding 1 mm from the protection to the trace or to the ground.
• The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm).
• The ground of the protection is connected as short as possible to the ground plane under the integrated circuit.
S32K1xx Data Sheet, Rev. 13, 04/2020
16
NXP Semiconductors
VREFH
VREFL
VSSA
VDD
VDDA
General
VOSC = 3.3 V nominal
FIRC
SIRC
SPLL
SOSC
ADC
CMP
VCORE = 1.2 V/1.4 V nominal
VFlash = 3.3 V nominal
PMC
LV SOG
GPIO
VSS
Flash
Pads
System RAM
TCD RAM
I/D Cache
EEE RAM
*Note: VSSA and VSS are shorted at package level
Figure 7. Power diagram
4.5 LVR, LVD and POR operating requirements
Table 8. VDD supply LVR, LVD and POR operating requirements for S32K1xx series
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Rising and falling VDD POR detect voltage
1.1
1.6
2.0
V
VLVR
LVR falling threshold (RUN, HSRUN, and
STOP modes)
2.50
2.58
2.7
V
—
45
—
mV
LVR falling threshold (VLPS/VLPR modes)
1.97
2.22
2.44
V
Falling low-voltage detect threshold
2.8
2.875
3
V
LVD hysteresis
—
50
—
mV
VLVR_HYST
VLVR_LP
VLVD
VLVD_HYST
LVR hysteresis
Notes
1
1
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
17
General
Table 8. VDD supply LVR, LVD and POR operating requirements for S32K1xx series
(continued)
Symbol
VLVW
VLVW_HYST
VBG
Description
Min.
Typ.
Max.
Unit
Falling low-voltage warning threshold
4.19
4.305
4.5
V
—
75
—
mV
0.97
1.00
1.03
V
LVW hysteresis
Bandgap voltage reference
Notes
1
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
Table 9. VDD supply LVR and POR operating requirements for S32K14xW series
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Rising and falling VDD POR detect voltage
1.1
1.6
2.0
V
VLVR
LVR falling threshold (RUN and STOP
modes)
1.97
2.22
2.44
V
—
45
—
mV
LVR falling threshold (VLPS/VLPR modes)
2.06
2.26
2.46
V
Falling low-voltage warning threshold
4.19
4.305
4.5
V
—
75
—
mV
0.97
1.00
1.03
V
VLVR_HYST
VLVR_LP2
VLVW
VLVW_HYST
VBG
LVR hysteresis
LVW hysteresis
Bandgap voltage reference
Notes
1
1
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
2. An internal monitor could reset the chip at a higher supply level, but 3.13 V onward the chip is fully functional.
4.6 Power mode transition operating behaviors
All specifications in the following table assume this clock configuration:
Table 10. Clock configuration
S32K1xx
S32K14xW
RUN mode
Clock source
FIRC
FIRC
SYS_CLK/CORE_CLK
48 MHz
48 MHz
BUS_CLK
48 MHz
48 MHz
FLASH_CLK
24 MHz
16 MHz
Clock source
SPLL
NA
SYS_CLK/CORE_CLK
112 MHz
NA
BUS_CLK
56 MHz
NA
FLASH_CLK
28 MHz
NA
SIRC
SIRC
HRUN mode
VLPR mode
Clock source
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
18
NXP Semiconductors
General
Table 10. Clock configuration (continued)
S32K1xx
S32K14xW
SYS_CLK/CORE_CLK
4 MHz
1 MHz
BUS_CLK
4 MHz
1 MHz
FLASH_CLK
1 MHz
0.25
Clock source
FIRC
FIRC
SYS_CLK/CORE_CLK
48 MHz
48 MHz
BUS_CLK
48 MHz
48 MHz
FLASH_CLK
24 MHz
16 MHz
STOP1/STOP2 mode
VLPS mode
All clock source disabled 1
1.
• For S32K11x – FIRC/SOSC
• For S32K14x, S32K14xW – FIRC/SOSC/SPLL
Table 11. Power mode transition operating behaviors for S32K1xx series
Symbol
tPOR
Description
Min.
Typ.
Max.
Unit
After a POR event, amount of time from the point VDD
reaches 2.7 V to execution of the first instruction
across the operating temperature range of the chip.
—
325
—
μs
VLPS → RUN
8
—
17
μs
STOP1 → RUN
0.07
0.075
0.08
μs
STOP2 → RUN
0.07
0.075
0.08
μs
VLPR → RUN
19
—
26
μs
VLPR → VLPS
5.1
5.7
6.5
μs
VLPS → VLPR
18.8
23
27.75
μs
RUN → Compute operation
0.72
0.75
0.77
μs
HSRUN → Compute operation
0.3
0.31
0.35
μs
RUN → STOP1
0.35
0.38
0.4
μs
RUN → STOP2
0.2
0.23
0.25
μs
RUN → VLPS
0.3
0.35
0.4
μs
RUN → VLPR
3.5
3.8
5
μs
VLPS → Asynchronous DMA Wakeup
105
110
125
μs
STOP1 → Asynchronous DMA Wakeup
1
1.1
1.3
μs
STOP2 → Asynchronous DMA Wakeup
1
1.1
1.3
μs
Pin reset → Code execution
—
214
—
μs
NOTE
HSRUN should only be used when frequencies in excess of 80
MHz are required. When using 80 MHz and below, RUN mode
is the recommended operating mode.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
19
General
Table 12. Power mode transition operating behaviors for S32K14xW series
Symbol
tPOR
Description
Min.
Typ.
Max.
Unit
—
TBD
—
μs
VLPS → RUN
TBD
—
TBD
μs
STOP1 → RUN
TBD
TBD
TBD
μs
STOP2 → RUN
TBD
TBD
TBD
μs
VLPR → RUN
TBD
—
TBD
μs
VLPR → VLPS
TBD
TBD
TBD
μs
VLPS → VLPR
TBD
TBD
TBD
μs
RUN → Compute operation
TBD
TBD
TBD
μs
RUN → STOP1
TBD
TBD
TBD
μs
RUN → STOP2
TBD
TBD
TBD
μs
RUN → VLPS
TBD
TBD
TBD
μs
RUN → VLPR
TBD
TBD
TBD
μs
VLPS → Asynchronous DMA Wakeup
TBD
TBD
TBD
μs
STOP1 → Asynchronous DMA Wakeup
TBD
TBD
TBD
μs
STOP2 → Asynchronous DMA Wakeup
TBD
TBD
TBD
μs
—
TBD
—
μs
After a POR event, amount of time from the point VDD
reaches 3.13 V to execution of the first instruction
across the operating temperature range of the chip.
Pin reset → Code execution
4.7 Power consumption
The following table shows the power consumption targets for the device in various mode
of operations. Attached S32K1xx_Power_Modes _Configuration.xlsx details the modes
used in gathering the power consumption data stated in the following table Table 13. For
full functionality refer to table: Module operation in available power modes of the
Reference Manual.
S32K1xx Data Sheet, Rev. 13, 04/2020
20
NXP Semiconductors
26
40
1.05
1.07
1.70
6.3
7.2
11.8
20.3
85
Typ
76
93
1.1
1.11
1.77
6.6
7.5
12
20.6
251
Max
287
300
1.39
1.4
NA
8
8.9
13.4
22.1
279
Typ
139
164
1.15
1.16
1.81
6.8
7.7
12.3
20.8
255
Max
590
603
1.68
1.69
NA
9.2
10.1
14.5
23.1
302
Typ
NA
NA
NA
NA
1.96
NA
NA
NA
NA
NA
Max
891
904
2.02
2.04
NA
10.4
11.3
15.6
24.1
325
25
Typ
27
40
1.15
1.16
1.76
6.4
7.3
12.8
21.5
85
Typ
81
100
1.20
1.21
1.82
6.7
7.6
13.2
21.8
274
Max
304
323
1.46
1.47
NA
8
9
14.5
23.4
301
Typ
149
175
1.27
1.28
1.89
6.9
7.9
13.4
22.1
279
Max
606
637
1.76
1.77
NA
9.3
10.4
15.4
24.2
320
Typ
NA
NA
NA
NA
2.03
NA
NA
NA
NA
NA
Max
1111
1126
2.32
2.33
NA
11.0
11.9
17.1
25.9
357
105
125
NA
IDD/MHz (μA/MHz) 4
Peripherals enabled
HSRUN@112
MHz (mA) 3
Peripherals disabled
Peripherals enabled
Peripherals disabled
Peripherals enabled
RUN@64 MHz RUN@80 MHz
(mA)
(mA)
Peripherals disabled
Peripherals disabled
RUN@48
MHz (mA)
Peripherals enabled
STOP2
(mA)
Peripherals enabled use case 27
Peripherals disabled 6
LPTMR enabled
STOP1
(mA)
Typ
125
S32K142
VLPR (mA)
25
105
S32K118
Peripherals disabled 5
S32K1xx Data Sheet, Rev. 13, 04/2020
S32K116
Ambient Temperature (°C)
Chip/Device
VLPS (μA) 2
Peripherals enabled use case 16
NXP Semiconductors
Table 13. Power consumption (Typicals unless stated otherwise) 1
245
NA
268
Typ
29
40
1.17
1.21
2.19
6.4
7.4
17.3
24.6
24.5
31.3
28.8
37.5
40.5
52.2
360
85
Typ
128
137
1.48
1.51
2.31
7
8
17.6
24.9
25
31.6
29.1
37.7
41.1
52.5
364
Max
335
360
1.87
1.89
NA
8.6
9.4
22
28.2
26.9
33.5
32
40
44
55.6
400
Table continues on the next page...
21
General
25
105
125
S32K144
25
85
IDD/MHz (μA/MHz) 4
Peripherals enabled
HSRUN@112
MHz (mA) 3
Peripherals disabled
Peripherals enabled
Peripherals disabled
RUN@64 MHz RUN@80 MHz
(mA)
(mA)
Peripherals enabled
Peripherals disabled
RUN@48
MHz (mA)
Peripherals disabled
STOP2
(mA)
Peripherals enabled
STOP1
(mA)
Peripherals enabled use case 27
Peripherals enabled use case 16
Peripherals disabled 6
LPTMR enabled
VLPR (mA)
Typ
240
257
1.58
1.61
2.44
7.6
8.3
18.3
25.7
25.5
31.9
29.8
38
41.5
53.1
373
Max
740
791
2.32
2.34
NA
9.9
10.9
23.1
30.2
27.8
35.3
33.8
40.7
44.9
57.4
423
Typ
NA
NA
NA
NA
2.84
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Max
1637
1694
3.1
3.21
NA
12.7
13.7
25
32.9
30.7
38.8
36
43.8
NA
450
Typ
29.8
42
1.48
1.50
2.91
7
7.7
19.7
26.9
25.1
33.3
30.2
39.6
43.3
55.6
378
Typ
150
159
1.72
1.85
3.08
7.2
8.1
20.4
27.1
26.1
33.5
30.5
40
43.9
56.1
381
Max
359
384
2.60
2.65
NA
9.2
9.9
23.2
29.6
29.3
36.2
34.8
42.1
46.3
59.7
435
Typ
256
273
1.80
2.10
3.23
7.8
8.5
20.6
27.4
26.6
33.8
31.2
40.5
44.8
57.1
390
Max
850
900
2.65
2.70
NA
10.3
11.1
23.9
30.6
30.3
37.3
35.6
43.5
47.9
61.3
445
Typ
NA
NA
NA
NA
3.65
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Max
1960
1998
3.18
3.25
NA
12.9
13.8
26.9
33.6
35
40.3
38.7
46.8
NA
484
25
Typ
35
48
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NA
TBD
85
Typ
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NA
TBD
Max
TBD
TBD
TBD
TBD
NA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NA
TBD
105
125
S32K14xW
Peripherals disabled 5
S32K1xx Data Sheet, Rev. 13, 04/2020
Ambient Temperature (°C)
Chip/Device
VLPS (μA) 2
General
22
Table 13. Power consumption (Typicals unless stated otherwise) 1 (continued)
NXP Semiconductors
105
125
Typ
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NA
TBD
Max
TBD
TBD
TBD
TBD
NA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NA
TBD
Typ
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Table continues on the next page...
IDD/MHz (μA/MHz) 4
Peripherals disabled
HSRUN@112
MHz (mA) 3
NA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NA
TBD
Typ
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
NA
NA
NA
Max
TBD
TBD
TBD
8
NA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
70
NA
TBD
25
Typ
37
47
1.57
1.61
3.3
8
9.2
23.4
31.4
30.5
40.2
36.2
47.6
52
68.3
452
85
Typ
207
209
1.79
1.83
3.54
8.9
10.1
24.4
32.4
31.5
41.3
37.2
48.7
53.3
69.8
465
Max
974
981
3.32
3.38
NA
12.7
13.9
29.3
37.9
36.7
47
42.4
54.4
60.3
78
530
Peripherals enabled
TBD
Peripherals enabled
TBD
Peripherals enabled
TBD
LPTMR enabled
Peripherals enabled
Peripherals disabled
RUN@64 MHz RUN@80 MHz
(mA)
(mA)
Peripherals disabled
RUN@48
MHz (mA)
Peripherals disabled
STOP2
(mA)
Peripherals enabled use case 27
Peripherals disabled 6
STOP1
(mA)
TBD
105
Typ
419
422
1.99
2.04
3.78
9.8
11
25.3
33.4
32.5
42.2
38.1
49.6
54.4
70.8
477
Max
2004
2017
4.06
4.13
NA
17.1
18.3
34.1
42.6
41.3
51.4
46.9
58.8
65.7
82.8
587
Typ
NA
NA
NA
NA
4.44
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Max
3358
3380
5.28
5.38
NA
22.6
23.7
40.2
48.8
47.3
57.4
52.8
64.8
NA
660
25
Typ
38
54
2.17
2.20
3.45
8.5
9.6
27.6
34.9
35.5
45.3
42.1
57.7
60.3
83.3
526
85
Typ
336
357
2.30
2.35
3.74
10.1
11.1
29.1
37.0
36.8
46.6
43.4
59.9
62.9
88.7
543
Max
1660
1736
3.48
3.55
NA
14.5
15.6
34.8
43.6
41.9
53.9
48.7
65.1
70.4
96.1
609
Typ
560
577
2.49
2.54
4.03
10.9
11.9
29.8
37.8
37.6
47.5
45.2
61.5
63.8
89.1
565
Max
2945
2970
4.40
4.47
NA
18.0
19.0
38.4
46.8
44.9
55.3
51.6
66.8
73.6
97.4
645
125
S32K1488
VLPR (mA)
Max
150
S32K146
Peripherals disabled 5
S32K1xx Data Sheet, Rev. 13, 04/2020
Ambient Temperature (°C)
Chip/Device
VLPS (μA) 2
Peripherals enabled use case 16
NXP Semiconductors
Table 13. Power consumption (Typicals unless stated otherwise) 1 (continued)
105
125
NA
NA
NA
NA
4.85
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
3990
4166
6.00
6.08
NA
23.4
24.5
44.3
52.5
50.9
61.3
57.5
71.6
NA
719
23
General
Typ
Max
2.
3.
4.
5.
6.
7.
8.
Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes
VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise stated. All output pins are floating and On-chip pulldown is enabled for
all unused input pins.
Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation.
HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.
Values mentioned for S32K14x devices are measured at RUN@80 MHz with peripherals disabled and values mentioned for S32K11x devices are measured at
RUN@48 MHz with peripherals disabled.
With PMC_REGSC[CLKBIASDIS] set to 1. See Reference Manual for details.
Data collected using RAM
Numbers on limited samples size and data collected with Flash
The S32K148 data points assume that ENET/QuadSPI/SAI etc. are inactive.
General
24
1.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
NXP Semiconductors
Table 14. VLPS additional use-case power consumption at typical conditions 1, 2, 3
Use-case
VLPS and RTC
VLPS and
LPUART TX/RX
S32K1xx Data Sheet, Rev. 13, 04/2020
VLPS and
LPUART wake-up
VLPS and LPI2C
master
VLPS and LPI2C
slave wake-up
VLPS and LPSPI
master 4
VLPS and LPIT
Description
• Clock source: LPO or
RTC_CLKIN
• Clock source: SIRC
• Transmiting or receiving
continuously using DMA
• Baudrate: 19.2 kbps
• Clock source: SIRC
• Wake-up address feature
enabled
• Baudrate: 19.2 kbps
• Clock Source: SIRC
• Transmit/receive using DMA
• Baudrate: 100 kHz
• Clock source: SIRC
• Wake-up address feature
enabled
• Baudrate: 100 kHz
• Clock source: SIRC
• Transmit/receive using DMA
• Baudrate: 500 kHz
• Clock source: SIRC
• 1 channel enable
• Mode: 32-bit periodic counter
Temp.
Device
Unit
S32K116
S32K118
S32K142
S32K144
S32K14x
W
S32K146
S32K148
25
30
30
30
31
TBD
38
40
μA
85
96
102
148
170
TBD
227
356
μA
105
179
189
280
290
TBD
460
600
μA
125
281
327
570
680
TBD
810
1250
μA
25
179
187
230
230
TBD
250
250
μA
85
235
244
320
400
TBD
410
490
μA
105
304
325
490
550
TBD
600
850
μA
125
499
551
890
1070
TBD
1250
1960
μA
25
107
107
135
138
TBD
146
146
μA
85
149
157
170
240
TBD
280
350
μA
105
199
223
260
400
TBD
480
600
μA
125
347
405
530
580
TBD
1000
1280
μA
25
600
600
670
690
TBD
820
900
μA
85
696
712
880
960
TBD
1220
1370
μA
105
815
852
1080
1250
TBD
1660
2060
μA
125
1152
1251
1970
1980
TBD
2860
3690
μA
25
260
260
260
260
TBD
270
280
μA
85
293
308
340
340
TBD
410
510
μA
105
339
367
430
430
TBD
610
810
μA
125
478
543
740
760
TBD
1170
1540
μA
25
2.51
2.94
2.99
3.19
TBD
3.75
4.11
mA
2.67
3.09
3.26
3.7
TBD
4.35
4.93
mA
2.83
3.21
3.5
4.2
TBD
4.93
5.74
mA
125
3.34
3.53
3.93
4.63
TBD
5.97
7.38
mA
25
114
114
114
114
TBD
120
130
μA
85
158
164
190
250
TBD
260
320
μA
105
210
223
310
410
TBD
440
570
μA
125
371
408
640
750
TBD
910
1280
μA
25
General
85
105
4.
All power numbers listed in this table are typical power numbers
Current numbers are quoted for a certain application code and may vary on user configuration and silicon process variation.
The power numbers are not strictly for the VLPS mode operation alone, but also includes power due to periodic wakeup. The power therefore includes wakeup
plus VLPS mode activity. This leads to greater dependence of power numbers on application code.
The single LPSPI used is LPSPI1 in S32K14X devices but LPSPI0 in S32K11x devices.
General
26
1.
2.
3.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
General
The following table shows the power consumption targets for S32K148 in various mode
of operations measure at 3.3 V.
Table 15. Power consumption at 3.3 V
Chip/Device
Ambient
Temperature
(°C)
S32K148
HSRUN@112 MHz (mA)1
RUN@80 MHz (mA)
Peripherals
enabled +
QSPI
Peripherals
enabled +
ENET + SAI
Peripherals
enabled +
QSPI
Peripherals
enabled +
ENET + SAI
25
Typ
67.3
79.1
89.8
105.5
85
Typ
67.4
79.2
95.6
105.9
Max
82.5
88.2
109.7
117.4
Typ
68.0
79.8
96.6
106.7
Max
80.3
89.1
109.0
119.0
Max
83.5
94.7
105
125
NA
1. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C.
4.8 ESD handling ratings
Symbol
Description
VHBM
Electrostatic discharge voltage, human body model
VCDM
Electrostatic discharge voltage, charged-device model
ILAT
Min.
Max.
Unit
Notes
− 4000
4000
V
1
2
All pins except the corner pins
− 500
500
V
Corner pins only
− 750
750
V
Latch-up current at ambient temperature of 125 °C
− 100
100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4.9 EMC radiated emissions operating behaviors
EMC measurements to IC-level IEC standards are available from NXP on request.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
27
I/O parameters
5 I/O parameters
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 8. Input signal measurement reference
5.2 General AC specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 16. General switching specifications
Symbol
WFRST
WNFRST
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous path
50
—
ns
3
RESET input filtered pulse
—
10
ns
4
Maximum of
(100 ns, bus
clock period)
—
ns
5
RESET input not filtered pulse
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in
that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.
4. Maximum length of RESET pulse which will be the filtered by internal filter only if PCR_PTA5[PFE] is at its reset value of
1'b1.
5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter only if PCR_PTA5[PFE] is at its reset
value of 1'b1. This number depends on the bus clock period also. In this case, minimum pulse width which will cause reset
is 250 ns. For faster clock frequencies which have clock period less than 100 ns, the minimum pulse width not filtered will
S32K1xx Data Sheet, Rev. 13, 04/2020
28
NXP Semiconductors
I/O parameters
be 100 ns. After this filtering mechanism, the software has an option to put additional filtering in addition to this, by means
of PCM_RPC register and/or PORT_DFER register for PTA5.
5.3 DC electrical specifications at 3.3 V Range
NOTE
For details on the pad types defined in Table 17 and Table 19,
see Reference Manual section IO Signal Table and IO Signal
Description Input Multiplexing sheet(s) attached with
Reference Manual.
Table 17. DC electrical specifications at 3.3 V Range for S32K1xx series
Symbol
Parameter
Value
Unit
Notes
Min.
Typ.
Max.
2.7
3.3
4
V
1
VDD
I/O Supply Voltage
Vih
Input Buffer High Voltage
0.7 × VDD
—
VDD + 0.3
V
2
Vil
Input Buffer Low Voltage
VSS − 0.3
—
0.3 × VDD
V
3
0.06 × VDD
—
—
V
3.5
—
—
mA
I/O current sink capability measured when
pad Vol = 0.8 V
3
—
—
mA
IohGPIO-HD_DSE_1
I/O current source capability measured when
pad Voh = (VDD − 0.8 V)
14
—
—
mA
4
IolGPIO-HD_DSE_1
I/O current sink capability measured when
pad Vol = 0.8 V
12
—
—
mA
4
IohGPIO-FAST_DSE_0
I/O current sink capability measured when
pad Voh=VDD-0.8 V
9.5
—
—
mA
5
IolGPIO-FAST_DSE_0
I/O current sink capability measured when
pad Vol = 0.8 V
10
—
—
mA
5
IohGPIO-FAST_DSE_1
I/O current sink capability measured when
pad Voh=VDD-0.8 V
16
—
—
mA
5
IolGPIO-FAST_DSE_1
I/O current sink capability measured when
pad Vol = 0.8 V
15.5
—
—
mA
5
—
—
100
mA
Vhys
IohGPIO
IohGPIO-HD_DSE_0
IolGPIO
IolGPIO-HD_DSE_0
IOHT
IIN
Input Buffer Hysteresis
I/O current source capability measured when
pad Voh = (VDD − 0.8 V)
Output high current total for all ports
Input leakage current (per pin) for full temperature range at VDD = 3.3 V
All pins other than high drive port pins
High drive port pins
7
6
0.005
0.5
μA
0.010
0.5
μA
RPU
Internal pullup resistors
20
60
kΩ
8
RPD
Internal pulldown resistors
20
60
kΩ
9
1. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to
operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.
2. For reset pads, same Vih levels are applicable
3. For reset pads, same Vil levels are applicable
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
29
I/O parameters
4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard
value given above.
5. For refernce only. Run simulations with the IBIS model and custom board for accurate results.
6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
other GPIOs are normal drive only. For details see IO Signal Description Input Multiplexing sheet(s) attached with the
Reference Manual.
7. When using ENET and SAI on S32K148, the overall device limits associated with high drive pin configurations must be
respected i.e. On 144-pin LQFP the general purpose pins: PTA10, PTD0, and PTE4 must be set to low drive.
8. Measured at input V = VSS
9. Measured at input V = VDD
Table 18. DC electrical specifications at 3.3 V Range for S32K14xW series
Symbol
Parameter
Value
Unit
Min.
Typ.
Max.
3.13
3.3
4
V
Notes
VDD
I/O Supply Voltage
Vih
Input Buffer High Voltage
0.7 × VDD
—
VDD + 0.3
V
1
Vil
Input Buffer Low Voltage
VSS − 0.3
—
0.3 × VDD
V
2
0.06 × VDD
—
—
V
3.5
—
—
mA
I/O current sink capability measured when
pad Vol = 0.8 V
3
—
—
mA
IohGPIO-HD_DSE_1
I/O current source capability measured when
pad Voh = (VDD − 0.8 V)
14
—
—
mA
3
IolGPIO-HD_DSE_1
I/O current sink capability measured when
pad Vol = 0.8 V
12
—
—
mA
3
Output high current total for all ports
—
—
100
mA
Vhys
IohGPIO
IohGPIO-HD_DSE_0
IolGPIO
IolGPIO-HD_DSE_0
IOHT
IIN
Input Buffer Hysteresis
I/O current source capability measured when
pad Voh = (VDD − 0.8 V)
Input leakage current (per pin) for full temperature range at VDD = 3.3 V
4
All pins other than high drive port pins
0.005
0.5
μA
High drive port pins
0.010
0.5
μA
RPU
Internal pullup resistors
20
60
kΩ
5
RPD
Internal pulldown resistors
20
60
kΩ
6
1. For reset pads, same Vih levels are applicable
2. For reset pads, same Vil levels are applicable
3. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard
value given above.
4. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
other GPIOs are normal drive only. For details see IO Signal Description Input Multiplexing sheet(s) attached with the
Reference Manual.
5. Measured at input V = VSS
6. Measured at input V = VDD
S32K1xx Data Sheet, Rev. 13, 04/2020
30
NXP Semiconductors
I/O parameters
5.4 DC electrical specifications at 5.0 V Range
Table 19. DC electrical specifications at 5.0 V Range for S32K1xx series
Symbol
Parameter
Value
Unit
Min.
Typ.
Max.
4
—
5.5
V
Notes
VDD
I/O Supply Voltage
Vih
Input Buffer High Voltage
0.65 x
VDD
—
VDD + 0.3
V
1
Vil
Input Buffer Low Voltage
VSS − 0.3
—
0.35 x VDD
V
2
0.06 x
VDD
—
—
V
I/O current source capability measured
when pad Voh= (VDD - 0.8 V)
5
—
—
mA
I/O current sink capability measured
when pad Vol= 0.8 V
5
—
—
mA
IohGPIO-HD_DSE_1
I/O current source capability measured
when pad Voh = VDD - 0.8 V
20
—
—
mA
3
IolGPIO-HD_DSE_1
I/O current sink capability measured
when pad Vol = 0.8 V
20
—
—
mA
3
IohGPIO-FAST_DSE_0
I/O current sink capability measured
when pad Voh = VDD - 0.8 V
14.0
—
—
mA
4
IolGPIO-FAST_DSE_0
I/O current sink capability measured
when pad Vol= 0.8 V
14.5
—
—
mA
4
IohGPIO-FAST_DSE_1
I/O current sink capability measured
when pad Voh = VDD - 0.8 V
21
—
—
mA
4
IolGPIO-FAST_DSE_1
I/O current sink capability measured
when pad Vol= 0.8 V
20.5
—
—
mA
4
IOHT
Output high current total for all ports
—
—
100
mA
Vhys
IohGPIO
IohGPIO-HD_DSE_0
IolGPIO
IolGPIO-HD_DSE_0
IIN
Input Buffer Hysteresis
Input leakage current (per pin) for full temperature range at VDD = 5.5 V
5
All pins other than high drive port pins
0.005
0.5
μA
High drive port pins
0.010
0.5
μA
RPU
Internal pullup resistors
20
50
kΩ
6
RPD
Internal pulldown resistors
20
50
kΩ
7
1.
2.
3.
4.
5.
For reset pads, same Vih levels are applicable
For reset pads, same Vil levels are applicable
The strong pad I/O pin is capable of switching a 50 pF load up to 40 MHz.
For refernce only. Run simulations with the IBIS model and custom board for accurate results.
Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
other GPIOs are normal drive only. For details see IO Signal Description Input Multiplexing sheet(s) attached with the
Reference Manual.
6. Measured at input V = VSS
7. Measured at input V = VDD
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
31
I/O parameters
Table 20. DC electrical specifications at 5.0 V Range for S32K14xW series
Symbol
Parameter
Value
Unit
Min.
Typ.
Max.
4
—
5.5
V
Notes
VDD
I/O Supply Voltage
Vih
Input Buffer High Voltage
0.65 x
VDD
—
VDD + 0.3
V
-1
Vil
Input Buffer Low Voltage
VSS − 0.3
—
0.35 x VDD
V
1
0.06 x
VDD
—
—
V
I/O current source capability measured
when pad Voh= (VDD - 0.8 V)
5
—
—
mA
I/O current sink capability measured
when pad Vol= 0.8 V
5
—
—
mA
IohGPIO-HD_DSE_1
I/O current source capability measured
when pad Voh = VDD - 0.8 V
20
—
—
mA
2
IolGPIO-HD_DSE_1
I/O current sink capability measured
when pad Vol = 0.8 V
20
—
—
mA
2
IOHT
Output high current total for all ports
—
—
100
mA
Vhys
Input Buffer Hysteresis
IohGPIO
IohGPIO-HD_DSE_0
IolGPIO
IolGPIO-HD_DSE_0
IIN
Input leakage current (per pin) for full temperature range at VDD = 5.5 V
3
All pins other than high drive port pins
0.005
0.5
μA
High drive port pins
0.010
0.5
μA
RPU
Internal pullup resistors
20
50
kΩ
4
RPD
Internal pulldown resistors
20
50
kΩ
5
1. For reset pads, same Vil levels are applicable
2. The strong pad I/O pin is capable of switching a 50 pF load up to 40 MHz.
3. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All
other GPIOs are normal drive only. For details see IO Signal Description Input Multiplexing sheet(s) attached with the
Reference Manual
4. Measured at input V = VSS
5. Measured at input V = VDD
5.5 AC electrical specifications at 3.3 V range
Table 21. AC electrical specifications at 3.3 V Range for S32K1xx series
Symbol
tRFGPIO
tRFGPIO-HD
DSE
NA
0
Rise time (nS) 1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max.
Min.
Max.
3.2
14.5
3.4
15.7
25
5.7
23.7
6.0
26.2
50
20.0
80.0
20.8
88.4
200
3.2
14.5
3.4
15.7
25
5.7
23.7
6.0
26.2
50
20.0
80.0
20.8
88.4
200
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
32
NXP Semiconductors
I/O parameters
Table 21. AC electrical specifications at 3.3 V Range for S32K1xx series (continued)
Symbol
DSE
1
tRFGPIO-FAST
0
1
Rise time (nS) 1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max.
Min.
Max.
1.5
5.8
1.7
6.1
25
2.4
8.0
2.6
8.3
50
6.3
22.0
6.0
23.8
200
0.6
2.8
0.5
2.8
25
3.0
7.1
2.6
7.5
50
12.0
27.0
10.3
26.8
200
0.4
1.3
0.38
1.3
25
1.5
3.8
1.4
3.9
50
7.4
14.9
7.0
15.3
200
1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be
different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections.
Table 22. AC electrical specifications at 3.3 V Range for S32K14xW series
Symbol
tRFGPIO
tRFGPIO-HD
DSE
NA
0
1
Rise time (nS) 1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max.
Min.
Max.
3.2
14.5
3.4
15.7
25
5.7
23.7
6.0
26.2
50
20.0
80.0
20.8
88.4
200
3.2
14.5
3.4
15.7
25
5.7
23.7
6.0
26.2
50
20.0
80.0
20.8
88.4
200
1.5
5.8
1.7
6.1
25
2.4
8.0
2.6
8.3
50
6.3
22.0
6.0
23.8
200
1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be
different. For protocol specific AC specifications, see respective sections.
5.6 AC electrical specifications at 5 V range
Table 23. AC electrical specifications at 5 V Range for S32K1xx series
Symbol
tRFGPIO
DSE
NA
Rise time (nS)1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max .
Min.
Max.
2.8
9.4
2.9
10.7
25
5.0
15.7
5.1
17.4
50
17.3
54.8
17.6
59.7
200
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
33
I/O parameters
Table 23. AC electrical specifications at 5 V Range for S32K1xx series (continued)
Symbol
tRFGPIO-HD
DSE
0
1
tRFGPIO-FAST
0
1
Rise time (nS)1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max .
Min.
Max.
2.8
9.4
2.9
10.7
25
5.0
15.7
5.1
17.4
50
17.3
54.8
17.6
59.7
200
1.1
4.6
1.1
5.0
25
2.0
5.7
2.0
5.8
50
5.4
16.0
5.0
16.0
200
0.42
2.2
0.37
2.2
25
2.0
5.0
1.9
5.2
50
9.3
18.8
8.5
19.3
200
0.37
0.9
0.35
0.9
25
1.2
2.7
1.2
2.9
50
6.0
11.8
6.0
12.3
200
1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be
different, for example for ENET, QSPI etc. . For protocol specific AC specifications, see respective sections.
Table 24. AC electrical specifications at 5 V Range for S32K14xW series
Symbol
tRFGPIO
tRFGPIO-HD
DSE
NA
0
1
Rise time (nS)1
Fall time (nS) 1
Capacitance (pF) 2
Min.
Max .
Min.
Max.
2.8
9.4
2.9
10.7
25
5.0
15.7
5.1
17.4
50
17.3
54.8
17.6
59.7
200
2.8
9.4
2.9
10.7
25
5.0
15.7
5.1
17.4
50
17.3
54.8
17.6
59.7
200
1.1
4.6
1.1
5.0
25
2.0
5.7
2.0
5.8
50
5.4
16.0
5.0
16.0
200
1. For reference only. Run simulations with the IBIS model and your custom board for accurate results.
2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be
different. For protocol specific AC specifications, see respective sections.
5.7 Standard input pin capacitance
Table 25. Standard input pin capacitance
Symbol
CIN_D
Description
Min.
Max.
Unit
—
7
pF
Input capacitance: digital pins
S32K1xx Data Sheet, Rev. 13, 04/2020
34
NXP Semiconductors
I/O parameters
NOTE
Please refer to External System Oscillator electrical
specifications for EXTAL/XTAL pins.
5.8 Device clock specifications
Table 26. Device clock specifications 1
Symbol
Description
High Speed run
Min.
Max.
Unit
mode2
fSYS
System and core clock
—
112
MHz
fBUS
Bus clock
—
56
MHz
Flash clock
—
28
MHz
fFLASH
Normal run mode (S32K11x series)
fSYS
System and core clock
—
48
MHz
fBUS
Bus clock
—
48
MHz
—
24
MHz
—
80
MHz
Bus clock
—
404
MHz
Flash clock
—
26.67
MHz
—
80
MHz
—
404
MHz
—
20
MHz
fFLASH
Flash clock
Normal run mode (S32K14x series)
fSYS
fBUS
fFLASH
3
System and core clock
Normal run mode (S32K14xW series) 5
fSYS
fBUS
fFLASH
System and core clock
Bus clock
Flash clock
VLPR mode (S32K1xx
series)6
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fERCLK
External reference clock
—
16
MHz
VLPR mode (S32K14xW
1.
2.
3.
4.
5.
6.
series)6
fSYS
System and core clock
—
1
MHz
fBUS
Bus clock
—
1
MHz
fFLASH
Flash clock
—
0.25
MHz
fERCLK
External reference clock
—
TBD
MHz
Refer to the section Feature comparison for the availability of modes and other specifications.
Only available on some devices. See section Feature comparison.
With SPLL as system clock source.
48 MHz when fSYS is 48 MHz
With SPLL as system clock source.
The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
35
Peripheral operating requirements and behaviors
6 Peripheral operating requirements and behaviors
6.1 System modules
There are no electrical specifications necessary for the device's system modules.
6.2 Clock interface modules
6.2.1 External System Oscillator electrical specifications
S32K1xx Data Sheet, Rev. 13, 04/2020
36
NXP Semiconductors
Clock interface modules
Single input comparator
(EXTAL WAVE)
ref_clk
Mux
Differential input comparator
(HG/LP mode)
Peak detector
LP mode
Driver
(HG/LP mode)
Pull down resistor (OFF)
ESD PAD
280 ohms
ESD PAD
40 ohms
XTAL pin
EXTAL pin
Series resistor for current
limitation
1M ohms Feedback Resistor
Crystal or resonator
C1
C2
Figure 9. Oscillator connections scheme
Table 27. External System Oscillator electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
gmXOSC
Crystal oscillator transconductance
SCG_SOSCCFG[RANGE]=2'b10 for 4-8 MHz
2.2
—
13.7
mA/V
SCG_SOSCCFG[RANGE]=2'b11 for 8-40 MHz
16
—
47
mA/V
VIL
Input low voltage — EXTAL pin in external clock mode
VIH
Input high voltage — EXTAL pin in external clock
mode
C1
Notes
VSS
—
1.15
V
0.7 * VDD
—
VDD
V
EXTAL load capacitance
—
—
—
1
C2
XTAL load capacitance
—
—
—
1
RF
Feedback resistor
Low-gain mode (HGO=0)
2
—
—
—
MΩ
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
37
Clock interface modules
Table 27. External System Oscillator electrical specifications
(continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
1
—
MΩ
Low-gain mode (HGO=0)
—
0
—
kΩ
High-gain mode (HGO=1)
—
0
—
kΩ
High-gain mode (HGO=1)
,3
RS
Notes
Series resistor
Vpp_XTAL
Peak-to-peak amplitude of oscillation (oscillator mode) at XTAL
4
Low-gain mode (HGO=0)
—
1.0
—
V
High-gain mode (HGO=1)
—
3.3
—
V
Vpp_EXTAL Peak-to-peak amplitude of oscillation (oscillator mode) at EXTAL
VSOSCOP
4, 5
Low-gain mode (HGO=0)
0.8
—
—
V
High-gain mode (HGO=1), VDD= 4.0 V to 5.5 V
1.7
—
—
V
Oscillation operating point
4
High-gain mode (HGO=1)
1.15
—
—
V
1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as:
gm_crit = 4 * (ESR + RS) * (2πF)2 * (C0 + CL)2
where:
•
•
•
•
•
•
•
•
gmXOSC is the transconductance of the internal oscillator circuit
ESR is the equivalent series resistance of the external crystal
RS is the series resistance connected between XTAL pin and external crystal for current limitation
F is the external crystal oscillation frequency
C0 is the shunt capacitance of the external crystal
CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)]
Cs is stray or parasitic capacitance on the pin due to any PCB traces
C1, C2 external load capacitances on EXTAL and XTAL pins
See manufacture datasheet for external crystal component values
• When low-gain is selected, internal RF will be selected and external RF should not be attached.
• When high-gain is selected, external RF (1 M Ohm) needs to be connected for proper operation of the crystal. For
external resistor, up to 5% tolerance is allowed.
3. RS should be selected carefully to have appropriate oscillation amplitude for both protecting crystal or resonator device and
satisfying proper oscillation startup condition.
4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
5. Minimum value is shown as a reference only, however the HW design needs to ensure it reaches the maximum value by
following the guidelines given in above notes (notes 1, 2, and 3) and performs the required robustness testing at the
application level. During testing, a low capacitance probe (< 5 pF ) must be used to avoid any decrease in the Vpp_EXTAL
value.
2.
6.2.2 External System Oscillator frequency specifications
S32K1xx Data Sheet, Rev. 13, 04/2020
38
NXP Semiconductors
NXP Semiconductors
Table 28. External System Oscillator frequency specifications
Symbol
Description
Min.
S32K14x/
S32K14xW
fosc_hi
S32K1xx Data Sheet, Rev. 13, 04/2020
4.
S32K11x
S32K14x/
S32K14xW
Max.
S32K11x
Oscillator crystal or resonator
frequency
4
—
fec_extal
Input clock frequency (external clock
mode)
—
—
tdc_extal
Input clock duty cycle (external clock
mode)
48
50
8 MHz low-gain mode (HGO=0)
—
8 MHz high-gain mode (HGO=1)
tcst
1.
2.
3.
Typ.
S32K14x/
S32K14xW
Unit
Notes
S32K11x
40 1, 2
50
MHz
48
MHz
3
52
%
3
1.5
—
ms
4
—
2.5
—
40 MHz low-gain mode (HGO=0)
—
2
—
40 MHz high-gain mode (HGO=1)
—
2
—
Crystal Start-up Time
For an ideal clock of 40 MHz, if permitted by application requirements, an error of +/- 5% is supported with 50% duty cycle.
In S32K14xW, when sourcing ADC clock from oscillator, a better duty cycle is expected.
Frequencies below 40 MHz can be used for degraded duty cycle upto 40-60%. In S32K14xW, when sourcing ADC clock from oscillator, a better duty cycle is
expected. To cater for the duty cycle requirement or to limit the ADC clock to ≤ fADCK, the divider ADCn.ADC_CFG1[ADICLK] for the specific ADC instance can be
used.
Proper PC board layout procedures must be followed to achieve specifications.
Clock interface modules
39
System Clock Generation (SCG) specifications
6.2.3 System Clock Generation (SCG) specifications
6.2.3.1
Fast internal RC Oscillator (FIRC) electrical specifications
Table 29. Fast internal RC Oscillator electrical specifications for S32K1xx series
Parameter1
Symbol
Value
Unit
Min.
Typ.
Max.
FIRC target frequency
—
48
—
MHz
ΔF
Frequency deviation across process, voltage, and
temperature < 105°C
—
±0.5
±1
%FFIRC
ΔF125
Frequency deviation across process, voltage, and
temperature < 125°C
—
±0.5
±1.1
%FFIRC
TStartup
Startup time
3.4
5
µs2
TJIT, 3
Cycle-to-Cycle jitter
—
300
500
ps
Long term jitter over 1000 cycles
—
0.04
0.1
%FFIRC
FFIRC
3
TJIT
1. With FIRC regulator enable
2. Startup time is defined as the time between clock enablement and clock availability for system use.
3. FIRC as system clock
Table 30. Fast internal RC Oscillator electrical specifications for S32K14xW series
Parameter1
Symbol
FFIRC
ΔF
Value
Unit
Min.
Typ.
Max.
FIRC target frequency
—
48
—
MHz
Frequency deviation across process, voltage, and
temperature
—
±0.5
±1.4
%FFIRC
3.4
5
µs2
TStartup
Startup time
TJIT, 3
Cycle-to-Cycle jitter
—
300
500
ps
Long term jitter over 1000 cycles
—
0.04
0.1
%FFIRC
3
TJIT
1. With FIRC regulator enable
2. Startup time is defined as the time between clock enablement and clock availability for system use.
3. FIRC as system clock
NOTE
Fast internal RC oscillator is compliant with LIN when device
is used as a slave node.
S32K1xx Data Sheet, Rev. 13, 04/2020
40
NXP Semiconductors
System Clock Generation (SCG) specifications
6.2.3.2
Slow internal RC oscillator (SIRC) electrical specifications
Table 31. Slow internal RC oscillator (SIRC) electrical specifications for S32K1xx series
Symbol
Parameter
Value
Unit
Min.
Typ.
Max.
SIRC target frequency
—
8
—
MHz
ΔF
Frequency deviation across process, voltage, and
temperature < 105°C
—
—
±3
%FSIRC
ΔF125
Frequency deviation across process, voltage, and
temperature < 125°C
—
—
±3.3
%FSIRC
TStartup
Startup time
—
9
12.5
µs1
FSIRC
1. Startup time is defined as the time between clock enablement and clock availability for system use.
Table 32. Slow internal RC oscillator (SIRC) electrical specifications for S32K14xW series
Symbol
Parameter
FSIRC
ΔF
TStartup
Value
Unit
Min.
Typ.
Max.
SIRC target frequency
—
8
—
MHz
Frequency deviation across process, voltage, and
temperature
—
—
±3.3
%FSIRC
Startup time
—
9
12.5
µs1
1. Startup time is defined as the time between clock enablement and clock availability for system use.
6.2.4 Low Power Oscillator (LPO) electrical specifications
Table 33. Low Power Oscillator (LPO) electrical specifications
Symbol
FLPO
Tstartup
Parameter
Internal low power oscillator
frequency
Startup Time
Value
Unit
Min.
Typ.
Max.
S32K1xx/
S32K14xW
S32K1xx/
S32K14xW
S32K1xx
S32K14xW
113
128
139
141
—
—
20
kHz
µs
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
41
Memory and memory interfaces
6.2.5 SPLL electrical specifications
Table 34. SPLL electrical specifications
Symbol
Parameter
FSPLL_REF1
2
FSPLL_Input
Min.
Typ.
Max.
S32K1xx/
S32K14xW
S32K1xx/
S32K14xW
PLL Reference Frequency Range
8
—
PLL Input Frequency
8
—
S32K1xx
Unit
S32K14xW
16
MHz
40
48
MHz
FVCO_CLK
VCO output frequency
180
—
320
MHz
FSPLL_CLK
PLL output frequency
90
—
160
MHz
at FVCO_CLK 180 MHz
—
120
—
ps
at FVCO_CLK 320 MHz
—
75
—
ps
at FVCO_CLK 180 MHz
—
1350
—
ps
at FVCO_CLK 320 MHz
—
600
—
ps
± 4.47
—
± 5.97
%
JCYC_SPLL
JACC_SPLL
DUNL
TSPLL_LOCK
PLL Period Jitter
(RMS)3
PLL accumulated jitter over 1µs (RMS)3
Lock exit frequency tolerance
Lock detector detection
time4
—
—
150 ×
10-6
+ 1075(1/FSPLL_REF)
s
1. FSPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG
register of Reference Manual.
2. FSPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input
source could be derived from a crystal oscillator or some other external square wave clock source using OSC bypass
mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual.
3. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each
PCB and results will vary
4. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use.
6.3 Memory and memory interfaces
6.3.1 Flash memory module (FTFC/FTFM) electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.3.1.1
Symbol
Flash timing specifications — commands
Table 35. Flash command timing specifications for S32K14x series
Description1
S32K142
Typ
trd1blk
Read 1 Block
execution time
Max
S32K144
Typ
S32K146
Max
Typ
Max
S32K148
Typ
Max
32 KB flash
—
—
—
—
—
—
—
—
64 KB flash
—
0.5
—
0.5
—
0.5
—
—
Unit Notes
ms
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
42
NXP Semiconductors
Memory and memory interfaces
Table 35. Flash command timing specifications for S32K14x series (continued)
Description1
Symbol
S32K142
Typ
S32K144
Max
Typ
S32K146
Max
Typ
S32K148
Max
Typ
Max
Unit Notes
128 KB flash —
—
—
—
—
—
—
—
256 KB flash —
2
—
—
—
—
—
—
512 KB flash —
—
—
1.8
—
2
—
2
Read 1 Section
execution time
2 KB flash
—
75
—
75
—
75
—
75
4 KB flash
—
100
—
100
—
100
—
100
tpgmchk
Program Check
execution time
—
—
95
—
95
—
95
—
100
µs
tpgm8
Program Phrase —
execution time
90
225
90
225
90
225
90
225
µs
tersblk
Erase Flash
Block execution
time
32 KB flash
—
—
—
—
—
—
—
—
ms
2
64 KB flash
30
550
30
550
30
550
—
—
128 KB flash —
—
—
—
—
—
—
—
256 KB flash 250
2125
—
—
—
—
—
—
512 KB flash —
2
trd1sec
µs
—
250
4250
250
4250
250
4250
tersscr
Erase Flash
—
Sector execution
time
12
130
12
130
12
130
12
130
ms
tpgmsec1k
Program Section —
execution time
(1KB flash)
5
—
5
—
5
—
5
—
ms
trd1all
Read 1s All
Block execution
time
—
—
2.8
—
2.3
—
5.2
—
8.2
ms
trdonce
Read Once
execution time
—
—
30
—
30
—
30
—
30
µs
tpgmonce
Program Once
execution time
—
90
—
90
—
90
—
90
—
µs
tersall
Erase All Blocks —
execution time
250
2800
400
4900
700
10000 1400
17000
ms
tvfykey
Verify Backdoor
Access Key
execution time
—
35
—
35
—
35
35
µs
tersallu
Erase All Blocks —
Unsecure
execution time
250
2800
400
4900
700
10000 1400
17000
ms
2
tpgmpart
Program
Partition for
EEPROM
execution time
32 KB
EEPROM
backup
70
—
70
—
70
—
—
—
ms
3
64 KB
EEPROM
backup
71
—
71
—
71
—
150
—
Control
Code 0xFF
0.08
—
0.08
—
0.08
—
0.08
—
ms
3
tsetram
Set FlexRAM
Function
execution time
—
—
2
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
43
Memory and memory interfaces
Table 35. Flash command timing specifications for S32K14x series (continued)
Symbol
Description1
S32K142
Typ
teewr8b
teewr16b
Byte write to
FlexRAM
execution time
16-bit write to
FlexRAM
execution time
S32K144
Max
Typ
S32K146
Max
Typ
Max
S32K148
Typ
Max
32 KB
EEPROM
backup
0.8
1.2
0.8
1.2
0.8
1.2
—
—
48 KB
EEPROM
backup
1
1.5
1
1.5
1
1.5
—
—
64 KB
EEPROM
backup
1.3
1.9
1.3
1.9
1.3
1.9
1.3
1.9
32 KB
EEPROM
backup
385
1700
385
1700
385
1700
—
—
48 KB
EEPROM
backup
430
1850
430
1850
430
1850
—
—
64 KB
EEPROM
backup
475
2000
475
2000
475
2000
475
4000
32 KB
EEPROM
backup
385
1700
385
1700
385
1700
—
—
48 KB
EEPROM
backup
430
1850
430
1850
430
1850
—
—
64 KB
EEPROM
backup
475
2000
475
2000
475
2000
475
4000
Unit Notes
µs
3,4
µs
3,4
teewr32bers
32-bit write to
—
erased FlexRAM
location
execution time
360
2000
360
2000
360
2000
360
2000
µs
teewr32b
32-bit write to
FlexRAM
execution time
32 KB
EEPROM
backup
630
2000
630
2000
630
2000
—
—
µs
3,4
48 KB
EEPROM
backup
720
2125
720
2125
720
2125
—
—
64 KB
EEPROM
backup
810
2250
810
2250
810
2250
810
4500
1st 32-bit
write
200
550
200
550
200
550
200
1100
µs
4,5,6
2nd through 150
Next to Last
(Nth-1) 32bit write
550
150
550
150
550
150
550
tquickwr
32-bit Quick
Write execution
time: Time from
CCIF clearing
(start the write)
until CCIF
setting (32-bit
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
44
NXP Semiconductors
Memory and memory interfaces
Table 35. Flash command timing specifications for S32K14x series (continued)
Description1
Symbol
S32K142
Typ
write complete,
ready for next
32-bit write)
tquickwrClnup Quick Write
Cleanup
execution time
Max
S32K144
Typ
Last (Nth)
200
32-bit write
(time for
write only,
not cleanup)
550
—
(# of —
Quick
Writes
) * 2.0
—
200
S32K146
Max
Typ
Max
S32K148
Typ
550
200
550
200
(# of
Quick
Writes )
* 2.0
—
(# of —
Quick
Writes
) * 2.0
Max
Unit Notes
550
(# of
Quick
Writes
) * 2.0
ms
7
1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external
clocks).
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may
be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM
issues detected.
4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the
times shown.
5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur
after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record
set will still be valid and the new records will be discarded.
6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,
assuming still powered. Or via SETRAM cleanup execution command is requested at a later point.
Table 36. Flash command timing specifications for S32K14xW series
S32K142W
Description-1
Symbol
trd1blk
Max
Typ
Max
Unit
Notes
64 KB flash
—
0.5
—
0.5
256 KB flash
—
2.5
—
—
512 KB flash
—
—
—
2.5
Read 1 Section
execution time
2 KB flash
—
95
—
95
4 KB flash
—
125
—
125
tpgmchk
Program Check
execution time
—
—
125
—
125
µs
tpgm8
Program Phrase
execution time
—
100
250
100
250
µs
tersblk
Erase Flash Block
execution time
64 KB flash
35
610
35
610
ms
-1
256 KB flash
140
2340
—
—
512 KB flash
—
—
280
4675
-1
trd1sec
Read 1 Block
execution time
Typ
S32K144W
ms
µs
tersscr
Erase Flash Sector
execution time
—
15
150
15
150
ms
tpgmsec
Program Section
execution time
1 KB flash
5.5
—
5.5
—
ms
trd1all
Read 1s All Block
execution time
—
—
3.5
—
4.5
ms
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
45
Memory and memory interfaces
Table 36. Flash command timing specifications for S32K14xW series (continued)
S32K142W
Symbol
Description-1
Typ
S32K144W
Max
Typ
Max
Unit
Notes
trdonce
Read Once
execution time
—
—
38
—
38
µs
tpgmonce
Program Once
execution time
—
100
—
100
—
µs
tersall
Erase All Blocks
execution time
—
160
2700
310
5300
ms
tvfykey
Verify Backdoor
Access Key
execution time
—
—
45
—
45
µs
tersallu
Erase All Blocks
—
Unsecure execution
time
160
2700
310
5300
ms
-1
tpgmpart
Program Partition for 32 KB EEPROM
EEPROM execution backup
time
64 KB EEPROM
backup
77
—
77
—
ms
-1
78
—
78
—
Control Code 0xFF 0.10
—
0.10
—
ms
-1
32 KB EEPROM
backup
1.0
1.5
1.0
1.5
48 KB EEPROM
backup
1.2
1.8
1.2
1.8
64 KB EEPROM
backup
1.4
2.1
1.4
2.1
32 KB EEPROM
backup
690
2200
690
2200
µs
-1,-1
48 KB EEPROM
backup
790
2350
790
2350
64 KB EEPROM
backup
890
2500
890
2500
1st 32-bit write
220
600
220
600
µs
-1,-1,-1
2nd through Next 165
to Last (Nth-1) 32bit write
600
165
600
Last (Nth) 32-bit
220
write (time for write
only, not cleanup)
600
220
600
tsetram
teewr32b
tquickwr
tquickwrClnup
Set FlexRAM
Function execution
time
32-bit write to
FlexRAM execution
time
32-bit Quick Write
execution time: Time
from CCIF clearing
(start the write) until
CCIF setting (32-bit
write complete,
ready for next 32-bit
write)
Quick Write Cleanup —
execution time
—
(# of
—
Quick
Writes ) *
2.0
(# of
ms
Quick
Writes ) *
2.0
-1
-1
S32K1xx Data Sheet, Rev. 13, 04/2020
46
NXP Semiconductors
Memory and memory interfaces
Table 37. Flash command timing specifications for S32K11x series
Description1
Symbol
S32K116
Typ
trd1blk
Read 1 Block execution
time
S32K118
Max
Typ
Max
32 KB flash
—
0.36
—
0.36
64 KB flash
—
—
—
—
128 KB flash
—
1.2
—
—
256 KB flash
—
—
—
2
512 KB flash
—
—
—
—
Unit
Notes
ms
trd1sec
Read 1 Section
execution time
2 KB flash
—
75
—
75
4 KB flash
—
100
—
100
tpgmchk
Program Check
execution time
—
—
100
—
100
µs
tpgm8
Program Phrase
execution time
—
90
225
90
225
µs
tersblk
Erase Flash Block
execution time
32 KB flash
15
300
15
300
ms
2
2
64 KB flash
—
—
—
—
128 KB flash
120
1100
—
—
256 KB flash
—
—
250
2125
512 KB flash
—
—
—
—
µs
tersscr
Erase Flash Sector
execution time
—
12
130
12
130
ms
tpgmsec1k
Program Section
execution time (1 KB
flash)
—
5
—
5
—
ms
trd1all
Read 1s All Block
execution time
—
—
1.7
—
2.8
ms
trdonce
Read Once execution
time
—
—
30
—
30
µs
tpgmonce
Program Once execution —
time
90
—
90
—
µs
tersall
Erase All Blocks
execution time
—
150
1500
230
2500
ms
tvfykey
Verify Backdoor Access
Key execution time
—
—
35
—
35
µs
tersallu
Erase All Blocks
—
Unsecure execution time
150
1500
230
2500
ms
2
tpgmpart
Program Partition for
32 KB EEPROM 71
EEPROM execution time backup
—
71
—
ms
3
64 KB EEPROM —
backup
—
—
—
Control Code
0xFF
—
0.08
—
ms
3
1.2
0.8
1.2
tsetram
Set FlexRAM Function
execution time
0.08
32 KB EEPROM 0.8
backup
2
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
47
Memory and memory interfaces
Table 37. Flash command timing specifications for S32K11x series (continued)
Symbol
Description1
S32K116
Typ
teewr8b
teewr16b
Byte write to FlexRAM
execution time
16-bit write to FlexRAM
execution time
S32K118
Max
Typ
Max
48 KB EEPROM —
backup
—
—
—
64 KB EEPROM —
backup
—
—
—
32 KB EEPROM 385
backup
1700
385
1700
48 KB EEPROM —
backup
—
—
—
64 KB EEPROM —
backup
—
—
—
32 KB EEPROM 385
backup
1700
385
1700
48 KB EEPROM —
backup
—
—
—
64 KB EEPROM —
backup
—
—
—
Unit
Notes
µs
3,4
µs
3,4
teewr32bers
32-bit write to erased
FlexRAM location
execution time
—
360
2000
360
2000
µs
teewr32b
32-bit write to FlexRAM
execution time
32 KB EEPROM 630
backup
2000
630
2000
µs
3,4
48 KB EEPROM —
backup
—
—
—
64 KB EEPROM —
backup
—
—
—
32-bit Quick Write
execution time: Time
from CCIF clearing (start
the write) until CCIF
setting (32-bit write
complete, ready for next
32-bit write)
1st 32-bit write
200
550
200
550
µs
4,5,6
2nd through Next 150
to Last (Nth-1)
32-bit write
550
150
550
Last (Nth) 32-bit
write (time for
write only, not
cleanup)
200
550
200
550
Quick Write Cleanup
execution time
—
—
(# of
—
Quick
Writes ) *
2.0
tquickwr
tquickwrClnup
(# of Quick
ms
Writes ) * 2.0
7
1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/external
clocks).
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may
be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM
issues detected.
4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2x the
times shown.
5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur
after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record
set will still be valid and the new records will be discarded.
S32K1xx Data Sheet, Rev. 13, 04/2020
48
NXP Semiconductors
Memory and memory interfaces
6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries.
7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes,
assuming still powered. Or via SETRAM cleanup execution command is requested at a later point.
NOTE
Under certain circumstances FlexMEM maximum times may be
exceeded. In this case the user or application may wait, or assert
reset to the FTFC/FTFM macro to stop the operation.
6.3.1.2
Symbol
Reliability specifications
Table 38. NVM reliability specifications
Description
Min.
Typ.
Max.
Unit
Notes
When using as Program and Data Flash
tnvmretp1k
Data retention after up to 1 K cycles
20
—
—
years
1
nnvmcycp
Cycling endurance
1K
—
—
cycles
2, 3
When using FlexMemory feature : FlexRAM as Emulated EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
—
—
years
1, 4
tnvmretee10
20
—
—
years
1
100 K
—
—
writes
1.6 M
—
—
writes
nnvmwree16
nnvmwree256
Data retention up to 10% of write endurance
Write endurance
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 256
5, 6, 7
1. Data retention period per block begins upon initial user factory programming or after each subsequent erase.
2. Program and Erase for PFlash and DFlash are supported across product temperature specification in Normal Mode (not
supported in HSRUN mode).
3. Cycling endurance is per DFlash or PFlash Sector.
4. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years.
5. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product
temperature specification in Normal Mode (not supported in HSRUN mode). Greater write endurance may be achieved
with larger ratios of EEPROM backup to FlexRAM.
6. For usage of any EEE driver other than the FlexMemory feature, the endurance spec will fall back to the specified
endurance value of the D-Flash specification (1K).
7. FlexMemory calculator tool is available at NXP web site for help in estimation of the maximum write endurance achievable
at specific EEPROM/FlexRAM ratios. The “In Spec” portions of the online calculator refer to the NVM reliability
specifications section of data sheet. This calculator is only applies to the FlexMemory feature.
6.3.2 QuadSPI AC specifications
The following table describes the QuadSPI electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
• Add 50 ohm series termination on board in QuadSPI SCK for Flash A to avoid loop
back reflection when using in Internal DQS (PAD Loopback) mode.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
49
Memory and memory interfaces
• QuadSPI trace length should be 3 inches.
• For non-Quad mode of operation if external device doesn’t have pull-up feature,
external pull-up needs to be added at board level for non-used pads.
• With external pull-up, performance of the interface may degrade based on load
associated with external pull-up.
S32K1xx Data Sheet, Rev. 13, 04/2020
50
NXP Semiconductors
NXP Semiconductors
Table 39. QuadSPI electrical specifications
FLASH PORT
Sym
Unit
FLASH A
QuadSPI Mode
RUN1
HSRUN1
SDR
SDR
Internal
Sampling
N1
Min
Max
FLASH B
Internal DQS
Internal
Sampling
PAD
Loopback
Internal
Loopback
Min
Min
Max
Max
Internal DQS
N1
Min
Max
RUN/HSRUN2
PAD
Loopback
Internal
Loopback
Min
Min
Max
Max
SDR
DDR3
Internal
Sampling
External DQS
N1
External DQS
Min
Max
Min
Max
Register Settings
S32K1xx Data Sheet, Rev. 13, 04/2020
MCR[DDR_EN]
-
0
0
0
0
0
0
0
1
MCR[DQS_EN]
-
0
1
1
0
1
1
0
1
MCR[SCLKCFG[0]]
-
-
1
0
-
1
0
-
-
MCR[SCLKCFG[1]]
-
-
1
0
-
1
0
-
-
MCR[SCLKCFG[2]]
-
-
-
-
-
-
-
-
0
MCR[SCLKCFG[3]]
-
-
-
-
-
-
-
-
0
MCR[SCLKCFG[5]]
-
0
0
0
0
0
0
0
1
SMPR[FSPHS]
-
0
1
0
0
1
0
0
0
SMPR[FSDLY]
-
0
0
0
0
0
0
0
0
-
0
23
-
0
30
-
-
SOCCR
[SOCCFG[7:0]]
SOCCR[SOCCFG[15:8]]
-
-
-
-
-
-
-
-
30
FLSHCR[TDH]
-
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
Timing Parameters
-
-
48
-
-
40
-
Table continues on the next page...
-
80
-
1/fSCK
-
64
1/fSCK
ns
-
1/fSCK
tSCK
38
1/fSCK
SCK Clock Period
-
1/fSCK
MHz
1/fSCK
fSCK
50
-
20
-
204
-
50.0
-
50.04
-
51
Memory and memory interfaces
SCK Clock Frequency
FLASH PORT
Sym
Unit
FLASH A
RUN1
HSRUN1
SDR
SDR
QuadSPI Mode
Internal
Sampling
N1
Min
Max
FLASH B
Internal DQS
Internal
Sampling
PAD
Loopback
Internal
Loopback
Min
Min
Max
Max
Internal DQS
N1
Min
Max
RUN/HSRUN2
PAD
Loopback
Internal
Loopback
Min
Min
Max
Max
SDR
DDR3
Internal
Sampling
External DQS
N1
External DQS
Min
Max
Min
Max
2.5
-
10
-
14
-
1.6
-
9
-
25
-
2
-
Data Input Hold Time
tIH
ns
0
-
1
-
1
-
0
-
1
-
1
-
0
-
20
-
Data Output Valid Time
tOV
ns
-
4.5
-
4.5
-
4.5
-
4
-
4
-
4
-
10
-
10
-
5
-
5
5
-
tSCK/2 - 2.5
tSCK/2 - 2.5
tSCK/2 - 1.5
tSCK/2 - 0.750
tSCK/2 - 0.750
tSCK/2 - 1.5
tSCK/2 - 1.5
tSCK/2 - 1.5
Data Output In-Valid
Time
tIV
ns
-
5
-
5
-
5
-
5
-
35
CS to SCK Time 6
tCSSCK
ns
5
-
5
-
5
-
5
-
5
-
5
-
10
-
10
-
SCK to CS Time 7
tSCKCS
ns
5
-
5
-
5
-
5
-
5
-
5
-
5
-
5
-
Output Load
NXP Semiconductors
1.
2.
3.
4.
5.
6.
7.
tSCK/2 + 2.5
-
tSCK/2 + 2.5
15
tSCK/2 + 1.5
ns
tSCK/2 + 1.5
tIS
tSCK/2 + 1.5
Data Input Setup Time
tSCK/2 + 1.5
ns
tSCK/2 + 1.5
tSDC
tSCK/2 - 1.5
S32K1xx Data Sheet, Rev. 13, 04/2020
SCK Duty Cycle
pf
25
25
See Reference Manual for details on mode settings
See Reference Manual for details on mode settings
Valid for HyperRAM only
RWDS(External DQS CLK) frequency
For operating frequency ≤ 64 Mhz,Output invalid time is 5 ns.
Program register value QuadSPI_FLSHCR[TCSS] = 4`h2
Program register value QuadSPI_FLSHCR[TCSH] = 4`h1
25
25
25
25
25
25
Memory and memory interfaces
52
Table 39. QuadSPI electrical specifications (continued)
Memory and memory interfaces
1
2
Clock
3
tSCK
tSDC
tSDC
SCK
CS
tIS
tIH
Data in
Figure 10. QuadSPI input timing (SDR mode) diagram
1
2
3
Clock
tSCK
tSDC
tSDC
SCK
tSCKCS
tCSSCK
CS
tIV
tOV
Data out
Invalid
Figure 11. QuadSPI output timing (SDR mode) diagram
TIS
TIS
TIH
TIH
D1
invalid
D2
invalid
D3
invalid
D4
invalid
D5
TIS– Setup Time
TIH – Hold Time
Figure 12. QuadSPI input timing (HyperRAM mode) diagram
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
53
Analog modules
SCK
tIV
tOV
Output Invalid Data
Figure 13. QuadSPI output timing (HyperRAM mode) diagram
6.4 Analog modules
6.4.1 ADC electrical specifications
6.4.1.1
12-bit ADC operating conditions
S32K1xx Data Sheet, Rev. 13, 04/2020
54
NXP Semiconductors
NXP Semiconductors
Table 40. 12-bit ADC operating conditions
Symbol
S32K1xx/
S32K14xW
S32K1xx
S32K14xW
Unit
Notes
S32K1xx Data Sheet, Rev. 13, 04/2020
See Voltage
and current
operating
requirements
for values
VDDA
See Voltage and current
operating requirements for
values
V
2
VREFL
ADC reference voltage low
See Voltage
and current
operating
requirements
for values
0
See Voltage and current
operating requirements for
values
mV
2
VADIN
Input voltage
VREFL
—
VREFH
V
—
—
5
kΩ
0.75
1.2
kΩ
Source impedendance
fADCK < 4 MHz
Channel Selection Switch Impedance
—
RAD
Sampling Switch Impedance
—
2
5
kΩ
CP1
Pin Capacitance
—
10
—
pF
CP2
Analog Bus Capacitance
—
—
4
pF
CS
Sampling capacitance
—
4
5
pF
2
40
No ADC hardware
Continuous conversions
enabled, subsequent conversion
time
46.4
928
ADC hardware averaging set to
32. 5 Continuous conversions
enabled, subsequent conversion
time
1.45
29
ADC conversion clock frequency
ADC conversion frequency
Normal usage
averaging.5
50
40
MHz
3, 4
1160
Ksps
6, 7
36.25
Ksps
6, 7
55
Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. Typical values are for reference only, and
are not tested in production.
For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance, reference
supply quality should be better than SAR ADC. See application note AN5032 for details.
Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual .
ADC conversion will become less reliable above maximum frequency.
When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS.
ADC electrical specifications
RSW1
fCONV
3.
4.
5.
S32K1xx/
S32K14xW
Max.
ADC reference voltage high
fADCK
2.
Conditions
Typ.1
VREFH
RS
1.
Description
Min.
Numbers based on the minimum sampling time of 275 ns.
For guidelines and examples of conversion rate calculation, see the Reference Manual section 'Calibration function'
ADC electrical specifications
56
6.
7.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
ADC electrical specifications
Figure 14. ADC input impedance equivalency diagram
6.4.1.2
12-bit ADC electrical characteristics
NOTE
• ADC performance specifications are documented using a
single ADC. For parallel/simultaneous operation of both
ADCs, either for sampling the same channel by both ADCs
or for sampling different channels by each ADC, some
amount of decrease in performance can be expected. Care
must be taken to stagger the two ADC conversions, in
particular the sample phase, to minimize the impact of
simultaneous conversions.
• On reduced pin packages where ADC reference pins are
shared with supply pins, ADC analog performance
characteristics may be impacted. The amount of variation
will be directly impacted by the external PCB layout and
hence care must be taken with PCB routing. See AN5426
for details
• All accuracy numbers assume the ADC is calibrated with
VREFH=VDDA=VDD, with the calibration frequency set to
less than or equal to half of the maximum specified ADC
clock frequency.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
57
ADC electrical specifications
Table 41. 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS) 1
Symbol
Description
Min.
Typ.2
Max.
Unit
VDDA
Supply voltage
2.7
—
3
V
IDDA_ADC
Supply current per ADC
—
0.6
—
mA
SMPLTS
Sample Time
275
—
Refer to the
Reference
Manual
ns
Notes
3
TUE4
Total unadjusted error
—
±4
±8
LSB5
6, 7, 8, 9
DNL
Differential non-linearity
—
±1.0
—
LSB5
6, 7, 8, 9
INL
Integral non-linearity
—
±2.0
—
LSB5
6, 7, 8, 9
1.
2.
3.
4.
5.
6.
This table is not applicable to S32K14xW.
Typical values assume VDDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF.
The ADC supply current depends on the ADC conversion rate.
Represents total static error, which includes offset and full scale error.
1 LSB = (VREFH - VREFL)/2N
The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings
for AVGS.
7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC
performance may be observed.
8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the
internal analog parameters, assume minor degradation.
9. All the parameters in the table are given assuming system clock as the clocking source for ADC.
Table 42. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS)
Symbol
VDDA
Description
Supply voltage
IDDA_ADC
Supply current per ADC
SMPLTS
Sample Time
Min.
Typ.1
Max.
Unit
S32K1xx
S32K14xW
S32K1xx/
S32K14xW
S32K1xx/
S32K14xW
3
3.13
—
5.5
V
—
1
—
mA
275
—
Refer to the
Reference
Manual
ns
Notes
2
TUE3
Total unadjusted error
—
±4
±8
LSB4
5, 6, 7, 8
DNL
Differential non-linearity
—
±0.7
—
LSB4
5, 6, 7, 8
INL
Integral non-linearity
—
±1.0
—
LSB4
5, 6, 7, 8
1.
2.
3.
4.
5.
Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated.
The ADC supply current depends on the ADC conversion rate.
Represents total static error, which includes offset and full scale error.
1 LSB = (VREFH - VREFL)/2N
The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device
use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings
for AVGS.
6. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC
performance may be observed.
7. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the
internal analog parameters, assume minor degradation.
8. All the parameters in the table are given assuming system clock as the clocking source for ADC.
S32K1xx Data Sheet, Rev. 13, 04/2020
58
NXP Semiconductors
ADC electrical specifications
NOTE
• Due to triple bonding in lower pin packages like 32-QFN,
48-LQFP, and 64-LQFP degradation might be seen in ADC
parameters.
• When using high speed interfaces such as the QuadSPI,
SAI0, SAI1 or ENET there may be some ADC degradation
on the adjacent analog input paths. See following table for
details.
Pin name
TGATE purpose
PTE8
CMP0_IN3
PTC3
ADC0_SE11/CMP0_IN4
PTC2
ADC0_SE10/CMP0_IN5
PTD7
CMP0_IN6
PTD6
CMP0_IN7
PTD28
ADC1_SE22
PTD27
ADC1_SE21
6.4.2 CMP with 8-bit DAC electrical specifications
Table 44. Comparator with 8-bit DAC electrical specifications for S32K1xx series
Symbol
IDDHS
Description
Min.
Supply current, High-speed
-40 - 125 ℃
IDDLS
Supply current, Low-speed
VAIN
Analog input voltage
VAIO
Analog input offset voltage, High-speed mode
—
230
300
—
6
11
6
13
0 - VDDA
VDDA
μA
0
-40 - 125 ℃
mV
-40
±4
40
—
35
200
35
300
ns
-40 - 125 ℃
mode2
Propagation delay, Low-speed
-40 - 105 ℃
-40 - 125 ℃
tDHSS
25
mode2
-40 - 105 ℃
tDLSB
±1
Analog input offset voltage, Low-speed mode
Propagation delay, High-speed
Propagation delay, High-speed
-40 - 105 ℃
V
mV
-25
-40 - 125 ℃
Unit
μA
-40 - 125 ℃
tDHSB
Max.
mode1
-40 - 105 ℃
VAIO
Typ.
mode1
µs
—
0.5
2
—
0.5
3
mode3
ns
—
70
400
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
59
ADC electrical specifications
Table 44. Comparator with 8-bit DAC electrical specifications for S32K1xx series
(continued)
Symbol
Description
-40 - 125 ℃
tDLSS
Propagation delay, Low-speed
500
—
1
5
—
1
5
—
1.5
3
Initialization delay, Low-speed mode4
μs
—
10
30
Analog comparator hysteresis, Hyst0
mV
-40 - 125 ℃
VHYST1
70
Unit
μs
-40 - 125 ℃
VHYST0
—
mode4
-40 - 125 ℃
tIDLS
Max.
µs
-40 - 125 ℃
Initialization delay, High-speed
Typ.
mode3
-40 - 105 ℃
tIDHS
Min.
—
0
—
Analog comparator hysteresis, Hyst1, High-speed
mode
mV
-40 - 125 ℃
—
19
66
—
15
40
Analog comparator hysteresis, Hyst1, Low-speed
mode
-40 - 125 ℃
VHYST2
Analog comparator hysteresis, Hyst2, High-speed
mode
mV
-40 - 125 ℃
—
34
133
—
23
80
Analog comparator hysteresis, Hyst2, Low-speed
mode
-40 - 125 ℃
VHYST3
Analog comparator hysteresis, Hyst3, High-speed
mode
mV
-40 - 125 ℃
—
46
200
—
32
120
—
6
9
Analog comparator hysteresis, Hyst3, Low-speed
mode
-40 - 125 ℃
IDAC8b
8-bit DAC current adder (enabled)
3.3V Reference Voltage
5V Reference Voltage
1.
2.
3.
4.
5.
6.
μA
—
10
16
μA
INL5
8-bit DAC integral non-linearity
–0.75
—
0.75
LSB6
DNL
8-bit DAC differential non-linearity
–0.5
—
0.5
LSB6
tDDAC
Initialization and switching settling time
—
—
30
μs
Difference at input > 200mV
Applied ± (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point.
Applied ± (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point.
Applied ± (100 mV + VHYST0/1/2/3).
Calculation method used: Linear Regression Least Square Method
1 LSB = Vreference/256
S32K1xx Data Sheet, Rev. 13, 04/2020
60
NXP Semiconductors
ADC electrical specifications
Table 45. Comparator with 8-bit DAC electrical specifications for S32K14xW series
Symbol
IDDHS
Description
Min.
—
Supply current, Low-speed
—
-40 - 150 ℃
VAIN
Analog input voltage
VAIO
Analog input offset voltage, High-speed mode
0
13
6
13
0 - VDDA
VDDA
-40 - 150 ℃
-50
±1
50
Analog input offset voltage, Low-speed mode
Propagation delay, High-speed
-40
±4
40
-50
±4
50
—
35
200
35
300
35
400
ns
mode2
Propagation delay, Low-speed
µs
-40 - 105 ℃
—
0.5
2
-40 - 125 ℃
—
0.5
3
—
0.5
3
-40 - 105 ℃
—
70
400
-40 - 125 ℃
—
70
500
—
70
600
Propagation delay, High-speed
mode3
-40 - 150 ℃
Propagation delay, Low-speed
ns
mode3
µs
-40 - 105 ℃
—
1
5
-40 - 125 ℃
—
1
5
—
1
5
—
1.5
3
—
1.5
3
-40 - 150 ℃
Initialization delay, High-speed
mode4
-40 - 125 ℃
-40 - 150 ℃
Initialization delay, Low-speed
V
mV
mode2
-40 - 150 ℃
VHYST0
6
25
-40 - 150 ℃
tIDLS
11
mV
-40 - 125 ℃
tIDHS
6
±1
-40 - 105 ℃
tDLSS
300
-25
-40 - 150 ℃
tDHSS
230
-40 - 125 ℃
-40 - 125 ℃
tDLSB
300
μA
-40 - 125 ℃
tDHSB
230
mode-1
-40 - 105 ℃
Unit
μA
-40 - 150 ℃
VAIO
Max.
Supply current, High-speed mode1
-40 - 125 ℃
IDDLS
Typ.
μs
mode4
μs
-40 - 125 ℃
—
10
30
-40 - 150 ℃
—
10
30
Analog comparator hysteresis, Hyst0
mV
-40 - 125 ℃
—
0
—
-40 - 150 ℃
—
0
—
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
61
ADC electrical specifications
Table 45. Comparator with 8-bit DAC electrical specifications for S32K14xW series
(continued)
Symbol
Description
Min.
VHYST1
Analog comparator hysteresis, Hyst1, High-speed
mode
Typ.
Max.
Unit
mV
-40 - 125 ℃
—
19
66
-40 - 150 ℃
—
19
90
-40 - 125 ℃
—
15
40
-40 - 150 ℃
—
15
40
Analog comparator hysteresis, Hyst1, Low-speed
mode
VHYST2
Analog comparator hysteresis, Hyst2, High-speed
mode
mV
-40 - 125 ℃
—
34
133
-40 - 150 ℃
—
34
186
-40 - 125 ℃
—
23
80
-40 - 150 ℃
—
23
80
Analog comparator hysteresis, Hyst2, Low-speed
mode
VHYST3
Analog comparator hysteresis, Hyst3, High-speed
mode
mV
-40 - 125 ℃
—
46
200
-40 - 150 ℃
—
46
280
-40 - 125 ℃
—
32
120
-40 - 150 ℃
—
32
120
3.3V Reference Voltage
—
6
9
μA
5V Reference Voltage
—
10
16
μA
Analog comparator hysteresis, Hyst3, Low-speed
mode
IDAC8b
INL5
8-bit DAC current adder (enabled)
LSB6
8-bit DAC integral non-linearity
-40 - 125 ℃
–0.75
—
-40 - 150 ℃
1.
2.
3.
4.
5.
6.
DNL
8-bit DAC differential non-linearity
tDDAC
Initialization and switching settling time
0.75
-2
—
2
–0.5
—
0.5
LSB-1
—
—
30
μs
Difference at input > 200mV
Applied ± (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point.
Applied ± (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point.
Applied ± (100 mV + VHYST0/1/2/3).
Calculation method used: Linear Regression Least Square Method
1 LSB = Vreference/256
NOTE
For comparator IN signals adjacent to VDD/VSS or XTAL/
EXTAL or switching pins cross coupling may happen and
S32K1xx Data Sheet, Rev. 13, 04/2020
62
NXP Semiconductors
ADC electrical specifications
hence hysteresis settings can be used to obtain the desired
comparator performance. Additionally, an external capacitor
(1nF) should be used to filter noise on input signal. Also, source
drive should not be weak (Signal with < 50 K pull up/down is
recommended).
Figure 15. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 0)
Figure 16. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 1)
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
63
ADC electrical specifications
Figure 17. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 0)
Figure 18. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1)
S32K1xx Data Sheet, Rev. 13, 04/2020
64
NXP Semiconductors
Communication modules
6.5 Communication modules
6.5.1 LPUART electrical specifications
Refer to General AC specifications for LPUART specifications.
6.5.1.1
Supported baud rate
Baud rate = Baud clock / ((OSR+1) * SBR).
For details, see section: 'Baud rate generation' of the Reference Manual.
6.5.2 LPSPI electrical specifications
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable. The
following tables provide timing characteristics for classic LPSPI timing modes.
• All timing is shown with respect to 20% VDD and 80% VDD thresholds.
• All measurements are with maximum output load of 50 pF, input transition of 1 ns
and pad configured with fastest slew setting (DSE = 1).
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
65
Symbo
l
Num
Descripti
on
Run Mode2
Conditions
S32K1xx Data Sheet, Rev. 13, 04/2020
fop
3
tLead8 Enable
lead time
(PCS to
SPSCK
delay)
3.3 V IO
5.0 V IO
5.0 V IO
3.3 V IO
Min
Max
Min
Max
3.3 V IO
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
-
40
-
40
-
56
-
56
-
4
-
4
-
1
-
1
-
40
-
40
-
56
-
56
-
4
-
4
-
1
-
1
Master
Loopback5
-
40
-
48
-
48
-
48
-
4
-
4
-
1
-
1
Master
Loopback(sl
ow)6
-
48
-
48
-
48
-
48
-
4
-
4
-
1
-
1
-
10
-
10
-
14
-
14 7
-
2
-
2
-
0.5
-
0.5
7
-
2
-
2
-
0.5
-
0.5
Frequency Slave
of
Master
operation
Master
Loopback5
tSPSCK SPSCK
period
5.0 V IO
VLPR Mode (S32K14xW)
Max
-
10
-
10
-
14
-
-
20
-
12
-
24
-
12
-
2
-
2
-
0.5
-
0.5
-
12
-
12
-
12
-
12
-
2
-
2
-
0.5
-
0.5
Slave
100
-
100
-
72
-
72
-
500
-
500
-
-
2000
-
2000
Master
100
-
100
-
72
-
72
-
500
-
500
-
-
2000
-
2000
Master
Loopback5
50
-
83
-
42
-
83
-
500
-
500
-
-
2000
-
2000
Master
Loopback(sl
ow)6
83
-
83
-
83
-
83
-
500
-
500
-
-
2000
-
2000
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Master
Loopback(sl
ow)6
2
3.3 V IO
VLPR Mode (S32K1xx)
Min
fperiph, Peripheral Slave
3, 4
Frequency Master
1
5.0 V IO
HSRUN Mode2
Slave
14
NXP Semiconductors
Table continues on the next page...
Un
it
MH
z
MH
z
ns
ns
Communication modules
66
Table 46. LPSPI electrical specifications1
Min
Min
Max
-
-
Max
-
-
-
-
-
-
-
-
38
-
3
26
-
-
-
-
18
-
18
-
55
-
55
-
-
3711
-
72
-
78
-
145
-
145
-
32
tSPSCK/2-5
tSPSCK/2-5
Table continues on the next page...
tSPSCK/2+5
5
tSPSCK/2+5
-
12
ns
-
SPSCK/2+12
-
5
-
SPSCK/2-12
29
-
-
-
SPSCK/2+12
3
-
Max
SPSCK/2-12
Data setup Slave
time(input Master
s)
tSPSCK/2+3
Master
Loopback5
tSPSCK/2-3
Master
Max
(PCSSCK+1)*tperiph-115
(PCSSCK+1)*tperiph-50
(PCSSCK+1)*tperiph-50
(PCSSCK+1)*tperiph-25
-
Min
Un
it
(PCSSCK+1)*tperiph-115
Min
-
-
-
3.3 V IO
ns
ns
67
Communication modules
tSU
-
5.0 V IO
3.3 V IO
Slave
Master
Loopback(sl
ow)6
6
(PCSSCK+1)*tperiph-25
(PCSSCK+1)*tperiph-25
-
-
tSPSCK/2+3
tWSPSC Clock(SPS
10
CK) high
K
or low time
(SPSCK
duty cycle)
-
Max
-
tSPSCK/2-3
5
-
Min
5.0 V IO
(PCSSCK+1)*tperiph-115
Master
Loopback(sl
ow)6
-
Max
3.3 V IO
VLPR Mode (S32K14xW)
(PCSSCK+1)*tperiph-115
Enable lag Slave
time (After Master
SPSCK
Master
delay)
Loopback5
Min
-
tSPSCK/2+3
tLag9
tSPSCK/2-3
S32K1xx Data Sheet, Rev. 13, 04/2020
4
Max
(SCKPCS+1)*tperiph- 25
Master
Loopback(sl
ow)6
(SCKPCS+1)*tperiph- 25
Master
Loopback5
Min
(PCSSCK+1)*tperiph-25
Master
Max
5.0 V IO
(SCKPCS+1)*tperiph- 25
Min
3.3 V IO
VLPR Mode (S32K1xx)
(SCKPCS+1)*tperiph- 50
5.0 V IO
(SCKPCS+1)*tperiph- 25
Conditions
HSRUN Mode2
(SCKPCS+1)*tperiph- 50
Run Mode2
tSPSCK/2-3
Descripti
on
tSPSCK/2+3
Symbo
l
Num
NXP Semiconductors
Table 46. LPSPI electrical specifications1 (continued)
Symbo
l
Num
7
tHI
Descripti
on
Run Mode2
Conditions
5.0 V IO
HSRUN Mode2
3.3 V IO
5.0 V IO
3.3 V IO
VLPR Mode (S32K1xx)
VLPR Mode (S32K14xW)
5.0 V IO
5.0 V IO
3.3 V IO
Min
Max
Min
Max
3.3 V IO
S32K1xx Data Sheet, Rev. 13, 04/2020
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Master
Loopback5
7
-
8
-
5
-
7
-
20
-
20
-
60
-
60
-
Master
Loopback(sl
ow)6
8
-
10
-
7
-
9
-
20
-
20
-
61
-
61
-
3
-
3
-
3
-
3
-
14
-
14
-
27
-
27
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
3
-
3
-
2
-
3
-
11
-
11
-
26
-
26
-
Master
Loopback(sl
ow)6
3
-
3
-
3
-
3
-
12
-
12
-
20
-
20
-
Data hold Slave
time(input Master
s)
Master
Loopback5
Un
it
ns
8
ta
Slave
access
time
Slave
-
50
-
50
-
50
-
50
-
100
-
100
-
180
-
180
ns
9
tdis
Slave
MISO
(SOUT)
disable
time
Slave
-
50
-
50
-
50
-
50
-
100
-
100
-
180
-
180
ns
10
tv
Data valid Slave
(after
SPSCK
Master
edge)
-
30
-
39
-
26
-
36 11
-
92
-
96
-
190
-
190
ns
NXP Semiconductors
11
tHO
31 12
-
12
-
16
-
11
-
15
-
47
-
48
-
113
-
113
Master
Loopback5
-
12
-
16
-
11
-
15
-
47
-
48
-
112
-
112
Master
Loopback(sl
ow)6
-
8
-
10
-
7
-
9
-
44
-
44
-
99
-
99
4
-
4
-
4
-
4
-
4
-
4
-
4
-
4
-
-15
-
-22
-
-15
-
-23
-
-22
-
-29
-
-30
-
-30
-
Data hold Slave
time(outpu Master
ts)
Table continues on the next page...
ns
Communication modules
68
Table 46. LPSPI electrical specifications1 (continued)
12
S32K1xx Data Sheet, Rev. 13, 04/2020
13
Symbo
l
Num
NXP Semiconductors
Table 46. LPSPI electrical specifications1 (continued)
tRI/FI
Descripti
on
Rise/Fall
time input
tRO/FO Rise/Fall
time
output
Run Mode2
Conditions
5.0 V IO
HSRUN Mode2
3.3 V IO
5.0 V IO
3.3 V IO
VLPR Mode (S32K1xx)
VLPR Mode (S32K14xW)
5.0 V IO
5.0 V IO
3.3 V IO
Min
Max
Min
Max
3.3 V IO
Un
it
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Master
Loopback5
-10
-
-14
-
-10
-
-14
-
-14
-
-19
-
-19
-
-19
-
Master
Loopback(sl
ow)6
-15
-
-22
-
-15
-
-22
-
-21
-
-27
-
-30
-
-30
-
Slave
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
ns
Master
-
-
-
-
-
-
-
-
Master
Loopback5
-
-
-
-
-
-
-
-
Master
Loopback(sl
ow)6
-
-
-
-
-
-
-
-
Slave
-
25
ns
Master
-
-
-
-
-
-
-
-
Master
Loopback 5
-
-
-
-
-
-
-
-
Master
Loopback(sl
ow) 6
-
-
-
-
-
-
-
-
25
-
25
-
25
-
25
-
25
-
25
-
25
-
1.
2.
3.
4.
5.
69
Communication modules
Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode.
While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz.
fperiph = LPSPI peripheral clock
tperiph = 1/fperiph
Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.
Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0.
6. Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1.
Clock pad used is PTB2. Applicable only for LPSPI0.
7. This is the maximum operating frequency (fop) for LPSPI0 with GPIO-HD PAD type only. Otherwise, the maximum operating frequency (fop) is 12 Mhz.
8. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255.
9. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255.
10. While selecting odd dividers, ensure Duty Cycle is meeting this parameter.
11. Maximum operating frequency (fop ) is 12 MHz irrespective of PAD type and LPSPI instance.
12. Applicable for LPSPI0 only with GPIO-HD PAD type, with maximum operating frequency (fop) as 14 MHz.
Communication modules
SS1
(OUTPUT)
3
2
SPSCK
(CPOL=0)
(OUTPUT)
12
13
12
13
4
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
LSB IN
10
MOSI
(OUTPUT)
MSB OUT2
11
BIT 6 . . . 1
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. LPSPI master mode timing (CPHA = 0)
SS1
(OUTPUT)
2
3
SPSCK
(CPOL=0)
(OUTPUT)
5
SPSCK
(CPOL=1)
(OUTPUT)
6
MISO
(INPUT)
5
13
12
13
4
7
MSB IN2
BIT 6 . . . 1
LSB IN
11
10
MOSI
(OUTPUT)
12
PORT DATA MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 20. LPSPI master mode timing (CPHA = 1)
S32K1xx Data Sheet, Rev. 13, 04/2020
70
NXP Semiconductors
Communication modules
SS
(INPUT)
2
12
13
12
13
4
SPSCK
(CPOL=0)
(INPUT)
5
3
SPSCK
(CPOL=1)
(INPUT)
5
9
8
MISO
(OUTPUT)
CFGR1[OUTCFG]=1
MISO
(OUTPUT)
CFGR1[OUTCFG]=0
See
note1
See
note1
10
11
SLAVE MSB
BIT 6 . . . 1
SLAVE LSB OUT
See
note 1
SLAVE MSB
BIT 6 . . . 1
SLAVE LSB OUT
See
note 1
6
MOSI
(INPUT)
11
7
MSB IN
BIT 6 . . . 1
LSB IN
Notes:
1.The bus is driven but may not be equal to the valid serial data being sent.
Figure 21. LPSPI slave mode timing (CPHA = 0)
Figure 22. LPSPI slave mode timing (CPHA = 1)
6.5.3 LPI2C electrical specifications
See General AC specifications for LPI2C specifications.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
71
Communication modules
For supported baud rate see section 'Chip-specific LPI2C information' of the Reference
Manual.
6.5.4 FlexCAN electical specifications
For supported baud rate, see section 'Protocol timing' of the Reference Manual.
6.5.5 SAI electrical specifications
The following table describes the SAI electrical characteristics.
• Measurements are with maximum output load of 50 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
Table 47. Master mode timing specifications
Symbol
Description
Min.
Max.
Unit
2.97
3.6
V
40
—
ns
45%
55%
MCLK period
80
—
ns
45%
55%
BCLK period
—
Operating voltage
S1
SAI_MCLK cycle time
S2
SAI_MCLK pulse width high/low
S3
SAI_BCLK cycle time
S4
SAI_BCLK pulse width high/low
S5
SAI_RXD input setup before
SAI_BCLK
28
—
ns
S6
SAI_RXD input hold after
SAI_BCLK
0
—
ns
S7
SAI_BCLK to SAI_TXD output
valid
—
8
ns
S8
SAI_BCLK to SAI_TXD output
invalid
-2
—
ns
S9
SAI_FS input setup before
SAI_BCLK
28
—
ns
S10
SAI_FS input hold after
SAI_BCLK
0
—
ns
S11
SAI_BCLK to SAI_FS output
valid
—
8
ns
S12
SAI_BCLK to SAI_FS output
invalid
-2
—
ns
S32K1xx Data Sheet, Rev. 13, 04/2020
72
NXP Semiconductors
Communication modules
S1
S2
S2
SAI_MCLK (output)
S3
SAI_BCLK (output)
S4
S4
S12
S11
SAI_FS (output)
S10
S9
SAI_FS (input)
S7
S8
S7
S8
SAI_TXD
S5
S6
SAI_RXD
Figure 23. SAI Timing — Master modes
Table 48. Slave mode timing specifications
Symbol
—
Description
Operating voltage
Min.
Max.
Unit
2.97
3.6
V
80
—
ns
45%
55%
BCLK period
S13
SAI_BCLK cycle time (input)
S141
SAI_BCLK pulse width high/low
(input)
S15
SAI_RXD input setup before
SAI_BCLK
8
—
ns
S16
SAI_RXD input hold after
SAI_BCLK
2
—
ns
S17
SAI_BCLK to SAI_TXD output
valid
—
28
ns
S18
SAI_BCLK to SAI_TXD output
invalid
0
—
ns
S19
SAI_FS input setup before
SAI_BCLK
8
—
ns
S20
SAI_FS input hold after SAI_BCLK
2
—
ns
S21
SAI_BCLK to SAI_FS output valid
—
28
ns
S22
SAI_BCLK to SAI_FS output
invalid
0
—
ns
1. The slave mode parameters (S15 - S22) assume 50% duty cycle on SAI_BCLK input. Any change in SAI_BCLK duty cycle
input must be taken care during the board design or by the master timing.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
73
Communication modules
S13
S14
SAI_BCLK (input)
S14
S21
S22
SAI_FS (output)
S19
S20
SAI_FS (input)
S17
S18
S17
S18
SAI_TXD
S15
S16
SAI_RXD
Figure 24. SAI Timing — Slave modes
6.5.6 Ethernet AC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
The following table describes the MII electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
Table 49. MII signal switching specifications
Symbol
—
Description
RXCLK frequency
Min.
Max.
Unit
—
25
MHz
MII1
RXCLK pulse width high
35%
65%
RXCLK period
MII2
RXCLK pulse width low
35%
65%
RXCLK period
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
5
—
ns
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
TXCLK frequency
—
25
MHz
—
MII5
TXCLK pulse width high
35%
65%
TXCLK period
MII6
TXCLK pulse width low
35%
65%
TXCLK period
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
2
—
ns
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
S32K1xx Data Sheet, Rev. 13, 04/2020
74
NXP Semiconductors
Communication modules
MII2
MII1
MII3
MII4
RXCLK (input)
RXD[n:0]
Valid data
RXDV
Valid data
RXER
Valid data
Figure 25. MII receive diagram
MII6
MII5
TXCLK (input)
MII8
MII7
TXD[n:0]
Valid data
TXEN
Valid data
TXER
Valid data
Figure 26. MII transmit signal diagram
The following table describes the RMII electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
Table 50. RMII signal switching specifications
Symbol
Min.
Max.
Unit
—
50
MHz
RMII1, RMII5 RMII_CLK pulse width high
35%
65%
RMII_CLK
period
RMII2, RMII6 RMII_CLK pulse width low
35%
65%
RMII_CLK
period
—
Description
RMII input clock RMII_CLK Frequency
RMII3
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
4
—
ns
RMII4
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
2
—
ns
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
75
Communication modules
Table 50. RMII signal switching specifications
(continued)
Symbol
Description
Min.
Max.
Unit
RMII7
RMII_CLK to TXD[1:0], TXEN invalid
2
—
ns
RMII8
RMII_CLK to TXD[1:0], TXEN valid
—
15
ns
RMII2
RMII1
RMII3
RMII4
RMII_CLK(input)
RXD[n:0]
Valid data
CRS_DV
Valid data
RXER
Valid data
Figure 27. RMII receive diagram
RMII6
RMII5
RMII_CLK (input)
RMII8
RMII7
TXD[n:0]
Valid data
TXEN
Valid data
Figure 28. RMII transmit diagram
The following table describes the MDIO electrical characteristics.
• Measurements are with maximum output load of 25 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• I/O operating voltage ranges from 2.97 V to 3.6 V
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
• MDIO pin must have external Pull-up.
Table 51. MDIO timing specifications
Symbol
—
Description
MDC Clock Frequency
Min.
Max.
Unit
—
2.5
MHz
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
76
NXP Semiconductors
Debug modules
Table 51. MDIO timing specifications (continued)
Symbol
Description
Min.
Max.
Unit
MDC1
MDC pulse width high
40%
60%
MDC period
MDC2
MDC pulse width low
40%
60%
MDC period
MDC3
MDIO (input) to MDC rising edge setup
25
—
ns
MDC4
MDIO (input) to MDC rising edge hold
0
—
ns
MDC5
MDC falling edge to MDIO output valid
(maximum propagation delay)
—
25
ns
MDC6
MDC falling edge to MDIO output invalid
(minimum propagation delay)
-10
—
ns
MDC1
MDC2
MDC (output)
MDC6
MDIO (output)
MDC5
MDIO (input)
MDC3
MDC4
Figure 29. MII/RMII serial management channel timing diagram
6.5.7 Clockout frequency
Maximum supported clock out frequency for this device is 20 MHz
6.6 Debug modules
6.6.1 SWD electrical specofications
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
77
Symbo
l
Description
Run Mode
5.0 V IO
HSRUN Mode
3.3 V IO
5.0 V IO
VLPR Mode (S32K1xx)
3.3 V IO
5.0 V IO
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
3.3 V IO
VLPR Mode
(S32K14xW)
5.0 V IO
Unit
3.3 V IO
Min. Max. Min. Max. Min. Max.
-
10
-
10
-
1
-
1
MHz
S2
SWD_CLK cycle period
1/S1
-
1/S1
-
1/S1
-
1/S1
-
1/S1
-
1/S1
-
1/S1
-
1/S1
-
ns
S3
SWD_CLK clock pulse
width
S4
SWD_CLK rise and fall
times
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
ns
S9
SWD_DIO input data setup
time to SWD_CLK rise
4
-
4
-
4
-
4
-
16
-
16
-
30
-
30
-
ns
S10
SWD_DIO input data hold
time after SWD_CLK rise
3
-
3
-
3
-
3
-
10
-
10
-
19
-
19
-
ns
S11
SWD_CLK high to
SWD_DIO data valid
-
28
-
38
-
28
-
38
-
70
-
77
-
180
-
180
ns
S12
SWD_CLK high to
SWD_DIO high-Z
-
28
-
38
-
28
-
38
-
70
-
77
-
180
-
180
ns
S13
SWD_CLK high to
SWD_DIO data invalid
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
ns
S2/2+5
S2/2 - 5
S2/2 - 5
S2/2 - 5
S2/2 - 5
S2/2 - 5
S2/2-5
25
S2/2+5
-
S2/2-5
25
S2/2 + 5
-
S2/2 + 5
25
S2/2 + 5
-
S2/2 + 5
25
S2/2 + 5
-
S2/2 + 5
SWD_CLK frequency of
operation
S2/2 - 5
S32K1xx Data Sheet, Rev. 13, 04/2020
S1
Debug modules
78
Table 52. SWD electrical specifications
NXP Semiconductors
Debug modules
S2
S3
S3
SWD_CLK (input)
S4
S4
Figure 30. Serial wire clock input timing
SWD_CLK
S9
SWD_DIO
S10
Input data valid
S11
S13
SWD_DIO
Output data valid
S12
SWD_DIO
Figure 31. Serial wire data timing
6.6.2 Trace electrical specifications
The following table describes the ETM Trace electrical characteristics.
• Measurements are with maximum output load of 50 pF, input transition of 1 ns and
pad configured with fastest slew settings (DSE = 1'b1).
• While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the
interface should be OFF.
NOTE
ETM trace is supported only on S32K148.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
79
Debug modules
Table 53. ETM Trace specifications
Symbol
—
Fsys
Trace on fast pads
fTRACE
RUN Mode
HSRUN Mode
VLPR
Mode
Unit
System frequency
80
48
40
112
80
4
MHz
Max Trace frequency
80
48
40
74.667
80
4
MHz
tDVO
Data Output Valid
4
4
4
4
4
20
ns
tDIV
Data Output Invalid
-2
-2
-2
-2
-2
-10
ns
24
20
22.4
22.86
4
MHz
fTRACE
Trace on slow pads
Description
Max Trace frequency
22.86
tDVO
Data Output Valid
8
8
8
8
8
20
ns
tDIV
Data Output Invalid
-4
-4
-4
-4
-4
-10
ns
Figure 32. TRACE CLKOUT specifications
6.6.3 JTAG electrical specifications
S32K1xx Data Sheet, Rev. 13, 04/2020
80
NXP Semiconductors
Symb
ol
Description
Run Mode
5.0 V IO
Min.
HSRUN Mode
3.3 V IO
Min.
Max.
5.0 V IO
Min.
Max.
VLPR Mode (S32K1xx)
3.3 V IO
Min.
Max.
5.0 V IO
Min.
Max.
VLPR Mode (S32K14xW)
3.3 V IO
Min.
Max.
5.0 V IO
Min
Max
Min
Max
MHz
Boundary Scan
-
20
-
20
-
20
-
20
-
10
-
10
-
1
-
1
JTAG
-
20
-
20
-
20
-
20
-
10
-
10
-
1
-
1
-
1/JI
-
1/JI
-
1/JI
-
1/JI
-
1/JI
-
1/J1
-
1/J1
-
J2/2 + 5
J2/2 - 5
J2/2 + 5
J2/2 - 5
J2/2 + 5
J2/2 - 5
J2/2 + 5
J2/2 - 5
J2/2 + 5
S32K1xx Data Sheet, Rev. 13, 04/2020
JTAG
J2/2 - 5
Boundary Scan
ns
ns
J2/2 + 5
TCLK clock pulse width
J2/2 - 5
J3
1/JI
J2/2 + 5
TCLK cycle period
J2/2 - 5
J2
Unit
5.0 V IO
TCLK frequency of operation
J2/2 - 5
JI
Max.
J2/2 + 5
NXP Semiconductors
Table 54. JTAG electrical specifications
TCLK rise and fall
times
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
ns
J5
Boundary scan input
data setup time to
TCLK rise
5
-
5
-
5
-
5
-
15
-
15
-
23
-
23
-
ns
J6
Boundary scan input
data hold time after
TCLK rise
5
-
5
-
5
-
5
-
8
-
8
-
20
-
20
-
ns
J7
TCLK low to boundary
scan output data valid
-
28
-
32
-
28
-
32
-
80
-
80
-
184
-
184
ns
J8
TCLK low to boundary
scan output data invalid
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
J9
TCLK low to boundary
scan output high-Z
-
28
-
32
-
28
-
32
-
80
-
80
-
184
-
184
ns
J10
TMS, TDI input data
setup time to TCLK rise
3
-
3
-
3
-
3
-
15
-
15
-
23
-
23
-
ns
J11
TMS, TDI input data
hold time after TCLK
rise
2
-
2
-
2
-
2
-
8
-
8
-
20
-
20
-
ns
J12
TCLK low to TDO data
valid
-
28
-
32
-
28
-
32
-
80
-
80
-
184
-
184
ns
J13
TCLK low to TDO data
invalid
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
ns
81
Table continues on the next page...
Debug modules
J4
Symb
ol
J14
Description
Run Mode
5.0 V IO
TCLK low to TDO highZ
HSRUN Mode
3.3 V IO
5.0 V IO
VLPR Mode (S32K1xx)
3.3 V IO
5.0 V IO
3.3 V IO
VLPR Mode (S32K14xW)
5.0 V IO
Unit
5.0 V IO
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min
Max
Min
Max
-
28
-
32
-
28
-
32
-
80
-
80
-
184
-
184
ns
Debug modules
82
Table 54. JTAG electrical specifications (continued)
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
Debug modules
J2
J3
J3
TCLK (input)
J4
J4
Figure 33. Test clock input timing
TCLK
J5
Data inputs
J6
Input data valid
J7
J8
Data outputs
Output data valid
J9
Data outputs
Figure 34. Boundary scan (JTAG) timing
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
83
Thermal attributes
TCLK
J10
TDI/TMS
J11
Input data valid
J12
J13
TDO
Output data valid
J14
TDO
Figure 35. Test Access Port timing
7 Thermal attributes
7.1 Description
The tables in the following sections describe the thermal characteristics of the device.
NOTE
Junction temperature is a function of die size, on-chip power
dissipation, package thermal resistance, mounting side (board)
temperature, ambient temperature, air flow, power dissipation
or other components on the board, and board thermal resistance.
7.2 Thermal characteristics
S32K1xx Data Sheet, Rev. 13, 04/2020
84
NXP Semiconductors
NXP Semiconductors
Table 55. Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package
Rating
Conditions
Symbol
Package
Values (in °C/W)
S32K116 S32K118 S32K142
Thermal resistance, Junction to Single layer
Ambient (Natural Convection)1, 2 board (1s)
S32K1xx Data Sheet, Rev. 13, 04/2020
Thermal resistance, Junction to
Ambient (Natural Convection)1
Thermal resistance, Junction to
Ambient (Natural Convection)1, 2
Thermal resistance, Junction to
Ambient (@200 ft/min)1, 3
Four layer
board
(2s2p)
Single layer
board (1s)
Two layer
board
(1s1p)
RθJA
RθJA
RθJMA
RθJMA
S32K144
S32K144
W
S32K146 S32K148
32
93
NA
NA
NA
NA
NA
NA
NA
48
79
71
70
69
69
69
NA
NA
64
NA
62
61
60
61
60
59
NA
100
NA
NA
53
NA
52
NA
51
46
144
NA
NA
NA
NA
NA
NA
51
44
176
NA
NA
NA
NA
NA
NA
NA
42
32
50
NA
NA
NA
NA
NA
NA
NA
48
58
50
49
48
48
48
NA
NA
64
NA
46
45
45
45
45
44
NA
100
NA
NA
42
NA
42
NA
40
36
144
NA
NA
NA
NA
NA
NA
44
37
176
NA
NA
NA
NA
NA
NA
NA
36
32
32
NA
NA
NA
NA
NA
NA
NA
48
55
47
46
45
45
45
NA
NA
64
NA
44
43
42
43
42
41
NA
100
NA
NA
40
NA
40
NA
39
34
144
NA
NA
NA
NA
NA
NA
42
36
176
NA
NA
NA
NA
NA
NA
NA
35
32
77
NA
NA
NA
NA
NA
NA
NA
48
66
58
57
56
57
56
NA
NA
64
NA
50
49
49
49
49
48
NA
100
NA
NA
43
NA
42
NA
41
37
144
NA
NA
NA
NA
NA
NA
42
36
176
NA
NA
NA
NA
NA
NA
NA
34
32
43
NA
NA
NA
NA
NA
NA
NA
48
51
43
42
41
41
41
NA
NA
64
NA
39
38
38
38
38
37
NA
85
Table continues on the next page...
Thermal attributes
Thermal resistance, Junction to
Ambient (@200 ft/min)1
Two layer
board
(1s1p)
RθJA
S32K142
W
Rating
Conditions
Symbol
Package
Values (in °C/W)
S32K116 S32K118 S32K142
Thermal resistance, Junction to
Ambient (@200 ft/min)1, 3
S32K1xx Data Sheet, Rev. 13, 04/2020
Thermal resistance, Junction to
Board4
Thermal resistance, Junction to
Case 5
NXP Semiconductors
Thermal resistance, Junction to
Case (Bottom) 6
Four layer
board
(2s2p)
—
—
—
RθJMA
RθJB
RθJC
RθJCBottom
S32K142
W
S32K144
S32K144
W
S32K146 S32K148
100
NA
NA
35
NA
35
NA
34
30
144
NA
NA
NA
NA
NA
NA
37
31
176
NA
NA
NA
NA
NA
NA
NA
30
32
26
NA
NA
NA
NA
NA
NA
NA
48
48
41
40
39
39
39
NA
NA
64
NA
37
36
36
36
36
35
NA
100
NA
NA
34
NA
34
NA
33
28
144
NA
NA
NA
NA
NA
NA
36
30
176
NA
NA
NA
NA
NA
NA
NA
29
32
11
NA
NA
NA
NA
NA
NA
NA
48
33
24
23
22
23
22
NA
NA
64
NA
26
25
24
25
24
23
NA
100
NA
NA
25
NA
25
NA
24
19
144
NA
NA
NA
NA
NA
NA
30
24
176
NA
NA
NA
NA
NA
NA
NA
24
32
NA
NA
NA
NA
NA
NA
NA
NA
48
23
19
17
16
17
16
NA
NA
64
NA
14
13
12
12
12
11
NA
100
NA
NA
13
NA
12
NA
11
9
144
NA
NA
NA
NA
NA
NA
12
9
176
NA
NA
NA
NA
NA
NA
NA
9
32
1
48
64
100
144
Table continues on the next page...
NA
NA
Thermal attributes
86
Table 55. Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package
(continued)
NXP Semiconductors
Table 55. Thermal characteristics for 32-pin QFN and 48/64/100/144/176-pin LQFP package
(continued)
Rating
Conditions
Symbol
Package
Values (in °C/W)
S32K116 S32K118 S32K142
S32K142
W
S32K144
S32K144
W
S32K146 S32K148
176
Thermal resistance, Junction to
Package Top7
S32K1xx Data Sheet, Rev. 13, 04/2020
1.
2.
3.
4.
5.
6.
7.
Natural
Convection
ψJT
32
1
NA
NA
NA
NA
NA
NA
NA
48
4
2
2
2
2
2
NA
NA
64
NA
2
2
2
2
2
2
NA
100
NA
NA
2
NA
2
NA
2
1
144
NA
NA
NA
NA
NA
NA
2
1
176
NA
NA
NA
NA
NA
NA
NA
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air
flow, power dissipation of other components on the board, and board thermal resistance.
Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the
package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek
letters are not available, the thermal characterization parameter is written as Psi-JT.
Thermal attributes
87
Rating
Conditions
Symbol
Values
Unit
S32K146
S32K144
S32K148
Thermal resistance, Junction to Ambient (Natural
Convection) 1, 2
Single layer board (1s)
RθJA
57.2
61.0
52.5
°C/W
Thermal resistance, Junction to Ambient (Natural
Convection) 1, 2, 3
Four layer board
(2s2p)
RθJA
32.1
35.6
27.5
°C/W
RθJMA
44.1
46.6
39.0
°C/W
RθJMA
27.2
30.9
22.8
°C/W
Thermal resistance, Junction to Ambient (@200 ft/min) 1, 2, 3 Single layer board (1s)
Thermal resistance, Junction to Ambient (@200
ft/min)1, 3
Two layer board
(2s2p)
S32K1xx Data Sheet, Rev. 13, 04/2020
Thermal resistance, Junction to Board4
—
RθJB
15.3
18.9
11.2
°C/W
5
—
RθJC
10.2
14.2
7.5
°C/W
Thermal resistance, Junction to Package Top outside
center6
—
ψJT
0.2
0.4
0.2
°C/W
Thermal resistance, Junction to Package Bottom outside
center7
—
ψJB
12.2
15.9
18.3
°C/W
Thermal resistance, Junction to Case
1.
2.
3.
4.
5.
6.
7.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air
flow, power dissipation of other components on the board, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the
package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek
letters are not available, the thermal characterization parameter is written as Psi-JT.
Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12.
When Greek letters are not available, the thermal characterization parameter is written as Psi-JB.
Thermal attributes
88
Table 56. Thermal characteristics for the 100 MAPBGA package
NXP Semiconductors
Thermal attributes
7.3 General notes for specifications at maximum junction
temperature
An estimation of the chip junction temperature, TJ, can be obtained from this equation:
where:
• TA = ambient temperature for the package (°C)
• RθJA = junction to ambient thermal resistance (°C/W)
• PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which value is closer to the application depends on the power dissipated
by other components on the board. The value obtained on a single layer board is
appropriate for the tightly packed printed circuit board. The value obtained on the board
with the internal planes is usually appropriate if the board has low power dissipation and
the components are well separated.
When a heat sink is used, the thermal resistance is expressed in the following equation as
the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:
where:
• RθJA = junction to ambient thermal resistance (°C/W)
• RθJC = junction to case thermal resistance (°C/W)
• RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RθCA. For instance, the
user can change the size of the heat sink, the air flow around the device, the interface
material, the mounting arrangement on printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device.
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
89
Dimensions
To determine the junction temperature of the device in the application when heat sinks
are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using this equation:
where:
• TT = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a
40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
8 Dimensions
8.1 Obtaining package dimensions
Package dimensions are provided in the package drawings.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for
the drawing’s document number:
Package option
Document Number
32-pin QFN
SOT617-3 1
48-pin LQFP
98ASH00962A
64-pin LQFP
98ASS23234W
100-pin LQFP
98ASS23308W
100-pin MAPBGA
98ASA00802D
144-pin LQFP
98ASS23177W
176-pin LQFP
98ASS23479W
1. 5x5 mm package
S32K1xx Data Sheet, Rev. 13, 04/2020
90
NXP Semiconductors
Pinouts
9 Pinouts
9.1 Package pinouts and signal descriptions
For package pinouts and signal descriptions, refer to the Reference Manual.
10 Revision History
The following table provides a revision history for this document.
Table 57. Revision History
Rev. No.
Date
1
12 Aug 2016
2
03 March 2017
Substantial Changes
Initial release
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated descpition of QSPI and Clock interfaces in Key Features section
Updated figure: High-level architecture diagram for the S32K1xx family
Updated figure: S32K1xx product series comparison
Added note in section Selecting orderable part number
Updated figure: Ordering information
In table: Absolute maximum ratings :
• Added footnote to IINJPAD_DC
• Updated min and max value of IINJPAD_DC
• Updated description, max and min values for IINJSUM
• Updated VIN_TRANSIENT
In table: Voltage and current operating requirements :
• Renamed VSUP_OFF
• Updated max value of VDD_OFF
• Removed VINA and VIN
• Added VREFH and VREFL
• Updated footnote "Typical conditions assumes VDD = VDDA = VREFH = 5
V ...
• Removed INJSUM_AF
Updated footnotes in table Table 7
Updated section Power mode transition operating behaviors
In table: Power consumption
• Added footnote "With PMC_REGSC[CLKBIASDIS] ... "
• Updated conditions for VLPR
• Removed Idd/MHz for S32K144
• Updated numbers for S32K142 and S32K148
• Removed use case footnotes
In section Modes configuration :
• Replaced table "Modes configuration" with spreadsheet attachment:
'S32K1xx_Power_Modes _Master_configuration_sheet'
In table: DC electrical specifications at 3.3 V Range :
• Added footnotes to Vih Input Buffer High Voltage and Vih Input Buffer
Low Voltage
• Added footnote to High drive port pins
In table: DC electrical specifications at 5.0 V Range :
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
91
Revision History
Table 57. Revision History
Rev. No.
Date
Substantial Changes
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• Added footnotes Vih Input Buffer High Voltage and Vih Input Buffer Low
Voltage
Updated table: AC electrical specifications at 3.3 V range
Updated table: AC electrical specifications at 5 V range
In table: Standard input pin capacitance
• Added footnote to Normal run mode (S32K14x series)
Removed note from 1M ohms Feedback Resistor in figure Oscillator
connections scheme
In table: External System Oscillator electrical specifications
• Updated typical of IDDOSC Supply current — low-gain mode (low-power
mode) (HGO=0) 1 for 4 and 8 MHz
• Removed rows for Ilk_ext EXTAL/XTAL impedence High-frequency, lowgain mode (low-power mode) and high-frequency, high-gain mode and
VEXTAL
• Updated Typ. of RS low-gain mode
• Updated description of RF, RS, and VPP
• Removed footnote from RF Feedback resistor
• Updated footnote for C1 C2 and RF
In table: Table 28
• Removed mention of high-frequency
• Added HGO 0, 1 information
In table: Fast internal RC Oscillator electrical specifications
• Updated FFIRC
• Updated description of ΔF
• Updated typ and max values of TJIT cycle-to-cycle jitter and TJIT Long
term jitter over 1000 cycles
• Added footnotes to TJIT cycle-to-cycle jitter and TJIT Long term jitter
over 1000 cycles
• Updated naming convention of IDDFIRC Supply current
• Added footnote to IDDFIRC Supply current
• Added footnote to column Parameter
In table: Slow internal RC oscillator (SIRC) electrical specifications
• Removed VDD Supply current in 2 MHz Mode
• Removed footnote and updated description of ΔF
• Updated footnote to FSIRC and IDDSIRC
In table: SPLL electrical specifications
• Added row for FSPLL_REF PLL Reference
• Updated naming convention throughout the table
• Updated the max value of TSPLL_LOCK Lock detector detection time
In table: Flash timing specifications — commands
• Added footnotes:
• All command times assumes ...
• For all EEPROM Emulation terms ...
• 'First time' EERAM writes after a POR ...
• Removed footnote 'Assumes 25 MHz or ...'
• Updated Max of teewr32bers
• Added parameters tquickwr and tquickwrClnup
In table: Reliability specifications
• Removed Typ. values for all parameters
• Removed footnote 'Typical values represent ... '
• Added footnote 'Any other EEE driver usage ... '
Updated QuadSPI AC specifications
Removed topic: Reliability, Safety and Security modules
In table: 12-bit ADC operating conditions
• Updated VDDA
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
92
NXP Semiconductors
Revision History
Table 57. Revision History (continued)
Rev. No.
Date
Substantial Changes
•
•
•
•
•
•
•
•
•
•
•
3
14 March 2017
4
02 June 2017
• Updated values for VREFH and VREFL to add refernce to the section
"voltage and current operating requirments" for Min and Max valaues
• Updated footnote to Typ.
• Removed footnote from RAS Analog source resistance
• Updated figure: ADC input impedance equivalency diagram
In table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL =
VSS)
• Removed rows for VTEMP_S and VTEMP25
• Updated footnote to Typ.
In table: 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL =
VSS)
• Removed rows for VTEMP_S and VTEMP25
• Removed number for TUE
• Updated footnote to Typ.
In table: Comparator with 8-bit DAC electrical specifications
• Updated Typ. of IDDLS Supply current, Low-speed mode
• Updated Typ. of tDLSB Propagation delay, Low-speed mode
• Updated Typ. of tDHSS Propagation delay, High-speed mode
• Updated tDLSS Propagation delay
• Added row for tDDAC Initialization and switching settling time
• Updated footnote
Updated section LPSPI electrical specifications
Added section: SAI electrical specifications
Updated section: Ethernet AC specifications
Added section: Clockout frequency
Added section: Trace electrical specifications
Updated table: Table 55 : Updated numbers for S32K142 and S32K148
Updated table: Table 56 : Updated numbers for S32K148
Updated Document number for 32-pin QFN in topic Obtaining package
dimensions
• In Table 3
• Updated min. value of VDD_OFF
• Added parameter IINJSUM_AF
• Updated Power mode transition operating behaviors
• Updated Power consumption
• Updated footnote to TSPLL_LOCK in SPLL electrical specifications
• In 12-bit ADC electrical characteristics
• Updated table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH =
VDDA, VREFL = VSS)
• Added typ. value to IDDA_ADC, TUE, DNL, and INL
• Added min. value to SMPLTS
• Removed footnote 'All the parameters in this table ... '
• Updated table: 12-bit ADC characteristics (3 V to 5.5 V) (VREFH =
VDDA, VREFL = VSS)
• Added typ. value to IDDA_ADC
• Removed footnote 'All the parameters in this table ... '
• In Flash timing specifications — commands updated Max. value of tvfykey to
33 μs
• In section: Block diagram, added block diagram for S32K11x series.
• Updated figure: S32K1xx product series comparison.
• In section: Selecting orderable part number , added reference to attachement
S32K_Part_Numbers.xlsx.
• In section: Ordering information
• Updated figure: Ordering information.
• In Table 1,
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
93
Revision History
Table 57. Revision History (continued)
Rev. No.
Date
Substantial Changes
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5
06 Dec 2017
• Updated note 'All the limits defined ... '
• Updated parameter 'IINJPAD_DC_ABS', 'VIN_DC', IINJSUM_DC_ABS.
In Table 3,
• Updated parameter IINJPAD_DC_OP and IINJSUM_DC_OP.
In Table 8, updated TBDs for VLVR_HYST, VLVD_HYST, and VLVW_HYST
In Power mode transition operating behaviors,
• Added VLPR → VLPS
• Added VLPS → VLPR
• Updated TBDs for VLPS → Asynchronous DMA Wakeup, STOP1 →
Asynchronous DMA Wakeup, and STOP2 → Asynchronous DMA
Wakeup
In Table 13, updated the specifications for S32K144.
Updated the attachment S32K1xx_Power_Modes _Configuration.xlsx.
In Table 25, removed CIN_A.
In Table 27,
• Updated specificatins for gmXOSC.
• Removed IDDOSC
In Table 29,
• Added parameter ΔF125.
• Removed IDDFIRC
In Table 31,
• Added parameter ΔF125.
• Removed IDDSIRC
In Table 33, removed ILPO
Updated section: Flash memory module (FTFC/FTFM) electrical
specifications
In section: 12-bit ADC operating conditions,
• Updated TBDs for IDDA_ADC and TUE in Table 41
• Updated TBDs for IDDA_ADC and TUE in Table 42
In section: QuadSPI AC specifications, updated figure 'QuadSPI output
timing (HyperRAM mode) diagram'.
In section: 12-bit ADC operating conditions, updated Table 40.
In section: CMP with 8-bit DAC electrical specifications, added note 'For
comparator IN signals adjacent ... '
In table: Table 46, minor update in footnote 6.
In table: Table 55, updated specifications for S32K146.
• Removed S32K148 from 'Caution'
• Updated figure: S32K1xx product series comparison for
• 'EEPROM emulated by FlexRAM' of S32K148 (Added content to
footnote)
• Added support for LIN protocol version 2.2 A
• In Absolute maximum ratings :
• Added note 'Unless otherwise ... '
• Added parameter 'Added note 'Tramp_MCU'
• Updated footnote for 'Tramp'
• In Voltage and current operating requirements :
• Added footnote 'VDD and VDDA must be shorted ... ' against parameter
'VDD– VDDA'
• Updated footnote 'VDD and VDDA must be shorted ...'
• In Power and ground pins
• Added diagrams for 32-QFN and 48-LQFP and footnote below the
diagrams.
• Updated footnote 'VDD and VDDA must be shorted ...'
• In Power mode transition operating behaviors :
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
94
NXP Semiconductors
Revision History
Table 57. Revision History
Rev. No.
Date
Substantial Changes
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• Added footnote 'For S32K11x – FIRC/SOSC/FIRC/LPO; For S32K14x
– FIRC/SOSC/FIRC/LPO/SPLL' to 'VLPS Mode: All clock sources
disabled'
• Updated numbers for:
• VLPR → VLPS
• VLPS → VLPR
• 'RUN → Compute operation'
• RUN → VLPS
• RUN → VLPR
In Power consumption :
• Updated specs for S32K142, S32K144, and S32K148
• Updated footnote 'Typical current numbers are indicative ...'
• Updated footnote 'The S32K148 data ...'
• Removed footnote 'Above S32K148 data is preliminary targets only'
• Added new table 'Power consumption at 3.3 V'
In General AC specifications :
• Updated max value and footnote of WFRST
• Updated symbol for not filtered pulse to 'WNFRST', updated min value,
removed max. value, and added footnote
Fixed naming conventions to align with DS in DC electrical specifications at
3.3 V Range and DC electrical specifications at 5.0 V Range
Updated specs for AC electrical specifications at 3.3 V range and AC
electrical specifications at 5 V range
In Device clock specifications :
• Updated fBUS to 48 for 11x
• Added footnote to fBUS for 14x
In External System Oscillator frequency specifications :
• Added specs for S32K11x
• Updated 'tdc_extal' for S32K14x
• Added footnote 'Frequecies below ... ' to 'fec_extal' and 'tdc_extal'
Splitted Flash timing specifications — commands for S32K14x and S32K11x
Updated Flash timing specifications — commands for S32K14x
In Reliability specifications :
• Added footnote 'Data retention period ... ' for 'tnvmretp1k' and
'tnvmretee'
• Minor update in footnote for 'nnvmwree16' 'nnvmwree256'
In QuadSPI AC specifications :
• Updated 'MCR[SCLKCFG[5]]' value to 0
• Updated 'Data Input Setup Time' HSRUN Internal DQS PAD Loopback
value to 1.6
• Updated 'Data Input Setup Time' DDR External DQS min. value to 2
• Updated 'Data Input Hold Time' DDR External DQS min. value to 20
• Upadted figure 'QuadSPI output timing (SDR mode) diagram' and
'QuadSPI input timing (HyperRAM mode) diagram'
In 12-bit ADC electrical characteristics :
• Added note 'On reduced pin packages where ... '
• Removed max. value of 'IDDA_ADC'
• Added note 'Due to triple ... '
In 12-bit ADC operating conditions, removed parameter 'ΔVDDA'
In CMP with 8-bit DAC electrical specifications :
• Updated Typ. and Max. values of 'IDDLS'
• Upadted Typ. value of 'tDHSB'
• Updated Typ. value of 'VHYST1' , 'VHYST2', and 'VHYST3'
In LPSPI electrical specifications :
• Updated 'fperiph' and 'fop', and 'tSPSCK'
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
95
Revision History
Table 57. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Updated 3.3 V numbers and added footnote against fop, tSU, ans tV in
HSRUN Mode
• Added footnote to 'tWSPSCK'
• Updated Thermal characteristics for S32K11x
6
31 Jan 2018
• Changed the representation of ARM trademark throughout.
• Removed S32K142 from 'Caution'
• In 'Key features', added the following note under 'Power management',
'Memory and memory interfaces', and 'Reliability, safety and security':
• No write or erase access to ...
• In High-level architecture diagram for the S32K14x family, added the
following footnote:
• No write or erase access to ...
• In High-level architecture diagram for the S32K11x family :
• Minor editorial update: Fixed the placement of SRAM, under 'Flash
memory controller' block
• Updated figure: S32K1xx product series comparison :
• Updated footnote 1, and added against 'HSRUN' in addition to 'HW
security module (CSEc)' and 'EEPROM emulated by FlexRAM'.
• Updated 'System RAM (including FlexRAM and MTB)' row for
S32K144, S32K146, and S32K148.
• Updated channel count for S32K116 in row '12-bit SAR ADC (1 MSPS
each)'.
• Updated Ordering information
• Updated Flash timing specifications — commands for S32K148, S32K142,
S32K146, S32K116, and S32K118.
7
19 April 2018
• Changed Caution to Notes
• Updated the wordings of Notes and removed S32K146
• Added 'Following two are the available ...'
• In 'Key features' :
• Editorial updates
• Updated the note under Power management, Memory and memory
interfaces, and Safety and security.
• Updated FlexIO under Communications interfaces
• Added ENET and SAI under Communications interfaces
• Updated Cryptographic Services Engine (CSEc) under 'Safety and
security'
• In High-level architecture diagram for the S32K14x family :
• Minor editorial updates
• Updated note 3
• In High-level architecture diagram for the S32K11x family :
• Minor editorial updates
• In figure: S32K1xx product series comparison :
• Editorial updates
• Updated Frequency for S32K14x
• Updated footnote 4
• Added footnote 5
• In Ordering information :
• Renamed section, updated the starting paragraph
• Updated the figure
• In Voltage and current operating requirements, updated the note
• In Power consumption :
• Updated specs for S32K146
• Removed section 'Modes configuration', amd moved its content under
the fisrt paragraph.
• In 12-bit ADC operating conditions :
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
96
NXP Semiconductors
Revision History
Table 57. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Fixed the typo in RSW1
• In LPSPI electrical specifications :
• Updated tLead and tLag
• Added footnote in Figure: LPSPI slave mode timing (CPHA = 0) and
Figure: LPSPI slave mode timing (CPHA = 1)
• In Thermal characteristics :
• Updated the name of table: Thermal characteristics for 32-pin QFN
and 48/64/100/144/176-pin LQFP package
• Deleted specs for RθJC for 32 QFN package
• Added 'RθJCBottom'
8
18 June 2018
• In attachement 'S32K1xx_Power_Modes _Configuration':
• Updated VLPR peripherals disabled and Peripherals Enabled use case
#1, using 4 Mhz for System clock, 2 Mhz for bus clock, and 1Mhz for
flash.
• Removed S32K116 from Notes
• In figure: S32K1xx product series comparison :
• Added note 'Availability of peripherals depends on the pin
availability ...'
• Updated 'Ambient Operation Temperature' row
• Updated 'System RAM (including FlexRAM and MTB)' row for
S32K144, S32K146, and S32K148
• In Ordering information :
• Updated figure for 'Y: Optional feature'
• Updated footnote 3
• In Power and ground pins :
• In figure 'Power diagram', updtaed VFlash frequency to 3.3 V
• In Power mode transition operating behaviors :
• Updated footnote for 'VLPS Mode: All clock sources disabled'
• In Power consumption :
• Added IDDs for S32K116
• Added VLPR Peripherals enabled use case 2 at 125 °C/Typicals
• Renamed VLPR 'Peripherals enabled' to 'Peripherals enabled use
case 1'
• Added footnote 'Data collected using RAM' to VLPR 'Peripherals
disabled' and VLPR 'Peripherals enabled use case 1'
• Updated VLPS Peripherals enabled at 25 °C/Typicals for S32K142 and
S32K144 to 40 μA and 42 μA respectively
• Added table 'VLPS additional use-case power consumption at typical
conditions'
• In DC electrical specifications at 3.3 V Range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In DC electrical specifications at 5.0 V Range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In AC electrical specifications at 3.3 V range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In AC electrical specifications at 5 V range :
• Updated naming conventions
• Added specs for GPIO-FAST pad
• In External System Oscillator electrical specifications :
• Clarified description of gmXOSC
• Updated VIL max. to 1.15 V
• In Fast internal RC Oscillator (FIRC) electrical specifications :
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
97
Revision History
Table 57. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Updated specs for TJIT Cycle-to-Cycle jitter to 300 ps
• In QuadSPI AC specifications :
• Updated specs for Tiv Data Output In-Valid Time
• In figure 'QuadSPI output timing (SDR mode) diagram', marked Invalid
area
• In CMP with 8-bit DAC electrical specifications :
• Removed '(VAIO)' from decription of VHYST0
• In LPSPI electrical specifications :
• Added note 'Undefined' in figures 'LPSPI slave mode timing (CPHA =
0)' and 'LPSPI slave mode timing (CPHA = 1)'
9
18 Sep 2018
• In attachment 'S32K1xx_Power_Modes _Configuration':
• Added separate sheet for S32K14x and S32K11x devices
• Renamed VLPS (Peripherals Enabled) to VLPS (LPTMR enabled)
• Removed Note "Technical information ..."
• In Features:
• Updated Clock interfaces for '4 – 40 MHz fast external oscillator
(SOSC)' and 'Real Time Counter'
• Added 'Up to 20 MHz TCLK and 25 MHz SWD_CLK'
• In Absolute maximum ratings : Updated footnote 3 '60 seconds lifetime ... '
• Updated title of table Thermal operating characteristics
• In Ordering information :
• Updated 'Temperature'
• Updated 'Wafer Fab and Mask revision identifier'
• In Power consumption :
• Renamed 'VLPS Peripheral enabled' to 'LPTMR enabled'
• Added IDDs for S32K118 for 85 °C, 105 °C and 125 °C
• Updated IDDs for S32K118 for 25 °C
• Added IDDs for VLPR Peripherals enabled use case 2 for S32K116
• Updated IDDs and added footnotes in table 'VLPS additional use-case
power consumption at typical conditions'
• In General AC specifications :
• Updated footnote of WFRST and WNFRST
• In External System Oscillator electrical specifications :
• Added footnote to RS
• Renamed Vpp to Vpp_XTAL and updated the description accordingly
• Added Vpp_EXTAL
• Added VSOSCOP
• Updated equation 'gm_crit = 4 ...' in footnote 1
• In External System Oscillator frequency specifications :
• Added footnote "For an ideal clock of 40 MHz, if permitted ..." to fosc_hi
max.
• In Fast internal RC Oscillator (FIRC) electrical specifications :
• Updated note "Fast internal ... "
• In LPSPI electrical specifications :
• Updated figures 'LPSPI slave mode timing (CPHA = 0)' and 'LPSPI
slave mode timing (CPHA = 1)'
10
09 May 2019
• In Notes: Added note 'Technical information for the S32K148 ... '
• In attachment 'S32K1xx_Orderable_Part_Number_List':
• Added ISELED PN
• Added PN for new package offering (48-pin LQFP S32K142; 48-pin
LQFP S32K144; 100-pin LQFP S32K148)
• Added NFC PN
• Added UA as S32K148 Standard PN
• Updated Standard Base Feature Offer
• In figure 'S32K1xx product series comparison' :
Table continues on the next page...
S32K1xx Data Sheet, Rev. 13, 04/2020
98
NXP Semiconductors
Revision History
Table 57. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Added 48-pin LQFP for S32K142 and S32K144
• Added 100-pin LQFP for S32K148, along with footnote
• In Ordering information :
• Updated 'Ordering option'
• Updated note 2
• In Thermal characteristics :
• Added values for 48-pin LQFP for S32K142 and S32K144
• Added values for 100-pin LQFP for S32K148
11
27 June 2019
• In Notes: Removed note 'Technical information for the S32K148 ... '
12
04 Feb 2020
•
•
•
•
In Notes: Added note: 'Technical information for ...'
Added S32K14xW information throughout
Removed "Under development" from the footnote number 6 in Figure 3.
Updated Trace electrical specifications to clarify that the section applies only
for ETM Trace and is supported only by S32K148.
• In Table 28, added a new footnote from fosc_hi Max entry.
• Updated Figure 21 for number 8.
• In Reliability specifications, tnvmretee is changed to tnvmretee100, and added a
new row for the parameter tnvmretee10. And footnotes are updated in this topic.
13
05 April 2020
• In LVR, LVD and POR operating requirements,
• Updated table title for S32K14xW series
• Updated values for VLVR for S32K14xW series
• In Absolute maximum ratings, updated TJ for S32K14xW series
• In Thermal operating characteristics, updated TJ for S32K14xW series
• In External System Oscillator electrical specifications, added note 'Minimum
value is shown as a reference only ... ' to Vpp_EXTAL
S32K1xx Data Sheet, Rev. 13, 04/2020
NXP Semiconductors
99
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Document Number S32K1XX
Revision 13, 04/2020
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