GTL2002
2-bit bidirectional low voltage translator
Rev. 8 — 19 August 2013
Product data sheet
1. General description
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide
high-speed voltage translation with low ON-state resistance and minimal propagation
delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate
(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional
voltage translations between 1.0 V and 5.0 V without use of a direction pin.
When the Sn or Dn port is LOW the clamp is in the ON-state and a low resistance
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn
port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by
the pull-up resistors. This functionality allows a seamless translation between higher and
lower voltages selected by the user, without the need for directional control.
All transistors have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical, SREF and DREF can be
located on any of the other two matched Sn/Dn transistors, allowing for easier board
layout. The translator's transistors provide excellent ESD protection to lower voltage
devices and at the same time protect less ESD-resistant devices.
2. Features and benefits
2-bit bidirectional low voltage translator
Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V
buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS
levels
Provides bidirectional voltage translation with no direction pin
Low 6.5 ON-state resistance (Ron) between input and output pins (Sn/Dn)
Supports hot insertion
No power supply required; will not latch up
5 V tolerant inputs
Low standby current
Flow-through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: SO8, TSSOP8 (MSOP8), VSSOP8, XQFN8
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
3. Applications
Any application that requires bidirectional or unidirectional voltage level translation
from any voltage between 1.0 V and 5.0 V to any voltage between 1.0 V and 5.0 V
The open-drain construction with no direction pin is ideal for bidirectional low voltage
(e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I2C-bus port translation to the normal
3.3 V or 5.0 V I2C-bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal
levels.
4. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
GTL2002
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
GTL2002DP
2002
TSSOP8[1]
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
GTL2002DC
2002
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
GTL2002GM
G2X[2]
XQFN8
plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6 1.6 0.5 mm
SOT902-2
GTL2002D
[1]
Also known as MSOP8.
[2]
‘X’ will change based on date code.
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature
GTL2002D
GTL2002D,112
SO8
Standard marking
* IC's tube - DSC bulk pack
2000
Tamb = 40 C to +85 C
GTL2002D
GTL2002D,118
SO8
Reel 13” Q1/T1
*Standard mark SMD
2500
Tamb = 40 C to +85 C
GTL2002DP
GTL2002DP,118
TSSOP8
Reel 13” Q1/T1
*Standard mark SMD
2500
Tamb = 40 C to +85 C
GTL2002DC
GTL2002DC,125
VSSOP8
Reel 7” Q3/T4
*Standard mark
3000
Tamb = 40 C to +85 C
GTL2002GM
GTL2002GM,125
XQFN8
Reel 7” Q3/T4
*Standard mark
4000
Tamb = 40 C to +85 C
GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
2 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
5. Functional diagram
DREF
GREF
SREF
D1
D2
S1
S2
002aac784
Fig 1.
Functional diagram
6. Pinning information
6.1 Pinning
GND
1
8
GREF
SREF
2
7
DREF
S1
3
6
D1
D2
GTL2002D
5
1
SREF
2
S1
3
S2
4
GTL2002DP
Pin configuration for SO8
Fig 3.
1
8
GREF
S1
2
7
DREF
S2
3
6
D1
GND
4
5
D2
GTL2002
Product data sheet
Pin configuration for VSSOP8
DREF
6
D1
5
D2
GREF
1
SREF
S1
7
DREF
2
6
D1
3
5
D2
002aac780
Transparent top view
Fig 5.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
GND
S2
SREF
002aac779
Fig 4.
7
GTL2002GM
terminal 1
index area
GTL2002DC
GREF
Pin configuration for TSSOP8
(MSOP8)
8
Fig 2.
8
002aac778
002aac777
4
4
S2
GND
Pin configuration for XQFN8
© NXP B.V. 2013. All rights reserved.
3 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SO8, TSSOP8, VSSOP8
XQFN8U
GND
1
4
ground (0 V)
SREF
2
1
source of reference transistor
S1
3
2
port S1
S2
4
3
port S2
D2
5
5
port D2
D1
6
6
port D1
DREF
7
7
drain of reference transistor
GREF
8
8
gate of reference transistor
7. Functional description
Refer to Figure 1 “Functional diagram”.
7.1 Function selection
Table 4.
Function selection, HIGH to LOW translation
Assuming Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
GREF[1]
DREF
SREF
Input Dn
Output Sn
Transistor
H
H
0V
X
X
off
[4]
on
H
H
VTT
H
VTT[2][4]
H
H
VTT[4]
L
L[3]
on
L
L
0 V VTT[4]
X
X
off
[1]
GREF should be at least 1.5 V higher than SREF for best translator operation.
[2]
Sn is not pulled up or pulled down.
[3]
Sn follows the Dn input LOW.
[4]
VTT is equal to the SREF voltage.
Table 5.
Function selection, LOW to HIGH translation
Assuming Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
GREF[1]
DREF
SREF
Input Sn
Output Dn
Transistor
H
H
0V
X
X
off
H
H
VTT[4]
VTT[4]
H[2]
nearly off
H
VTT
[4]
L
L[3]
on
L
0V
X
X
off
H
L
[1]
GTL2002
Product data sheet
VTT[4]
GREF should be at least 1.5 V higher than SREF for best translator operation.
[2]
Dn is pulled up to VCC through an external resistor.
[3]
Dn follows the Sn input LOW.
[4]
VTT is equal to the SREF voltage.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
4 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
8. Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side VCC through a pull-up resistor (typically 200 k). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to VCC). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 k
resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to (VCC 1.5 V),
the output of each Sn has a maximum output voltage equal to SREF and the output of
each Dn has a maximum output voltage equal to VCC.
1.8 V
1.5 V
1.2 V
1.0 V
5V
200 kΩ
totem pole or
open-drain I/O
VCORE
GND
GREF
SREF
DREF
S1
D1
S2
D2
CPU I/O
VCC
CHIPSET I/O
increase bit size
by using 10-bit GTL2010
or 22-bit GTL2000
3.3 V
VCC
S3
D3
S4
D4
S5
D5
Sn
Dn
CHIPSET I/O
002aac060
Typical bidirectional voltage translation.
Fig 6.
GTL2002
Product data sheet
Bidirectional translation to multiple higher voltage levels such as an I2C-bus
application
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Rev. 8 — 19 August 2013
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5 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
8.2 Unidirectional down translation
For unidirectional clamping, higher voltage to lower voltage, the GREF input must be
connected to DREF and both pins pulled to the higher side VCC through a pull-up resistor
(typically 200 k). A filter capacitor on DREF is recommended. Pull-up resistors are
required if the chip set I/O are open-drain. The opposite side of the reference transistor
(SREF) is connected to the processor core supply voltage. When DREF is connected
through a 200 k resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V
to (VCC 1.5 V), the output of each Sn has a maximum output voltage equal to SREF.
1.8 V
1.5 V
1.2 V
1.0 V
0.8 V
easy migration to lower voltage
as processor geometry shrinks
VCORE
CPU I/O
5V
200 kΩ
GTL2003
GND
GREF
SREF
DREF
S1
D1
S2
D2
VDD1
CHIPSET I/O
totem pole I/O
S8
D8
002aac061
Typical unidirectional HIGH-to-LOW voltage translation.
Fig 7.
Unidirectional down translation to protect low voltage processor pins
8.3 Unidirectional up translation
For unidirectional up translation, lower voltage to higher voltage, the reference transistor
is connected the same as for a down translation. A pull-up resistor is required on the
higher voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will
only pass the reference source (SREF) voltage as a HIGH when doing an up translation.
The driver on the lower voltage side only needs pull-up resistors if it is open-drain.
1.8 V
1.5 V
1.2 V
1.0 V
0.8 V
easy migration to lower voltage
as processor geometry shrinks
VCORE
CPU I/O
totem pole I/O
or open-drain
5V
200 kΩ
GTL2003
GND
GREF
SREF
DREF
S1
D1
S2
D2
S8
D8
VDD1
CHIPSET I/O
002aac062
Typical unidirectional LOW-to-HIGH voltage translation.
Fig 8.
GTL2002
Product data sheet
Unidirectional up translation to higher voltage chip sets
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Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
6 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
8.4 Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is
in the ON state to about 15 mA. This will guarantee a pass voltage of 260 mV to 350 mV.
If the current through the pass transistor is higher than 15 mA, the pass voltage will also
be higher in the ON state. To set the current through each pass transistor at 15 mA, the
pull-up resistor value is calculated as shown in Equation 1:
pull-up voltage V – 0.35 V
resistor value = -------------------------------------------------------------------------0.015 A
(1)
Table 6 summarizes resistor values for various reference voltages and currents at 15 mA
and also at 10 mA and 3 mA. The resistor value shown in the +10 % column or a larger
value should be used to ensure that the pass voltage of the transistor would be 350 mV or
less. The external driver must be able to sink the total current from the resistors on both
sides of the GTL-TVC device at 0.175 V, although the 15 mA only applies to current
flowing through the GTL-TVC device. See application note AN10145, “Bidirectional low
voltage translators” for more information.
Table 6.
Pull-up resistor values
Pull-up resistor value ()[1]
15 mA[2]
Voltage
Nominal
5.0 V
Product data sheet
341
Nominal
465
+ 10
512
3 mA[2]
%[3]
Nominal
1550
+ 10 %[3]
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
[1]
GTL2002
310
+ 10
10 mA[2]
%[3]
Calculated for VOL = 0.35 V.
[2]
Assumes output driver VOL = 0.175 V at stated current.
[3]
+ 10 % to compensate for VDD range and resistor tolerance.
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Rev. 8 — 19 August 2013
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GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
9. Limiting values
Table 7.
Limiting values[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Min
Max
Unit
voltage on pin SREF
[2]
0.5
+7.0
V
VDREF
voltage on pin DREF
[2]
0.5
+7.0
V
VGREF
voltage on pin GREF
[2]
0.5
+7.0
V
voltage on port Sn
[2]
0.5
+7.0
V
VDn
voltage on port Dn
[2]
0.5
+7.0
V
VSREF
VSn
Parameter
Conditions
IREFK
diode current on reference pins VI < 0 V
-
50
mA
ISK
diode current port Sn
VI < 0 V
-
50
mA
IDK
diode current port Dn
VI < 0 V
-
50
mA
Imax
clamp current per channel
channel in ON state
-
128
mA
Tstg
storage temperature
65
+150
C
[1]
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperature which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 150 C.
[2]
The input and output negative voltage ratings may be exceeded if the input and output clamp current
ratings are observed.
10. Recommended operating conditions
Table 8.
Recommended operating conditions
Symbol
Parameter
Conditions
VI/O
voltage on an input/output pin
Sn, Dn
Product data sheet
Max
Unit
0
5.5
V
VSREF
voltage on pin SREF
0
5.5
V
VDREF
voltage on pin DREF
0
5.5
V
VGREF
voltage on pin GREF
0
5.5
V
IPASS
pass transistor current
-
64
mA
Tamb
ambient temperature
40
+85
C
[1]
GTL2002
[1]
Min
operating in free air
VSREF VDREF 1.5 V for best results in level shifting applications.
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Rev. 8 — 19 August 2013
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8 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
11. Static characteristics
Table 9.
Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VOL
LOW-level output voltage
VDD = 3.0 V; VSREF = 1.365 V;
VSn or VDn = 0.175 V;
Iclamp = 15.2 mA
-
260
350
mV
VIK
input clamping voltage
II = 18 mA; VGREF = 0 V
-
-
1.2
V
ILI(gate)
gate input leakage current
VI = 5 V; VGREF = 0 V
-
-
5
A
Cig
input capacitance at gate
pin GREF; VI = 3 V or 0 V
-
19.4
-
pF
Cio(off)
off-state input/output capacitance
VO = 3 V or 0 V; VGREF = 0 V
[2]
-
7.4
-
pF
VO = 3 V or 0 V; VGREF = 3 V
[2]
-
18.6
-
pF
VI = 0 V; IO = 64 mA
[3]
Cio(on)
on-state input/output capacitance
ON-state resistance
Ron
VGREF = 4.5 V
-
3.5
5
VGREF = 3 V
-
4.4
7
VGREF = 2.3 V
-
5.5
9
-
67
105
VI = 0 V; IO = 30 mA;
VGREF = 1.5 V
[3]
-
9
15
VI = 2.4 V; IO = 15 mA;
VGREF = 4.5 V
[3]
-
7
10
VI = 2.4 V; IO = 15 mA;
VGREF = 3 V
[3]
-
58
80
VI = 1.7 V; IO = 15 mA;
VGREF = 2.3 V
[3]
-
50
70
VGREF = 1.5 V
[1]
All typical values are measured at Tamb = 25 C.
[2]
Cio(on) maximum of 30 pF and Cio(off) maximum of 15 pF is guaranteed by design.
[3]
Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two (Sn or Dn) terminals.
GTL2002
Product data sheet
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Rev. 8 — 19 August 2013
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GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
12. Dynamic characteristics
12.1 Dynamic characteristics for translator-type application
Table 10. Dynamic characteristics for translator-type application
Tamb = 40 C to +85 C; Vref = 1.365 V to 1.635 V; VDD1 = 3.0 V to 3.6 V; VDD2 = 2.36 V to 2.64 V;
GND = 0 V; tr = tf 3.0 ns. Refer to Figure 11.
Symbol
Parameter
Conditions
tPLH
LOW to HIGH
propagation delay
Sn to Dn; Dn to Sn
tPHL
HIGH to LOW
propagation delay
Sn to Dn; Dn to Sn
Min
Typ[1]
Max
Unit
[2]
0.5
1.5
5.5
ns
[2]
0.5
1.5
5.5
ns
[1]
All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V; Vref = 1.5 V and Tamb = 25 C.
[2]
Propagation delay guaranteed by characterization.
VI
input
VM
VM
GND
test jig output
HIGH-to-LOW,
LOW-to-HIGH
tPHL0
tPLH0
VM
VM
VDD2
tPHL
tPHL1
DUT output
HIGH-to-LOW,
LOW-to-HIGH
tPLH
tPLH1
VM
VOL
VDD2
VM
VOL
002aac789
VM = 1.5 V; VI = GND to 3.0 V.
Fig 9.
GTL2002
Product data sheet
The input (Sn) to output (Dn) propagation delays
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GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
12.2 Dynamic characteristics for CBT-type application
Table 11. Dynamic characteristics for CBT-type application
Tamb = 40 C to +85 C; VGREF = 5 V 0.5 V; GND = 0 V; tr = tf 3.0 ns; CL = 50 pF.
Symbol
tPD
[1]
Parameter
Conditions
[1]
propagation delay
Min
Typ
Max
Unit
-
-
250
ps
This parameter is warranted by the ON-state resistance at GREF = 4.5 V, but is not directly production
tested. The propagation delay is based on the RC time constant of the typical ON-state resistance of the
switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
3.0 V
input
1.5 V
1.5 V
tPLH
tPHL
0V
VOH
output
1.5 V
1.5 V
VOL
002aab664
tPD = the maximum of tPLH or tPHL.
VM = 1.5 V; VI = GND to 3.0 V.
Fig 10. Input (Sn) to output (Dn) propagation delays
GTL2002
Product data sheet
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Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
11 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
13. Test information
VDD1
VDD2
200 kΩ
DREF
VDD2
150 kΩ
GREF
VDD2
150 kΩ
150 kΩ
D2
D1
DUT
SREF
S2
S1
test jig
Vref
pulse
generator
002aac790
Fig 11. Load circuit for translator-type applications
RL
from output under test
500 Ω
CL
50 pF
S1
7V
open
GND
RL
500 Ω
002aab667
Test data are given in Table 12.
CL = load capacitance; includes jig and probe capacitance.
RL = load resistance.
Fig 12. Load circuit for CBT-type application
Table 12.
Test
tPD
GTL2002
Product data sheet
Test data
Load
Switch
CL
RL
50 pF
500
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Rev. 8 — 19 August 2013
open
© NXP B.V. 2013. All rights reserved.
12 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
14. Package outline
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Fig 13. Package outline SOT96-1 (SO8)
GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
13 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
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GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
14 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
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GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
15 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
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GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
16 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
17 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and 14
Table 13.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 14.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 17.
GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
18 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Soldering: PCB footprints
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GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
19 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
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GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
20 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
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GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
21 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
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GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
22 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
17. Abbreviations
Table 15.
GTL2002
Product data sheet
Abbreviations
Acronym
Description
CBT
Cross Bar Technology
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
ESD
ElectroStatic Discharge
GTL
Gunning Transceiver Logic
HBM
Human Body Model
I/O
Input/Output
I2C-bus
Inter-Integrated Circuit bus
LVTTL
Low Voltage Transistor-Transistor Logic
NMOS
Negative-channel Metal-Oxide Semiconductor
RC
Resistor Capacitor network
TTL
Transistor-Transistor Logic
TVC
Transceiver Voltage Clamps
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
23 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
18. Revision history
Table 16.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
GTL2002 v.8
20130819
Product data sheet
-
GTL2002 v.7
Modifications:
•
Section 2 “Features and benefits”:
– 10th bullet item: deleted phrase “150 V MM per JESD22-A115”
– 11th bullet item changed from “XQFN8U” to “XQFN8”
•
Table 1 “Ordering information”:
– removed type number “GTL2002DP/Q900”
– added column “Topside marking”
– GTL2002GM package name, description, and version changed per PCN #201108001F01:
from “XQFN8U, plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based;
body 1.6 1.6 0.5 mm (SOT902-1)”
to “XQFN8, plastic extremely thin quad flat package; no leads; 8 terminals;
body 1.6 1.6 0.5 mm (SOT902-2)”
•
Table 2 “Ordering options”:
– Added columns “Orderable part number”, “Package”, “Packing method”, and “Minimum order
quantity”
– Column “Topside mark” is moved to Table 1
•
Figure 3 “Pin configuration for TSSOP8 (MSOP8)” updated:
removed type number “GTL2002DP/Q900”
•
Figure 5 changed from “XQFN8U” (SOT902-1) to “XQFN8” (SOT902-2),
(per PCN #201108001F01)
•
•
Table 3 “Pin description” modified: column heading changed from “XQFN8U” to “XQFN8”
•
•
Section 15 “Soldering of SMD packages” updated
Figure 16 changed from “SOT902-1 (XQFN8U)” to “SOT902-2 (XQFN8)”,
per PCN #201108001F01
Added Section 16 “Soldering: PCB footprints”
GTL2002 v.7
20090702
Product data sheet
-
GTL2002 v.6
GTL2002 v.6
20071221
Product data sheet
-
GTL2002 v.5
GTL2002 v.5
20070813
Product data sheet
-
GTL2002 v.4
GTL2002 v.4
20060829
Product data sheet
-
GTL2002 v.3
GTL2002 v.3
(9397 750 13058)
20040929
Product data sheet
-
GTL2002 v.2
GTL2002 v.2
(9397 750 11349)
20030401
Product data
ECN 853-2214 29603
dated 2003 Feb 28
GTL2002 v.1
GTL2002 v.1
(9397 750 07417)
20000216
Product specification
ECN 853-2214 24367
dated 2000 Aug 16
-
GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
24 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
GTL2002
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
25 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
GTL2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 August 2013
© NXP B.V. 2013. All rights reserved.
26 of 27
GTL2002
NXP Semiconductors
2-bit bidirectional low voltage translator
21. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
8
8.1
8.2
8.3
8.4
9
10
11
12
12.1
12.2
13
14
15
15.1
15.2
15.3
15.4
16
17
18
19
19.1
19.2
19.3
19.4
20
21
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Function selection. . . . . . . . . . . . . . . . . . . . . . . 4
Application design-in information . . . . . . . . . . 5
Bidirectional translation . . . . . . . . . . . . . . . . . . 5
Unidirectional down translation. . . . . . . . . . . . . 6
Unidirectional up translation . . . . . . . . . . . . . . . 6
Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended operating conditions. . . . . . . . 8
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Dynamic characteristics for translator-type
application . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Dynamic characteristics for CBT-type
application . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Test information . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Soldering of SMD packages . . . . . . . . . . . . . . 17
Introduction to soldering . . . . . . . . . . . . . . . . . 17
Wave and reflow soldering . . . . . . . . . . . . . . . 17
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18
Soldering: PCB footprints. . . . . . . . . . . . . . . . 19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Contact information. . . . . . . . . . . . . . . . . . . . . 26
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 19 August 2013
Document identifier: GTL2002
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