GTL2002DP-T

NXP bidirectional low-voltage translators GTL20xx Low cost bidirectional voltage Headline translation without directional control Unlike level-shifting bus switches, which only translate between fixed voltages, these bidirectional low-voltage translators can translate any voltage between 1 and 5 V to any other voltage between 1 and 5 V. They also reduce ON-state resistance and minimize propagation delay. Key features 4 o directional control required for N bidirectional voltage translations 4 ow RON resistance (6.5 Ω) between L input and output pins (Sn/Dn) 4 ropagation delay: 1.5 ns (typ) P 4 hannel off-state capacitance: 7.5 pF C 4 ery low (5 µA) standby current V 4 o power supply required – prevents N latch-ups 4 ery small QFN package options V Applications 4 ni- and bidirectional translation for U any voltage between 1 and 5 V 4 idirectional translation of lowB voltage and legacy I2C-bus signals 4 hifting processor sideband I/O S signals between GTL and LVTTL/TTL levels The NXP family of Gunning Transceiver Logic (GTL) bidirectional low-voltage translators includes the 22-bit GTL2000, the 2-bit GTL2002, the 8-bit GTL2003, and the 10-bit GTL2010. Each delivers high-speed translation between different voltage levels with low ON-state resistance and minimal propagation delay. They can translate any voltage between 1 and 5 V to any other voltage between 1 and 5 V as long as there is at least 1 V difference between the voltage levels, so they offer greater design flexibility than level-shifting bus switches, which only translate between fixed voltages. Each GTL20xx device includes NMOS pass transistors (Sn and Dn pins) with a common gate (GREF pin) and a reference transistor (SREF and DREF pins). When one of the Sn or Dn ports is low, the clamp is in the ON-state and the Sn and Dn ports are linked through a low ON-resistance connection. Assuming the higher voltage is applied on the Dn port, when the Dn port is high, the voltage on the Sn port is limited to the voltage set by SREF. When the Sn port is high, the Dn port is pulled to a higher voltage by a pull-up resistor. This set-up enables seamless translation between user-selected voltages, without the need for directional control signals. All transistors have the same electrical characteristics so deviation from one output to another in voltage and propagation delay is kept to a minimum. The transistors also provide excellent ESD protection in case the low-voltage devices that are less resistant to ESD. The translators can be used in any application that requires uni- or bidirectional voltage translation for voltage levels between 1 and 5 V. The open-drain construction, which eliminates the need for directional control, makes the translators ideal for designs that combine low-voltage (1.0 to 1.8 V) and legacy (3.3 and/or 5.5 V) I2Cbus signals. The translators can change I2C-bus signal levels at speeds up to 3.4 MHz. The translators can also be used in designs that combine GTL and LVTTL/ TTL signals, shifting processor sideband I/O signals between voltage levels. Bidirectional voltage translation To configure the translators for bidirectional clamping, the GREF input must be connected to DREF and both pins must be pulled to the high-side VCC through a pull-up resistor (typically 200 k Ω). A filter capacitor on DREF is recommended. The CPU output can be set as totem pole or open drain (pull-up resistors may be required), as can the chipset output (pull-up resistors are required to pull the Dn outputs to VCC). No directional control is needed if both outputs are set as open drain. If either output is set to totem pole, however, there may be highto-low contentions in either direction. To prevent this, set data as unidirectional or use 3-stateable outputs with a mechanism for direction control. The opposite side of SREF is connected to the CPU power-supply voltage. When DREF is connected through a 200-k Ω resistor to VCC and SREF is set between 1.0 and VCC minus 1.5 V, the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn has a maximum output voltage equal to the voltage of the pull-up resistor (3.3 and/or 5 V). Unidirectional voltage translation The same configuration can be used for one-way voltage translation, either up or down. For down-only translation, if the chipset I/O are open drain, pull-up resistors are required. For up-only translation, a pull-up resistor is required on the high-side voltage (Dn). This is because the translator will only pass the reference source voltage (SREF) as a high when doing up-translation. The driver on the low-side voltage only needs a pull-up resistor if it is set as open drain. For more information on using the GTL20xx family, please refer to Application Note AN10145 at www.nxp. com/interface. GND SREF S1 S2 S3 S4 S5 S6 S7 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40 39 GREF DREF D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 S4 S5 Sn D4 D5 Dn S3 D3 Increase bit size by using 8-bit GTL2003 or 10-bit GTL2010 or 22-bit GTL2000 3.3 V VCORE S REF S1 CPU I/O S2 D2 GTL2002 GTL2003 1.8 V 1.5 V 1.2 V 1.0 V GND GREF D REF D1 Chipset I/O VCC GTL2002 5V Totem Pole or Open Drain I/O GTL2010 200 K S8 10 S9 11 S10 12 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 13 14 15 16 17 18 19 20 21 22 23 GTL2000 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC Chipset I/O S22 24 GTL20xx pinout diagram Typical configuration for bidirectional voltage translation Ordering information Package SO SSOP TSSOP HVQFN DHVQFN VSSOP XQFN Container Tube T&R Tube T&R Tube T&R T&R T&R T&R T&R GTL2000 --GTL2000DL GTL2000DL-T GTL2000DGG GTL2000DGG-T ----GTL2002 GTL2002D GTL2002D-T ---GTL2002DP-T --GTL2002DC-T GTL2002GM-T GTL2003 ----GTL2003PW GTL2003PW-T -GTL2003BQ-T --GTL2010 ----GTL2010PW GTL2010PW-T GTL2010BS-T ---- Note: In Europe and Asia, for tube orders, add “, 112” (e.g. GTL2010PW, 112), and for tape and reel orders, replace “-T” with “, 118” (e.g. GTL2010PW, 118). w ww.nxp.com © 2007 NXP N.V. All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof d oes not convey nor imply any license under patent or other industrial or intellectual property rights. Date of release: March 2007 Document order number: 9397 750 15911 Printed in the USA