HEC4040BT,118

HEF4040B 12-stage binary ripple counter Rev. 10 — 7 December 2021 Product data sheet 1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Tolerant of slow clock rise and fall time Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V Specified from -40 °C to +85 °C 3. Applications • • • Frequency dividing circuits Time delay circuits Control counters 4. Ordering information Table 1. Ordering information Type number HEF4040BT Package Temperature range Name Description Version -40 °C to +85 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4040B Nexperia 12-stage binary ripple counter 5. Functional diagram CP MR 10 T 11 12-STAGE COUNTER CD 9 7 6 5 3 2 4 13 12 14 15 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad589 Fig. 1. Functional diagram CP T FF 1 Q T Q CD FF 2 Q FF 12 Q T Q CD Q CD MR Q0 Q1 Q11 001aae615 Fig. 2. Logic diagram CP input 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 MR input Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad587 Fig. 3. Timing diagram HEF4040B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 2 / 11 HEF4040B Nexperia 12-stage binary ripple counter 6. Pinning information 6.1. Pinning HEF4040B Q11 1 16 VDD Q5 2 15 Q10 Q4 3 14 Q9 Q6 4 13 Q7 Q3 5 12 Q8 Q2 6 11 MR Q1 7 10 CP VSS 8 9 Q0 001aae614 Fig. 4. Pin configuration SOT109-1 (SO16) 6.2. Pin description Table 2. Pin description Symbol Pin Description VSS 8 ground supply voltage Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q 8, Q9, Q10, Q11 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 parallel output CP 10 clock input (HIGH-to-LOW edge-triggered) MR 11 master reset input (active HIGH) VDD 16 supply voltage 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current Tstg storage temperature Tamb ambient temperature Ptot total power dissipation P power dissipation HEF4040B Product data sheet Conditions VI < -0.5 V or VI > VDD + 0.5 V Min Max Unit -0.5 +18 V - ±10 mA -0.5 VO < -0.5 V or VO > VDD + 0.5 V per output All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 VDD + 0.5 V - ±10 mA - ±10 mA - 50 mA -65 +150 °C -40 +85 °C - 500 mW - 100 mW © Nexperia B.V. 2021. All rights reserved 3 / 11 HEF4040B Nexperia 12-stage binary ripple counter 8. Recommended operating conditions Table 4. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +85 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 ms/V VDD = 10 V - - 0.5 ms/V VDD = 15 V - - 0.08 ms/V 9. Static characteristics Table 5. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage HIGH-level output current LOW-level output current input leakage current IDD supply current input capacitance HEF4040B Product data sheet VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Unit Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 mA VO = 4.6 V 5V - -0.52 - -0.44 - -0.36 mA VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 μA 5V - 20 - 20 - 150 μA 10 V - 40 - 40 - 300 μA 15 V - 80 - 80 - 600 μA - - - - 7.5 - - pF |IO| < 1 μA |IO| < 1 μA HIGH-level output voltage |IO| < 1 μA ILI CI Conditions |IO| < 1 μA IO = 0 A All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 4 / 11 HEF4040B Nexperia 12-stage binary ripple counter 10. Dynamic characteristics Table 6. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; unless otherwise specified; for test circuit see Fig. 6. Symbol Parameter Conditions VDD Extrapolation formula [1] tPHL HIGH to LOW propagation delay CP → Q0; see Fig. 5 5V 10 V 15 V Qn → Qn + 1 MR → Qn; see Fig. 5 tPLH LOW to HIGH propagation delay CP → Q0; see Fig. 5 Qn → Qn + 1 tt transition time tW pulse width trec recovery time fmax [1] [2] [3] maximum frequency see Fig. 5 Min Typ Max Unit 78 ns + (0.55 ns/pF)CL - 105 210 ns 34 ns + (0.23 ns/pF)CL - 45 90 ns 27 ns + (0.16 ns/pF)CL - 35 70 ns 5V [2] (0.55 ns/pF)CL - 35 70 ns 10 V [2] (0.23 ns/pF)CL - 15 30 ns 15 V [2] (0.16 ns/pF)CL - 10 20 ns 5V 63 ns + (0.55 ns/pF)CL - 90 180 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 58 ns + (0.55 ns/pF)CL - 85 170 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V [2] (0.55 ns/pF)CL - 35 70 ns 10 V [2] (0.23 ns/pF)CL - 15 30 ns 15 V [2] (0.16 ns/pF)CL - 10 20 ns 5V [3] 10 ns + (1.00 ns/pF)CL - 60 120 ns - 30 60 ns 10 V 9 ns + (0.42 ns/pF)CL 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns CP input HIGH; minimum width; see Fig. 5 5V 50 25 - ns 10 V 30 15 - ns 15 V 20 10 - ns MR input HIGH; minimum width; see Fig. 5 5V 40 20 - ns 10 V 30 15 - ns 15 V 20 10 - ns MR input; see Fig. 5 5V 40 20 - ns 10 V 30 15 - ns 15 V 20 10 - ns 5V 10 20 - MHz 10 V 15 30 - MHz 15 V 25 50 - MHz CP input; see Fig. 5 The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). th For loads other than 50 pF at the n output, use the slope given. tt is the same as tTHL and tTLH. Table 7. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation HEF4040B Product data sheet VDD Typical formula for PD (μW) 5V PD = 400 × fi + Σ(fo × CL) × VDD where: 2 10 V PD = 2000 × fi + Σ(fo × CL) × VDD 15 V PD = 5200 × fi + Σ(fo × CL) × VDD 2 2 All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 fi = input frequency in MHz, fo = output frequency in MHz, CL = output load capacitance in pF, VDD = supply voltage in V, Σ(fo × CL) = sum of the outputs. © Nexperia B.V. 2021. All rights reserved 5 / 11 HEF4040B Nexperia 12-stage binary ripple counter 10.1. Waveforms and test circuit VI VM MR input VSS tW 1/fmax trec VI VM CP input VSS tPHL tPLH VOH Q0 or Qn output VOL tW tPHL VM tTLH tPLH VOH tTHL tPHL VM Qn + 1 output VOL 001aaj763 Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Measurement points are given in Table 8. Fig. 5. Waveforms showing the propagation delays, pulse widths, recovery times, maximum clock frequency, and output transition times Table 8. Measurement points Supply voltage Input Output VDD VI VM VM 5 V to 15 V VDD or VSS 0.5VDD 0.5VDD tW VI 90 % negative pulse 90 % VM VM 10 % 0V VI 10 % tf tr tr tf 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD G VI VO DUT RT CL 001aag182 b. Test circuit Test data is given in Table 9. Definitions test circuit: CL = load capacitance, including the jig and probe capacitance; RL = load resistance, which should be equal to the output impedance of the pulse generator. Fig. 6. Test circuit for measuring switching times HEF4040B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 6 / 11 HEF4040B Nexperia 12-stage binary ripple counter Table 9. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4040B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 7 / 11 HEF4040B Nexperia 12-stage binary ripple counter 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 7. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4040B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 8 / 11 HEF4040B Nexperia 12-stage binary ripple counter 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4040B v.10 20211207 Product data sheet - HEF4040B v.9 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Section 12 added. HEF4040B v.9 20160323 Modifications: • HEF4040B v.8 20111117 Modifications: • • HEF4040B v.7 20111010 HEF4040B v.6 20091125 HEF4040B v.5 Product data sheet - HEF4040B v.8 Type number HEF4040BP (SOT38-4) removed. - HEF4040B v.7 Product data sheet - HEF4040B v.6 Product data sheet - HEF4040B v.5 20090709 Product data sheet - HEF4040B v.4 HEF4040B v.4 20090304 Product data sheet - HEF4040B_CNV v.3 HEF4040B_CNV v.3 19950101 Product specification - HEF4040B_CNV v.2 HEF4040B_CNV v.2 19950101 Product specification - - HEF4040B Product data sheet Product data sheet Legal pages updated. Changes in Section 1 and Section 2. All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 9 / 11 HEF4040B Nexperia 12-stage binary ripple counter 14. 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 10 / 11 HEF4040B Nexperia 12-stage binary ripple counter Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................4 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveforms and test circuit........................................ 6 11. Package outline.......................................................... 8 12. Abbreviations.............................................................. 9 13. Revision history..........................................................9 14. Legal information......................................................10 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 7 December 2021 HEF4040B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 7 December 2021 © Nexperia B.V. 2021. All rights reserved 11 / 11