HEF40175BP,652

HEF40175B Quad D-type flip-flop Rev. 10 — 29 November 2021 Product data sheet 1. General description The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. When LOW, MR resets all flip-flops (Qn = LOW, Qn = HIGH), independent of CP and Dn. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • • • • • • • • • Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V Specified from -40 °C to +85°C and from -40 °C to +125 °C 3. Applications • • • Shift registers Buffer/storage register Pattern generator 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF40175BT -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF40175BTT -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 HEF40175B Nexperia Quad D-type flip-flop 5. Functional diagram 4 5 D0 12 D1 D Q FF 1 CP Q D2 D Q FF 2 CP Q CD 9 1 13 D3 D Q FF 3 CP Q CD D Q FF 4 CP Q CD CD CP MR Q0 Q0 3 Q1 Q1 2 6 Q2 Q2 7 11 Q3 Q3 10 14 15 001aae569 Fig. 1. Functional diagram D0 D1 D Q FF 1 CP Q D2 D Q FF 2 CP Q CD D3 D Q FF 3 CP Q CD D Q FF 4 CP Q CD CD CP MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 001aae571 Fig. 2. Logic diagram HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 2 / 13 HEF40175B Nexperia Quad D-type flip-flop 6. Pinning information 6.1. Pinning HEF40175B MR 1 16 VDD Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 VSS 8 9 HEF40175B CP MR 1 16 VDD Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 VSS 8 001aae570 Fig. 3. 9 CP 001aan211 Pin configuration SOT109-1 (SO16) Fig. 4. Pin configuration SOT403-1 (TSSOP16) 6.2. Pin description Table 2. Pin description Symbol Pin Description MR 1 master reset input (active LOW) Q0, Q1, Q2, Q3 2, 7, 10, 15 buffered output Q0, Q1, Q2, Q3 3, 6, 11, 14 complementary buffered output D0, D1, D2, D3 4, 5, 12, 13 data input VSS 8 ground supply voltage CP 9 clock input (LOW-to-HIGH edge-triggered) VDD 16 supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition. Input Output CP Dn MR Qn Qn ↑ H H H L ↑ L H L H ↓ X H no change no change X X L L H HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 3 / 13 HEF40175B Nexperia Quad D-type flip-flop 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O Min Max Unit -0.5 +18 V - ±10 mA -0.5 VDD + 0.5 - ±10 mA input/output current - ±10 mA IDD supply current - 50 mA Tstg storage temperature -65 +150 °C Tamb ambient temperature -40 +125 °C Ptot total power dissipation Tamb = -40 °C to +125 °C - 500 mW P power dissipation per output - 100 mW [1] Conditions VI < -0.5 V or VI > VDD + 0.5 V VO < -0.5 V or VO > VDD + 0.5 V [1] V For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 3 - 15 V VDD supply voltage VI input voltage 0 - VDD V Tamb ambient temperature in free air -40 - +125 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V VDD = 10 V - - 0.5 μs/V VDD = 15 V - - 0.08 μs/V HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 4 / 13 HEF40175B Nexperia Quad D-type flip-flop 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage |IO| < 1 μA |IO| < 1 μA |IO| < 1 μA VDD Tamb = -40 °C Tamb = +25 °C Tamb = +85 °C Tamb = +125 °C Unit Min Max Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 5V LOW-level output voltage |IO| < 1 μA 15 V - 0.05 - 0.05 - 0.05 - 0.05 V HIGH-level output current VO = 2.5 V 5V - -1.7 - -1.4 - -1.1 - -1.1 mA VO = 4.6 V 5V - -0.64 - -0.5 - -0.36 - -0.36 mA VO = 9.5 V 10 V - -1.6 - -1.3 - -0.9 - -0.9 mA VO = 13.5 V 15 V - -4.2 - -3.4 - -2.4 - -2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA 5V - 1.0 - 1.0 - 30 - 30 μA 10 V - 2.0 - 2.0 - 60 - 60 μA 15 V - 4.0 - 4.0 - 120 - 120 μA - - - - 7.5 - - - - pF LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF40175B Product data sheet all valid input combinations; |IO|= 0 A All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 5 / 13 HEF40175B Nexperia Quad D-type flip-flop 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C unless otherwise specified; for test circuit see Fig. 6. Symbol Parameter Conditions VDD Extrapolation formula[1] tPHL CP to Qn or Qn; see Fig. 5 5V HIGH to LOW propagation delay MR to Qn; see Fig. 5 tPLH LOW to HIGH propagation delay CP to Qn or Qn; see Fig. 5 MR to Qn; see Fig. 5 tt transition time tsu set-up time see Fig. 5 Min Typ 53 ns + (0.55 ns/pF) CL - 80 160 ns 10 V 24 ns + (0.23 ns/pF) CL - 35 70 ns 15 V 17 ns + (0.16 ns/pF) CL - 25 50 ns 5V 48 ns + (0.55 ns/pF) CL - 75 155 ns 10 V 19 ns + (0.23 ns/pF) CL - 30 65 ns 15 V 17 ns + (0.16 ns/pF) CL - 25 50 ns 5V 43 ns + (0.55 ns/pF) CL - 70 140 ns 10 V 19 ns + (0.23 ns/pF) CL - 30 65 ns 15 V 17 ns + (0.16 ns/pF) CL - 25 45 ns 5V 43 ns + (0.55 ns/pF) CL - 70 140 ns 10 V 19 ns + (0.23 ns/pF) CL - 30 65 ns 15 V 17 ns + (0.16 ns/pF) CL - 25 50 ns 5V 10 ns + (1.00 ns/pF) CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF) CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF) CL - 20 40 ns 60 30 - ns 20 10 - ns Dn to CP; see Fig. 5 5 V 10 V 15 V th hold time tW pulse width trec recovery time fmax [1] maximum frequency Max Unit 15 5 - ns +25 -5 - ns 10 V 10 0 - ns 15 V 10 0 - ns CP input LOW; minimum pulse width; see Fig. 5 5V 90 45 - ns 10 V 35 15 - ns 15 V 25 10 - ns MR input LOW; minimum pulse width; see Fig. 5 5V 80 40 - ns 10 V 30 15 - ns 15 V 20 10 - ns Dn to CP; see Fig. 5 5 V MR input; see Fig. 5 5 V 0 -30 - ns 10 V 0 -20 - ns 15 V 0 -15 - ns 5V 5 11 - MHz 10 V 15 30 - MHz 15 V 20 45 - MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formula shown (CL in pF). HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 6 / 13 HEF40175B Nexperia Quad D-type flip-flop Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter VDD dynamic power dissipation 5 V PD Typical formula for PD (μW) PD = 2000 × fi + Σ(fo × CL) × VDD where: 2 2 10 V PD = 8400 × fi + Σ(fo × CL) × VDD 15 V PD = 22500 × fi + Σ(fo × CL) × VDD 2 fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; Σ(fo × CL) = sum of the outputs. 11.1. Waveforms and test circuit VI MR input 0V VI CP input VM 0V VI Dn input 0V tPLH VOH Qn output VOL VM 10 % tPHL tPHL 90 % tTLH tTHL 001aak039 a. CP and MR to Qn propagation delays and Qn transition times 1/fmax VI VM CP input 0V tsu th tW VI Dn input VM 0V trec VI VM MR input 0V tW 001aae568 b. Minimum pulse widths for CP and MR, MR to CP recovery time, and set-up and hold time for Dn to CP VOH and VOL are typical output voltage levels that occur with the output load. Set-up and hold times are shown as positive values but may be specified as negative values. The shaded area are where input changes result in predicable output performance. Measurement points are given in Table 9. Fig. 5. Waveforms showing switching times HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 7 / 13 HEF40175B Nexperia Quad D-type flip-flop Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD tW VI 90 % negative pulse 90 % VM VM 10 % 0V VI 10 % tf tr tr tf 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveforms VDD G VI VO DUT CL RT 001aag182 b .Test circuit Test and measurement data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator; CL = Load capacitance including jig and probe capacitance. Fig. 6. Test circuit for measuring switching times Table 10. Measurement points and test data Supply voltage Input Load VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 8 / 13 HEF40175B Nexperia Quad D-type flip-flop 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig. 7. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 9 / 13 HEF40175B Nexperia Quad D-type flip-flop TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 Fig. 8. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Package outline SOT403-1 (TSSOP16) HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 10 / 13 HEF40175B Nexperia Quad D-type flip-flop 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF40175B v.10 20211129 Product data sheet - HEF40175B v.9 Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Table 4: Derating values for Ptot total power dissipation updated. HEF40175B v.9 20160321 Modifications: • HEF40175B v.8 20111121 Modifications: • • HEF40175B v.7 20110503 Product data sheet - HEF40175B v.6 HEF40175B v.6 20101214 Product data sheet - HEF40175B v.5 HEF40175B v.5 20100105 Product data sheet - HEF40175B v.4 HEF40175B v.4 20090813 Product data sheet - HEF40175B_CNV v.3 HEF40175B_CNV v.3 19950101 Product specification - HEF40175B_CNV v.2 HEF40175B_CNV v.2 19950101 Product specification - - HEF40175B Product data sheet Product data sheet - HEF40175B v.8 Type number HEF40175BP (SOT38-4) removed. Product data sheet - HEF40175B v.7 Legal pages updated. Changes in "General description", "Features and benefits" and "Applications". All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 11 / 13 HEF40175B Nexperia Quad D-type flip-flop 15. Legal information injury, death or severe property or environmental damage. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 12 / 13 HEF40175B Nexperia Quad D-type flip-flop Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................1 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 3 8. Limiting values............................................................. 4 9. Recommended operating conditions..........................4 10. Static characteristics..................................................5 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 7 12. Package outline.......................................................... 9 13. Abbreviations............................................................ 11 14. Revision history........................................................11 15. Legal information......................................................12 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 29 November 2021 HEF40175B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 29 November 2021 © Nexperia B.V. 2021. All rights reserved 13 / 13